CPS/MXWK_美芯微科/common/rom_inc/drv/drv_clock.h

/**
 ******************************************************************************
 * @copyright Copyright (C), 2016-2022, ConvenientPower. Co., Ltd.
 * @file    drv_clock.h
 * @version 1.0
 * @author  qing.cheng
 * @date    2023-03-09
 * @brief   Header file of DRV_CLOCK_H module.
 ******************************************************************************
 */

#ifndef DRV_CLOCK_H
#define DRV_CLOCK_H
#include "cmsdk_cm0.h"
#include "core_comm.h"
#include "stdbool.h"
#include "stdlib.h"
#include "string.h"
#include "clkctrl_define.h"
#include "sysctrl_define.h"
#define SYSTEM_CLOCK_CONFIG (24000000)
#define SYSTEM_6M   (6000000)
#define SYSTEM_12M  (12000000)
#define SYSTEM_24M  (24000000)

#define DELAY_CLOCK_24M   (24)
#define DELAY_CLOCK_12M   (12)
#define DELAY_CLOCK_6M    (6)

/*SYS_CTRL*/
#define SYS_CTRL_MCLK_SEL_24_6M             BIT_SET(0)
#define SYS_CTRL_GREEN_MODE                 BIT_SET(1)
#define SYS_CTRL_SLEEP_MODE                 BIT_SET(2)
#define SYS_CTRL_MASK_VIN_OV                BIT_SET(3)
#define SYS_CTRL_MASK_VIN_UV                BIT_SET(4)
#define SYS_CTRL_MASK_VIN1_OV               BIT_SET(5)
#define SYS_CTRL_MASK_VIN1_UV               BIT_SET(6)
#define SYS_CTRL_MASK_VIN2_OV               BIT_SET(7)
#define SYS_CTRL_MASK_VIN2_UV               BIT_SET(8)
#define SYS_CTRL_MASK_VBUS1_OCP             BIT_SET(9)
#define SYS_CTRL_MASK_VBUS2_OCP             BIT_SET(10)
#define SYS_CTRL_MASK_GATE1_UV              BIT_SET(11)
#define SYS_CTRL_MASK_GATE2_UV              BIT_SET(12)
#define SYS_CTRL_MASK_GATE3_UV              BIT_SET(13)
#define SYS_CTRL_MASK_V2_OCP                BIT_SET(14)
#define SYS_CTRL_MASK_I2C1                  BIT_SET(15)
#define SYS_CTRL_MASK_I2C2                  BIT_SET(16)
#define SYS_CTRL_MASK_CS1                   BIT_SET(17)
#define SYS_CTRL_MASK_CS2                   BIT_SET(18)
#define SYS_CTRL_MASK_PD1_CC_COMP_ENTRY     BIT_SET(19)
#define SYS_CTRL_MASK_PD1_CC_COMP_EXIT      BIT_SET(20)
#define SYS_CTRL_MASK_PD1_BMC               BIT_SET(21)
#define SYS_CTRL_MASK_DPDN1_OP4V            BIT_SET(22)
#define SYS_CTRL_MASK_DPDN1_2P0V            BIT_SET(23)
#define SYS_CTRL_MASK_DPDN1_1P2V            BIT_SET(24)
#define SYS_CTRL_MASK_DPDN_OV               BIT_SET(25)
#define SYS_CTRL_MASK_PD1_CCX_OV            BIT_SET(26)
#define SYS_CTRL_MASK_PD1_VCON_OC           BIT_SET(27)
#define SYS_CTRL_MASK_PD1_CCX_STATUS        BIT_SET(28)
#define SYS_CTRL_TRIM_MCU_START_DIS         BIT_SET(29)
#define SYS_CTRL_TRIM_TRIM_START_DIS        BIT_SET(30)
#define SYS_CTRL_TRIM_DIS                   BIT_SET(31)

/*PERI_CG*/
#define PERI_TIMER0_EN                      BIT_SET(0)
#define PERI_TIMER1_EN                      BIT_SET(1)
#define PERI_TIMER2_EN                      BIT_SET(2)
#define PERI_UART1_EN                       BIT_SET(3)
#define PERI_UART2_EN                       BIT_SET(4)
#define PERI_ADC_EN                         BIT_SET(5)
#define PERI_DAC_CTR_EN                     BIT_SET(6)
#define PERI_I2C_MASTER0_EN                 BIT_SET(7)
#define PERI_I2C_MASTER1_EN                 BIT_SET(8)
#define PERI_VD_EN                          BIT_SET(9)
#define PERI_PWD0_EN                        BIT_SET(10)
#define PERI_PWD1_EN                        BIT_SET(11)
#define PERI_PWD2_EN                        BIT_SET(12)
#define PERI_PWD3_EN                        BIT_SET(13)
#define PERI_PD0H_EN                        BIT_SET(14)
#define PERI_PD1H_EN                        BIT_SET(15)
#define PERI_PD0L_EN                        BIT_SET(16)
#define PERI_PD1L_EN                        BIT_SET(17)
#define PERI_UFCS0_EN                       BIT_SET(18)
#define PERI_UFCS1_EN                       BIT_SET(19)
#define PERI_SCP0_EN                        BIT_SET(20)
#define PERI_SCP1_EN                        BIT_SET(21)
#define PERI_WDOG_EN                        BIT_SET(22)
#define PERI_VIN_DIS_EN                     BIT_SET(23)

/*sys_rstreg*/
#define SYS_RSTREQ_MCU                      BIT_SET(0)
#define SYS_RSTREQ_APB                      BIT_SET(8)
#define SYS_RSTREQ_MCU_HOLD                 BIT_SET(16)
#define SYS_RSTREQ_SYSTEM                   BIT_SET(24)

#define SYS_PASSWORD    0x9A6E

typedef enum SYS_MCLK_SEL_e
{
    MCLK_SEL_24M = 0,
    MCLK_SEL_6M,

} SYS_MCLK_SEL_e;

typedef
enum drv_gpio_pimux_e
{
    PINMUX_GPIO_PIN0 = 0,
    PINMUX_GPIO_PIN1,
    PINMUX_GPIO_PIN2,
    PINMUX_GPIO_PIN3,
    PINMUX_GPIO_PIN4,
    PINMUX_GPIO_PIN5,
    PINMUX_GPIO_CC1_1,
    PINMUX_GPIO_CC2_1,
    PINMUX_GPIO_CC1_2,
    PINMUX_GPIO_CC2_2,
    PINMUX_GPIO_FB1,
    PINMUX_GPIO_COMP1,
    PINMUX_GPIO_FB2,
    PINMUX_GPIO_COMP2,
    PINMUX_GPIO_VFB,
    PINMUX_GPIO_IFB,
    PINMUX_PIN_MAX,
} drv_gpio_pimux_e;

/*
  * @brief  drv_clkctrl_sys_ctrl_config
  * @param  config
  * @note  word used to strl sysclock , mcu sleep ,wake
  * @retval
*/
__forceinline void drv_clkctrl_sys_ctrl_config(uint32_t config)
{
    REG_CLKCTRL_SYS_CTRL->word = config;
}

/*
  * @brief  drv_clkctrl_sys_ctrl_mask_clr
  * @param  config
  * @note  null
  * @retval null
*/
__forceinline void drv_clkctrl_sys_ctrl_mask_clr(uint32_t clr)
{
    REG_CLKCTRL_SYS_CTRL->word &= ~(clr);
}


/*
  * @brief  drv_clkctrl_sys_ctrl_mask_set
  * @param  value
  * @note  null
  * @retval null
*/
__forceinline void drv_clkctrl_sys_ctrl_mask_set(uint32_t value)
{
    REG_CLKCTRL_SYS_CTRL->word |= value;
}


/*
  * @brief  drv_clkctrl_sys_ctrl_config
* @param  mclk_sel ��0:24M MCLK,1:6M MCLK��
  * @note
  * @retval
*/
__forceinline void drv_clkctrl_sys_ctrl_mclk_set(uint8_t mclk_sel)
{
    REG_CLKCTRL_SYS_CTRL->bf.mclk_sel = mclk_sel;
}

/*
  * @brief  drv_clkctrl_sys_ctrl_mclk_get
  * @param  null
  * @note
  * @retval 24M/6M
*/
__forceinline uint32_t drv_clkctrl_sys_ctrl_mclk_get(void)
{
    uint32_t sysclk_buf[2] = {SYSTEM_24M, SYSTEM_6M};
    return sysclk_buf[REG_CLKCTRL_SYS_CTRL->bf.mclk_sel];
}

/*
  * @brief  drv_clkctrl_peri_cg_en
  * @param  value
  * @note  null
  * @retval null
*/
__forceinline void drv_clkctrl_peri_cg_en(uint32_t value)
{
    REG_CLKCTRL_PERI_CG->word = value;
}



/*
  * @brief  drv_clkctrl_peri_cg_mask_clr
  * @param  clr
  * @note  null
  * @retval null
*/
__forceinline void drv_clkctrl_peri_cg_mask_clr(uint32_t clr)
{
    REG_CLKCTRL_PERI_CG->word &= ~(clr);
}

/*
  * @brief  drv_clkctrl_peri_cg_mask_set
  * @param  value
  * @note  null
  * @retval null
*/
__forceinline void drv_clkctrl_peri_cg_mask_set(uint32_t value)
{
    REG_CLKCTRL_PERI_CG->word |= value;
}


/*
  * @brief  drv_clkctrl_sys_streq
  * @param  value
  * @note  null
  * @retval null
*/
__forceinline void drv_clkctrl_sys_streq(uint32_t value)
{
    REG_CLKCTRL_PERI_CG->word = value;
}


/*
  * @brief  drv_clkctrl_pin_mul_set
  * @param  pin_mode
  * @note  null
  * @retval null
*/
__forceinline void drv_clkctrl_pin_mul_set(uint32_t pin_mode)
{
    REG_CLKCTRL_PIN_MUL_SET->word = pin_mode;

}

/*
  * @brief  drv_clkctrl_pin_mul_mask_clr
  * @param  pin
  * @param  pin_clr
  * @note  null
  * @retval null
*/
__forceinline void drv_clkctrl_pin_mul_mask_clr(uint8_t pin, uint8_t pin_clr)
{
    REG_CLKCTRL_PIN_MUL_SET->word &= ~(pin_clr << (pin << 1));
}

/*
  * @brief  drv_clkctrl_pin_mul_mask_set
  * @param  pin
  * @param  pin_mode
  * @note  null
  * @retval null
*/
__forceinline void drv_clkctrl_pin_mul_mask_set(uint8_t pin, uint8_t pin_mode)
{
    REG_CLKCTRL_PIN_MUL_SET->word |= (pin_mode << (pin << 1));
}

/*
  * @brief  drv_clkctrl_mem_config
  * @param  word
  * @note  null
  * @retval null
*/
__forceinline void drv_clkctrl_mem_config(uint32_t word)
{
    REG_CLKCTRL_MEM->word = word;
}

/*
  * @brief  drv_clkctrl_mem_read
  * @param  word
  * @note  null
  * @retval null
*/
__forceinline uint8_t  drv_clkctrl_mem_read(void)
{
    return (REG_CLKCTRL_MEM->word & 0xff);;
}


/*
  * @brief  drv_clkctrl_dtest_config
  * @param  word
  * @note  null
  * @retval null
*/
__forceinline void drv_clkctrl_dtest_config(uint32_t word)
{
    REG_CLKCTRL_DTEST->word = word;
}

/*
  * @brief  drv_clkctrl_mbist_config
  * @param  word
  * @note  null
  * @retval null
*/
__forceinline void drv_clkctrl_mbist_config(uint32_t word)
{
    REG_CLKCTRL_MBIST->word = word;
}


/*
  * @brief  drv_clkctrl_password ��pw_hit��
  * @param  null
  * @note  null
  * @retval null
*/
__forceinline void drv_clkctrl_password(void)
{
    REG_CLKCTRL_CLKCTRL->word = SYS_PASSWORD;

}


/*
  * @brief  drv_clkctrl_filter
  * @param  filter_value
  * @note  null
  * @retval null
*/
__forceinline void drv_clkctrl_filter1(uint32_t filter_value)
{
    REG_CLKCTRL_FILTER->word = filter_value;
}


/*
  * @brief  drv_baudrate_vld_skew
  * @param  value
  * @note  fcs/vfcp train baud rate valid range config based on 115200 bps.
            standard 115200 is 104cycle in 12MHz, config this reg to set the valid range x=104 +/- vlld_skew.
            57600 range = x*2, 38400 range=x*3, 19200 range=x*6.
  * @retval null
*/
__forceinline void drv_baudrate_vld_skew(uint8_t value)
{
    REG_CLKCTRL_BAUDRATE->word = value;
}

/*******add 8860*****/
/*
  * @brief  drv_pin_mul_set1_mask_clr
  * @param  clr
  * @note  null
  * @retval null
*/
__forceinline void drv_pin_mul_set1_mask_clr(uint32_t clr)
{
    REG_CLKCTRL_PIN_MUL_SET1->word &= ~(clr);
}

/*
  * @brief  drv_pin_mul_set1_mask_set
  * @param  value
  * @note  null
  * @retval null
*/
__forceinline void drv_pin_mul_set1_mask_set(uint32_t value)
{
    REG_CLKCTRL_PIN_MUL_SET1->word |= value;
}


/*
  * @brief  drv_sys_stat_read
  * @param  word
  * @note  null
  * @retval null
*/
__forceinline uint8_t  drv_sys_stat_read(void)
{
    return (REG_CLKCTRL_SYS_STAT->word & 0x01);
}

/*
  * @brief  drv_mcu_start_flag_read
  * @param  word
  * @note  null
  * @retval null
*/
__forceinline uint32_t  drv_mcu_start_flag_read(uint32_t word)
{
    return (REG_CLKCTRL_MCU_START_FLAG->word & 0x01);
}

/*
  * @brief  drv_trim_start_flag_read
  * @param  word
  * @note  null
  * @retval null
*/
__forceinline uint32_t  drv_trim_start_flag_read(uint32_t word)
{
    return (REG_CLKCTRL_TRIM_START_FLAG->word & 0x01);
}


#endif