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163 lines
3.2 KiB
163 lines
3.2 KiB
4 months ago
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/**
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******************************************************************************
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* @copyright Copyright (C), 2016-2022, ConvenientPower. Co., Ltd.
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* @file drv_dma.h
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* @version 1.0
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* @author qing.cheng
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* @date 2022-10-31
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* @brief Header file of DRV_DMA_H module.
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******************************************************************************
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*/
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#ifndef _DRV_DMA_H_
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#define _DRV_DMA_H_
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#include "core_comm.h"
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#include "dma_define.h"
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#include "dma1_define.h"
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#include "adc_define.h"
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#include "pd0_define.h"
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#include "scp_define.h"
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#include "ufcs_define.h"
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#include "pd_define.h"
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#include "scp1_define.h"
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#include "ufcs1_define.h"
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#define DMA_ADDR_WORD_SET(cfg_buf, addr)\
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do{\
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cfg_buf[0] = (uint32_t)(addr) & 0xFF;\
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cfg_buf[1] = ((uint32_t)(addr) >> 8) & 0xFF;\
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cfg_buf[2] = ((uint32_t)(addr) >> 16) & 0xFF;\
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cfg_buf[3] = ((uint32_t)(addr) >> 24) & 0xFF;\
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}while(0)
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#define DMA_CFG_WORD_SET(cfg_buf, dma_buf_len, ctrl_byte)\
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do{\
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cfg_buf[0] = 0x00;\
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cfg_buf[1] = 0x00;\
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cfg_buf[2] = dma_buf_len;\
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cfg_buf[3] = ctrl_byte;\
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}while(0)
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/**
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* @brief disable dma0 chn
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* @note
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* @retval None
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*/
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#define drv_dma0_done_clr(chn_index)\
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do{\
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REG_DMA_DMA_DONE_CLR->bf.value = chn_index;\
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}while(0)
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/*
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* @brief drv_dma0_chn_enable
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* @param chn_index
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* @note
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* @retval
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*/
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#define drv_dma0_chn_enable(chn_index)\
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do{\
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REG_DMA_CHL_ENABLE->bf.value = chn_index;\
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}while(0)
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/*
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* @brief drv_dma0_ctrl_base_ptr
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* @param base_ptr
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* @note
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* @retval
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*/
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#define drv_dma0_ctrl_base_ptr(base_ptr)\
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do{\
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REG_DMA_CTRL_BASE_PTR->bf.value = base_ptr;\
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}while(0)
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/*
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* @brief drv_dma0_done_int_mask
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* @param base_ptr
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* @note
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* @retval
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*/
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#define drv_dma0_done_int_mask(chn_index)\
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do{\
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REG_DMA_DMADONE_INT_MASK->bf.value = chn_index;\
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}while(0)
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/*
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* @brief drv_dma0_done_int_mask
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* @param base_ptr
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* @note
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* @retval
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*/
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#define drv_dma0_done_int(chn_index)\
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do{\
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REG_DMA_DMADONE_INT->bf.value = chn_index;\
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}while(0)
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/***************DMA1******************************/
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/**
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* @brief disable dma0 chn
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* @note
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* @retval None
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*/
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#define drv_dma1_done_clr(chn_index)\
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do{\
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REG_DMA1_DMA_DONE_CLR->bf.value = chn_index;\
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}while(0)
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/*
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* @brief drv_dma1_chn_enable
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* @param chn_index
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* @note
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* @retval
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*/
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#define drv_dma1_chn_enable(chn_index)\
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do{\
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REG_DMA1_CHL_ENABLE->bf.value = chn_index;\
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}while(0)
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/*
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* @brief drv_dma1_ctrl_base_ptr
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* @param base_ptr
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* @note
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* @retval
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*/
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#define drv_dma1_ctrl_base_ptr(base_ptr)\
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do{\
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REG_DMA1_CTRL_BASE_PTR->bf.value = base_ptr;\
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}while(0)
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/*
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* @brief drv_dma1_done_int_mask
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* @param base_ptr
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* @note
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* @retval
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*/
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#define drv_dma1_done_int_mask(chn_index)\
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do{\
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REG_DMA1_DMADONE_INT_MASK->bf.value = chn_index;\
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}while(0)
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/*
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* @brief drv_dma1_done_int_mask
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* @param base_ptr
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* @note
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* @retval
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*/
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#define drv_dma1_done_int(chn_index)\
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do{\
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REG_DMA1_DMADONE_INT->bf.value = chn_index;\
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}while(0)
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#endif
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