CPS/MXWK_美芯微科/common/rom_inc/drv/drv_pd_phy.h

/**
 ******************************************************************************
 * @copyright Copyright (C), 2016-2022, ConvenientPower. Co., Ltd.
 * @file    drv_pd_phy.h
 * @version 1.0
 * @author  qing.cheng
 * @date    2022-11-03
 * @brief   Header file of DRV_PD_PHY_H module.
 ******************************************************************************
 */
#ifndef _DRV_PD_PHY_H_
#define _DRV_PD_PHY_H_
#include "core_comm.h"
#include "pd0_define.h"
#include "pd_define.h"
#include "extint_define.h"
#include "analog_define.h"
#include "drv_analog.h"
#define PD_INT_WAKE_FLAG    (0x10000)

#define PD_STATUS_RX_SOP        (0x08)
#define PD_STATUS_RX_SOP1       (0x10)
#define PD_STATUS_RX_SOP2       (0x20)
#define PD_STATUS_RX_SOP1_DB    (0x40)
#define PD_STATUS_RX_SOP2_DB    (0x80)

//Type C Interrupt Flag
//bit0:tx_dma_sreq
//bit1:rx_dma_sreq
//bit2:rx_crc_chk
//bit3:collision
//bit4:retryfail
//bit5:hardfail
//bit6:hardrst
//bit7:softrst
//bit8:goodcrcsent
//bit9:hardsent
//bit10:txsent
//bit11:pd_ccx_ovp
//bit12:pd_vcon_oc
//bit13:pd_status_activity

#define PD_INT_FLAG_TX_DMA_SREQ             (0x01)
#define PD_INT_FLAG_RX_DMA_SREQ             (0x02)
#define PD_INT_FLAG_RX_CRC_CHK              (0x04)
#define PD_INT_FLAG_COLLISION               (0x08)
#define PD_INT_FLAG_TX_RETRY_FAIL           (0x10)
#define PD_INT_FLAG_TX_HARD_FAIL            (0x20)
#define PD_INT_FLAG_RX_HARD_RESET           (0x40)
#define PD_INT_FLAG_RX_SOFT_RESET           (0x80)
#define PD_INT_FLAG_TX_GOODCRC_SENT         (0x100)
#define PD_INT_FLAG_TX_HARD_SENT            (0x200)
#define PD_INT_FLAG_TX_SENT                 (0x400)
#define PD_INT_FLAG_PD_CCX_OVP              (0x800)
#define PD_INT_FLAG_PD_VCON_OC              (0x1000)
#define PD_INT_FLAG_STATUS_ACTIVITY         (0x2000)


typedef enum PD_CCX_DETACH_e
{
    NOT_CC_DETACH = 0,
    CC1_DETACH,
    CC2_DETACH,
    CC1_CC2_DETACH,

} PD_CCX_DETACH_e;


/*********************PD0*********************/
/*
* @brief   pd wake int
* @param    en:1
* @retval   null
*/
#define drv_pd0_int_wake_en(x) \
        do{\
            REG_EXTINT_PD0_VWAKE_INT->bf.en = x;\
        }while(0)



/*
* @brief   pd ccx_states
* @param    en:1
* @retval   null
*/
#define drv_pd0_int_ccx_states_en(x) \
        do{\
            REG_EXTINT_PD0_CCX_STAT_INT->bf.en = x;\
        }while(0)



/*
* @brief   pd wake mask
* @param    en:1
* @retval   null
*/
#define drv_pd0_int_wake_mask(x) \
        do{\
            REG_EXTINT_PD0_VWAKE_INT->bf.mask = x;\
        }while(0)

/*
* @brief   pd wake mask
* @param    en:1
* @retval   null
*/
#define drv_pd0_int_wake_clr() \
        do{\
            REG_EXTINT_PD0_VWAKE_INT->bf.clr = 1;\
        }while(0)



/*
* @brief   pd wake mask
* @param    en:1
* @retval   null
*/
#define drv_pd0_int_mask(x) \
        do{\
              REG_PD0_INT_MASK->bf.value = x;\
        }while(0)

/*
* @brief   pd wake val
* @param    en:1
* @retval   null
*/
#define drv_pd0_int_get_wake_val() \
        (REG_EXTINT_PD0_VWAKE_INT->word)

/*
* @brief   pd int_flag
* @param    en:1
* @retval   null
*/
#define drv_pd0_int_flag()\
        (REG_PD0_INT_FLAG->word)





/*
* @brief   pd int_flag clr
* @param    en:1
* @retval   null
*/
#define drv_pd0_int_flag_clr(x)\
        do{\
            REG_PD0_INT_FLAG->bf.value = x;\
        }while(0)

/*
* @brief   pd meas cc1
* @param    en:1
* @retval   null
*/
#define drv_pd0_sw1_meas_cc1(x) \
        do{\
            REG_PD0_SW1->bf.meas_cc1 = x;\
        }while(0)

/*
* @brief   pd meas cc2
* @param    en:1
* @retval   null
*/
#define drv_pd0_sw1_meas_cc2(x) \
        do{\
            REG_PD0_SW1->bf.meas_cc2 = x;\
        }while(0)

/*
* @brief   Turn on the VCONN current to CC1 pin
* @param    en:1
* @retval   null
*/
#define drv_pd0_sw1_vcoon_cc1(x) \
        do{\
            REG_PD0_SW1->bf.vconn_cc1 = x;\
        }while(0)

/*
* @brief   Turn on the VCONN current to CC2 pin
* @param    en:1
* @retval   null
*/
#define drv_pd0_sw1_vcoon_cc2(x) \
        do{\
            REG_PD0_SW1->bf.vconn_cc2 = x;\
        }while(0)

/*
* @brief   Apply host pull up current to CC1 pin
* @param    en:1
* @retval   null
*/
#define drv_pd0_sw1_pu_en1(x) \
        do{\
            REG_PD0_SW1->bf.pu_en1 = x;\
        }while(0)

/*
* @brief   Apply host pull up current to CC2 pin
* @param    en:1
* @retval   null
*/
#define drv_pd0_sw1_pu_en2(x) \
        do{\
            REG_PD0_SW1->bf.pu_en2 = x;\
        }while(0)



/*
* @brief   enable CC1 comparator to  measure the voltage on CC1
* @param    en:1
* @retval   null
*/
#define drv_pd0_sw1_comp_en_cc1(x) \
        do{\
            REG_PD0_SW1->bf.comp_en_cc1 = x;\
        }while(0)
/*
* @brief   enable CC2 comparator to  measure the voltage on CC2
* @param    en:1
* @retval   null
*/
#define drv_pd0_sw1_comp_en_cc2(x) \
        do{\
            REG_PD0_SW1->bf.comp_en_cc2 = x;\
        }while(0)
/*
* @brief  Select BMC transceiver on CC1 pin.
* @param    en:1
* @retval   null
*/
#define drv_pd0_sw2_txcc1(x) \
        do{\
            REG_PD0_SW2->bf.txcc1= x;\
        }while(0)

/*
* @brief   Select BMC transceiver on CC2 pin.
* @param    en:1
* @retval   null
*/
#define drv_pd0_sw2_txcc2(x) \
        do{\
            REG_PD0_SW2->bf.txcc2= x;\
        }while(0)

/*
* @brief   sends a GoodCRC acknowledge packet back to the relevant SOP
* @param    en:1
* @retval   null
*/
#define drv_pd0_sw2_auto_crc(x) \
        do{\
            REG_PD0_SW2->bf.auto_crc= x;\
        }while(0)


/*
* @brief   used for GoodCRC ack packet(Port Data Role bit), For SOP: 1:SRC, 0:SNK
* @param    en:1
* @retval   null
*/
#define drv_pd0_sw2_data_role(x) \
        do{\
            REG_PD0_SW2->bf.datarole= x;\
        }while(0)


/*
* @brief   specrev
00=Revision 1.0
01=Revision 2.0
10=Revision 3.0
11=Do not use
* @param    en:1
* @retval   null
*/
#define drv_pd0_sw2_specrec(x) \
        do{\
            REG_PD0_SW2->bf.specrev = x;\
        }while(0)




/*
* @brief  used for GoodCRC ack packet(Port Power Role bit), For SOP: 1:SRC, 0:SNK
* @param    en:1
* @retval   null
*/
#define drv_pd0_sw2_power_role(x) \
        do{\
            REG_PD0_SW2->bf.powerrole = x;\
        }while(0)

/*
* @brief  1: enable TX
* @param    en:1
* @retval   null
*/
#define drv_pd0_ctrl_tx_start(x) \
        do{\
             REG_PD0_CTRL->bf.tx_start = x;\
        }while(0)

/*
* @brief 0: sop, 1: sop1, 2: sop2, 3: sop1_db, 4: sop2_db
* @param    en:1
* @retval   null
*/
#define drv_pd0_ctrl_tx_sop(x) \
        do{\
             REG_PD0_CTRL->bf.tx_sop = x;\
        }while(0)


/*
* @brief //10=pd3.0 ,11=pd2.0
* @param    en:1
* @retval   null
*/
#define drv_pd0_ctrl_n_retry(x) \
        do{\
             REG_PD0_CTRL->bf.n_retries = x;\
        }while(0)

/*
* @brief
//0: no current
//1: 80ua - default usb power
//2: 180ua - medium current mode: 1.5a
//3: 330ua - high current mode: 3a
* @param    en:1
* @retval   null
*/
#define drv_pd0_ctrl_host_cur(x) \
        do{\
             REG_PD0_CTRL->bf.host_cur = x;\
        }while(0)




/*
* @brief 1:enable sop packets
* @param    en:1
* @retval   null
*/
#define drv_pd0_ctrl_en_sop(x) \
        do{\
             REG_PD0_CTRL->bf.en_sop = x;\
        }while(0)


/*
* @brief 1:enable sop1 packets
* @param    en:1
* @retval   null
*/
#define drv_pd0_ctrl_en_sop1(x) \
        do{\
             REG_PD0_CTRL->bf.en_sop1 = x;\
        }while(0)



/*
* @brief 1:enable sop2 packets
* @param    en:1
* @retval   null
*/
#define drv_pd0_ctrl_en_sop2(x) \
        do{\
             REG_PD0_CTRL->bf.en_sop2 = x;\
        }while(0)

/*
* @brief 1:enable sop'_debug packets
* @param    en:1
* @retval   null
*/
#define drv_pd0_ctrl_en_sop1db(x) \
        do{\
             REG_PD0_CTRL->bf.en_sop1db = x;\
        }while(0)


/*
* @brief 1:enable sop''_debug packets
* @param    en:1
* @retval   null
*/
#define drv_pd0_ctrl_en_sop2db(x) \
        do{\
             REG_PD0_CTRL->bf.en_sop2db = x;\
        }while(0)


/*
* @brief /1:enable sop packets auto crc independently
* @param    en:1
* @retval   null
*/
#define drv_pd0_ctrl_en_sop_auto_crc(x) \
        do{\
             REG_PD0_CTRL->bf.en_sop_auto_crc = x;\
        }while(0)


/*
* @brief /1:enable sop' packets auto crc independently
* @param    en:1
* @retval   null
*/
#define drv_pd0_ctrl_en_sop1_auto_crc(x) \
        do{\
             REG_PD0_CTRL->bf.en_sop1_auto_crc = x;\
        }while(0)


/*
* @brief /1:enable sop' packets auto crc independently
* @param    en:1
* @retval   null
*/
#define drv_pd0_ctrl_en_sop2_auto_crc(x) \
        do{\
             REG_PD0_CTRL->bf.en_sop2_auto_crc = x;\
        }while(0)

/*
* @brief 1:Sent BIST Mode 01s pattern for testing
* @param    en:1
* @retval   null
*/
#define drv_pd0_ctrl_bist_mode(x) \
        do{\
             REG_PD0_CTRL->bf.bist_mode2 = x;\
        }while(0)



/*
* @brief send a soft reset packet
* @param    en:1
* @retval   null
*/
#define drv_pd0_ctrl_send_soft_reset(x) \
        do{\
             REG_PD0_CTRL->bf.send_softrst = x;\
        }while(0)



/*
* @brief 1=send a hard reset packet (highest priority)
* @param    en:1
* @retval   null
*/
#define drv_pd0_ctrl_send_hard_reset(x) \
        do{\
             REG_PD0_CTRL->bf.send_hardrst = x;\
        }while(0)


/*
* @brief enable wake detection functionality
* @param    en:1
* @retval   null
*/
#define drv_pd0_ctrl_auto_retry(x) \
        do{\
             REG_PD0_CTRL->bf.auto_retry = x;\
        }while(0)


/*
* @brief//bist_sopset
* @param    en:1
* @retval   null
*/
#define drv_pd0_ctrl_bist_sopset(x) \
        do{\
             REG_PD0_CTRL->bf.bist_always_on = x;\
        }while(0)

/*
* @brief enable wake detection functionality
* @param    en:1
* @retval   null
*/
#define drv_pd0_ctrl_wake_en(x) \
        do{\
             REG_PD0_CTRL->bf.wake_en = x;\
        }while(0)

/*
* @brief   pd sw_reset
* @param    en:1
* @retval   null
*/
#define drv_pd0_sw_reset(x) \
        do{\
            REG_PD0_RESET->bf.sw_reset = x;\
        }while(0)


/*
* @brief   pd pd_reset
* @param    en:1
* @retval   null
*/
#define drv_pd0_sw_pd_reset(x) \
        do{\
            REG_PD0_RESET->bf.pd_reset = x;\
        }while(0)


/*
* @brief   pd power_enable
* @param    en:1
* @retval   null
*/
#define drv_pd0_power_enable(x) \
        do{\
            REG_PD0_POWER->bf.cc_comp_en = x;\
        }while(0)


/*
* @brief   pd status
* @param    en:1
* @retval   null
*/
#define drv_pd0_status() \
        (REG_PD0_STATUS->word)



/*
* @brief   pd status cc1
* @param    en:1
* @retval   null
*/
#define drv_pd0_status_cc1() \
        (REG_PD0_STATUS->bf.cc1)


/*
* @brief   pd status cc2
* @param    en:1
* @retval   null
*/
#define drv_pd0_status_cc2() \
        (REG_PD0_STATUS->bf.cc2)



/*
* @brief   pd status rx_sop
* @param    en:1
* @retval   null
*/
#define drv_pd0_status_rx_sop() \
        (REG_PD0_STATUS->bf.rx_sop)


/*
* @brief   pd status rx_sop1
* @param    en:1
* @retval   null
*/
#define drv_pd0_status_rx_sop1() \
        (REG_PD0_STATUS->bf.rx_sop1)


/*
* @brief   pd status rx_sop2
* @param    en:1
* @retval   null
*/
#define drv_pd0_status_rx_sop2() \
        (REG_PD0_STATUS->bf.rx_sop2)





/*
* @brief   pd status word
* @param    en:1
* @retval   null
*/
#define drv_pd0_status_word() \
        (REG_PD0_STATUS->word)



/*
* @brief   pd status activiry
* @param    en:1
* @retval   null
*/
#define drv_pd0_status_activity() \
        (REG_PD0_STATUS->bf.activity)



#define drv_pd0_analog_ccx_comp(x)\
        do{\
            REG_ANALOG_PD1->bf.ccx_l_th = x;\
            REG_ANALOG_PD1->bf.ccx_h_th = (x &0x01);\
        }while(0)

#define drv_pd0_analog_cc_status() (drv_analog_pd1_cc_read())

#define drv_pd0_analog_cc1_comp_detach()\
        (REG_ANALOG_PD10->bf.cc1_comp_detach)

#define drv_pd0_analog_cc2_comp_detach()\
        (REG_ANALOG_PD10->bf.cc2_comp_detach)

/*
* @brief   drv_pd0_cfg
* @param   word
* @retval   null
*/
#define drv_pd0_cfg(word) \
        do{\
            REG_PD0_CFG->word = word;\
        }while(0)

/********************PD1***********************/
/*
* @brief   pd wake int
* @param    en:1
* @retval   null
*/
#define drv_pd1_int_wake_en(x) \
        do{\
            REG_EXTINT_PD1_VWAKE_INT->bf.en = x;\
        }while(0)



/*
* @brief   pd ccx_states
* @param    en:1
* @retval   null
*/
#define drv_pd1_int_ccx_states_en(x) \
        do{\
            REG_EXTINT_PD1_CCX_STAT_INT->bf.en = x;\
        }while(0)



/*
* @brief   pd wake mask
* @param    en:1
* @retval   null
*/
#define drv_pd1_int_wake_mask(x) \
        do{\
            REG_EXTINT_PD1_VWAKE_INT->bf.mask = x;\
        }while(0)

/*
* @brief   pd wake mask
* @param    en:1
* @retval   null
*/
#define drv_pd1_int_wake_clr() \
        do{\
            REG_EXTINT_PD1_VWAKE_INT->bf.clr = 1;\
        }while(0)



/*
* @brief   pd wake mask
* @param    en:1
* @retval   null
*/
#define drv_pd1_int_mask(x) \
        do{\
              REG_PD_INT_MASK->bf.value = x;\
        }while(0)






/*
* @brief   pd wake val
* @param    en:1
* @retval   null
*/
#define drv_pd1_int_get_wake_val() \
        (REG_EXTINT_PD1_VWAKE_INT->word)

/*
* @brief   pd int_flag
* @param    en:1
* @retval   null
*/
#define drv_pd1_int_flag()\
        (REG_PD_INT_FLAG->word)





/*
* @brief   pd int_flag clr
* @param    en:1
* @retval   null
*/
#define drv_pd1_int_flag_clr(x)\
        do{\
            REG_PD_INT_FLAG->bf.value = x;\
        }while(0)

/*
* @brief   pd meas cc1
* @param    en:1
* @retval   null
*/
#define drv_pd1_sw1_meas_cc1(x) \
        do{\
            REG_PD_SW1->bf.meas_cc1 = x;\
        }while(0)

/*
* @brief   pd meas cc2
* @param    en:1
* @retval   null
*/
#define drv_pd1_sw1_meas_cc2(x) \
        do{\
            REG_PD_SW1->bf.meas_cc2 = x;\
        }while(0)

/*
* @brief   Turn on the VCONN current to CC1 pin
* @param    en:1
* @retval   null
*/
#define drv_pd1_sw1_vcoon_cc1(x) \
        do{\
            REG_PD_SW1->bf.vconn_cc1 = x;\
        }while(0)

/*
* @brief   Turn on the VCONN current to CC2 pin
* @param    en:1
* @retval   null
*/
#define drv_pd1_sw1_vcoon_cc2(x) \
        do{\
            REG_PD_SW1->bf.vconn_cc2 = x;\
        }while(0)

/*
* @brief   Apply host pull up current to CC1 pin
* @param    en:1
* @retval   null
*/
#define drv_pd1_sw1_pu_en1(x) \
        do{\
            REG_PD_SW1->bf.pu_en1 = x;\
        }while(0)

/*
* @brief   Apply host pull up current to CC2 pin
* @param    en:1
* @retval   null
*/
#define drv_pd1_sw1_pu_en2(x) \
        do{\
            REG_PD_SW1->bf.pu_en2 = x;\
        }while(0)


/*
* @brief
01=2.6v
10=2.8v
11=3.0v
* @param    en:1
* @retval   null
*/
#define drv_pd1_sw1_ccx_wake_th(x) \
        do{\
            REG_PD_SW1->bf.ccx_wake_th= x;\
        }while(0)

/*
* @brief   enable CC1 comparator to  measure the voltage on CC1
* @param    en:1
* @retval   null
*/
#define drv_pd1_sw1_comp_en_cc1(x) \
        do{\
            REG_PD_SW1->bf.comp_en_cc1 = x;\
        }while(0)
/*
* @brief   enable CC2 comparator to  measure the voltage on CC2
* @param    en:1
* @retval   null
*/
#define drv_pd1_sw1_comp_en_cc2(x) \
        do{\
            REG_PD_SW1->bf.comp_en_cc2 = x;\
        }while(0)
/*
* @brief  Select BMC transceiver on CC1 pin.
* @param    en:1
* @retval   null
*/
#define drv_pd1_sw2_txcc1(x) \
        do{\
            REG_PD_SW2->bf.txcc1= x;\
        }while(0)

/*
* @brief   Select BMC transceiver on CC2 pin.
* @param    en:1
* @retval   null
*/
#define drv_pd1_sw2_txcc2(x) \
        do{\
            REG_PD_SW2->bf.txcc2= x;\
        }while(0)

/*
* @brief   sends a GoodCRC acknowledge packet back to the relevant SOP
* @param    en:1
* @retval   null
*/
#define drv_pd1_sw2_auto_crc(x) \
        do{\
            REG_PD_SW2->bf.auto_crc= x;\
        }while(0)


/*
* @brief   used for GoodCRC ack packet(Port Data Role bit), For SOP: 1:SRC, 0:SNK
* @param    en:1
* @retval   null
*/
#define drv_pd1_sw2_data_role(x) \
        do{\
            REG_PD_SW2->bf.datarole= x;\
        }while(0)


/*
* @brief   specrev
00=Revision 1.0
01=Revision 2.0
10=Revision 3.0
11=Do not use
* @param    en:1
* @retval   null
*/
#define drv_pd1_sw2_specrec(x) \
        do{\
            REG_PD_SW2->bf.specrev = x;\
        }while(0)




/*
* @brief  used for GoodCRC ack packet(Port Power Role bit), For SOP: 1:SRC, 0:SNK
* @param    en:1
* @retval   null
*/
#define drv_pd1_sw2_power_role(x) \
        do{\
            REG_PD_SW2->bf.powerrole = x;\
        }while(0)

/*
* @brief  1: enable TX
* @param    en:1
* @retval   null
*/
#define drv_pd1_ctrl_tx_start(x) \
        do{\
             REG_PD_CTRL->bf.tx_start = x;\
        }while(0)

/*
* @brief 0: sop, 1: sop1, 2: sop2, 3: sop1_db, 4: sop2_db
* @param    en:1
* @retval   null
*/
#define drv_pd1_ctrl_tx_sop(x) \
        do{\
             REG_PD_CTRL->bf.tx_sop = x;\
        }while(0)


/*
* @brief //10=pd3.0 ,11=pd2.0
* @param    en:1
* @retval   null
*/
#define drv_pd1_ctrl_n_retry(x) \
        do{\
             REG_PD_CTRL->bf.n_retries = x;\
        }while(0)

/*
* @brief
//0: no current
//1: 80ua - default usb power
//2: 180ua - medium current mode: 1.5a
//3: 330ua - high current mode: 3a
* @param    en:1
* @retval   null
*/
#define drv_pd1_ctrl_host_cur(x) \
        do{\
             REG_PD_CTRL->bf.host_cur = x;\
        }while(0)




/*
* @brief 1:enable sop packets
* @param    en:1
* @retval   null
*/
#define drv_pd1_ctrl_en_sop(x) \
        do{\
             REG_PD_CTRL->bf.en_sop = x;\
        }while(0)


/*
* @brief 1:enable sop1 packets
* @param    en:1
* @retval   null
*/
#define drv_pd1_ctrl_en_sop1(x) \
        do{\
             REG_PD_CTRL->bf.en_sop1 = x;\
        }while(0)



/*
* @brief 1:enable sop2 packets
* @param    en:1
* @retval   null
*/
#define drv_pd1_ctrl_en_sop2(x) \
        do{\
             REG_PD_CTRL->bf.en_sop2 = x;\
        }while(0)

/*
* @brief 1:enable sop'_debug packets
* @param    en:1
* @retval   null
*/
#define drv_pd1_ctrl_en_sop1db(x) \
        do{\
             REG_PD_CTRL->bf.en_sop1db = x;\
        }while(0)


/*
* @brief 1:enable sop''_debug packets
* @param    en:1
* @retval   null
*/
#define drv_pd1_ctrl_en_sop2db(x) \
        do{\
             REG_PD_CTRL->bf.en_sop2db = x;\
        }while(0)


/*
* @brief /1:enable sop packets auto crc independently
* @param    en:1
* @retval   null
*/
#define drv_pd1_ctrl_en_sop_auto_crc(x) \
        do{\
             REG_PD_CTRL->bf.en_sop_auto_crc = x;\
        }while(0)


/*
* @brief /1:enable sop' packets auto crc independently
* @param    en:1
* @retval   null
*/
#define drv_pd1_ctrl_en_sop1_auto_crc(x) \
        do{\
             REG_PD_CTRL->bf.en_sop1_auto_crc = x;\
        }while(0)


/*
* @brief /1:enable sop' packets auto crc independently
* @param    en:1
* @retval   null
*/
#define drv_pd1_ctrl_en_sop2_auto_crc(x) \
        do{\
             REG_PD_CTRL->bf.en_sop2_auto_crc = x;\
        }while(0)
/*
* @brief 1:Sent BIST Mode 01s pattern for testing
* @param    en:1
* @retval   null
*/
#define drv_pd1_ctrl_bist_mode(x) \
        do{\
             REG_PD_CTRL->bf.bist_mode2 = x;\
        }while(0)



/*
* @brief send a soft reset packet
* @param    en:1
* @retval   null
*/
#define drv_pd1_ctrl_send_soft_reset(x) \
        do{\
             REG_PD_CTRL->bf.send_softrst = x;\
        }while(0)



/*
* @brief 1=send a hard reset packet (highest priority)
* @param    en:1
* @retval   null
*/
#define drv_pd1_ctrl_send_hard_reset(x) \
        do{\
             REG_PD_CTRL->bf.send_hardrst = x;\
        }while(0)


/*
* @brief enable wake detection functionality
* @param    en:1
* @retval   null
*/
#define drv_pd1_ctrl_auto_retry(x) \
        do{\
             REG_PD_CTRL->bf.auto_retry = x;\
        }while(0)


/*
* @brief//bist_sopset
* @param    en:1
* @retval   null
*/
#define drv_pd1_ctrl_bist_sopset(x) \
        do{\
             REG_PD_CTRL->bf.bist_always_on = x;\
        }while(0)

/*
* @brief enable wake detection functionality
* @param    en:1
* @retval   null
*/
#define drv_pd1_ctrl_wake_en(x) \
        do{\
             REG_PD_CTRL->bf.wake_en = x;\
        }while(0)

/*
* @brief   pd sw_reset
* @param    en:1
* @retval   null
*/
#define drv_pd1_sw_reset(x) \
        do{\
            REG_PD_RESET->bf.sw_reset = x;\
        }while(0)


/*
* @brief   pd pd_reset
* @param    en:1
* @retval   null
*/
#define drv_pd1_sw_pd_reset(x) \
        do{\
            REG_PD_RESET->bf.pd_reset = x;\
        }while(0)


/*
* @brief   pd power_enable
* @param    en:1
* @retval   null
*/
#define drv_pd1_power_enable(x) \
        do{\
            REG_PD_POWER->bf.cc_comp_en = x;\
        }while(0)


/*
* @brief   pd status
* @param    en:1
* @retval   null
*/
#define drv_pd1_status() \
        (REG_PD_STATUS->word)



/*
* @brief   pd status cc1
* @param    en:1
* @retval   null
*/
#define drv_pd1_status_cc1() \
        (REG_PD_STATUS->bf.cc1)


/*
* @brief   pd status cc2
* @param    en:1
* @retval   null
*/
#define drv_pd1_status_cc2() \
        (REG_PD_STATUS->bf.cc2)



/*
* @brief   pd status rx_sop
* @param    en:1
* @retval   null
*/
#define drv_pd1_status_rx_sop() \
        (REG_PD_STATUS->bf.rx_sop)


/*
* @brief   pd status rx_sop1
* @param    en:1
* @retval   null
*/
#define drv_pd1_status_rx_sop1() \
        (REG_PD_STATUS->bf.rx_sop1)


/*
* @brief   pd status rx_sop2
* @param    en:1
* @retval   null
*/
#define drv_pd1_status_rx_sop2() \
        (REG_PD_STATUS->bf.rx_sop2)





/*
* @brief   pd status word
* @param    en:1
* @retval   null
*/
#define drv_pd1_status_word() \
        (REG_PD_STATUS->word)



/*
* @brief   pd status activiry
* @param    en:1
* @retval   null
*/
#define drv_pd1_status_activity() \
        (REG_PD_STATUS->bf.activity)



#define drv_pd1_analog_ccx_comp(x)\
        do{\
            REG_ANALOG_PD2->bf.ccx_l_th = x;\
            REG_ANALOG_PD2->bf.ccx_h_th = (x &0x01);\
        }while(0)

#define drv_pd1_analog_cc_status() (drv_analog_pd2_cc_read())


#define drv_pd1_analog_cc1_comp_detach()\
        (REG_ANALOG_PD20->bf.cc1_comp_detach)

#define drv_pd1_analog_cc2_comp_detach()\
        (REG_ANALOG_PD20->bf.cc2_comp_detach)

/*
* @brief   drv_pd1_cfg
* @param   word
* @retval   null
*/
#define drv_pd1_cfg(word) \
        do{\
            REG_PD_CFG->word = word;\
        }while(0)


__forceinline uint32_t drv_pd_analog_cc_status_get(uint8_t port)
{
    if(port == 0)
    {
        return drv_pd0_analog_cc_status();
    }
    else
    {
        return drv_pd1_analog_cc_status();
    }
}

#endif