CPS/MXWK_美芯微科/common/rom_inc/drv/drv_scp_phy.h

#ifndef DRV_SCP_PHY_H
#define DRV_SCP_PHY_H

#include "drv_clock.h"
#include "CMSDK_CM0.h"
#include "scp_define.h"
#include "scp1_define.h"


//bit0: scp_byte_get_int,
//bit1: scp_pkt_get_int,
//bit2: scp_ping_get_int,
//bit3: scp_rst_get_int,
//bit4: scp_rx_err_int,
//bit5: scp_parity_err_int

#define SCP_RX_INT_BYTE_GET         0x01
#define SCP_RX_INT_PKT_GET          0x02
#define SCP_RX_INT_PING_GET         0x04
#define SCP_RX_INT_RESET_GET        0x08
#define SCP_RX_INT_RX_ERR_GET       0x10
#define SCP_RX_INT_PARITY_ERR       0x20

#define SCP_RX_INT_ALL          (SCP_RX_INT_BYTE_GET | \
                                SCP_RX_INT_PKT_GET | \
                                SCP_RX_INT_PING_GET | \
                                SCP_RX_INT_RESET_GET | \
                                SCP_RX_INT_RX_ERR_GET | \
                                SCP_RX_INT_PARITY_ERR)

//interrupt flag
//bit0: scp_ping_sent_int,
//bit1: scp_send_done_int,
//bit2: scp_reset_done_int,
//bit3: scp_ping_clash_int,


#define SCP_TX_INT_PING_SENT         0x01
#define SCP_TX_INT_SEND_DONE         0x02
#define SCP_TX_INT_RESET_DONE        0x04
#define SCP_TX_INT_PING_CLASH        0x08

#define SCP_TX_INT_ALL          (SCP_TX_INT_PING_SENT | \
                                SCP_TX_INT_SEND_DONE | \
                                SCP_TX_INT_RESET_DONE | \
                                SCP_TX_INT_PING_CLASH)

/******************SCP0*******************/
/*
* @brief   scp phy send ping
* @param    en:1
* @retval   null
*/
#define drv_scp0_phy_send_ping() \
    do{ \
        REG_SCP_CFG->word |= 0x01; \
   }while(0)


/*
* @brief   scp phy send data
* @param    en:1
* @retval   null
*/
#define drv_scp0_phy_send_data_enable() \
    do{ \
        REG_SCP_CFG->word |= 0x04; \
   }while(0)

/*
* @brief   receive effective ping width configure
* @param   X:receive effective ping width configure, default is 10%
* @retval   null
*/
#define drv_scp0_phy_config_receive_effective(x)\
   do{\
       REG_SCP_CFG->bf.ui_time_skew = x;\
   }while(0)


/*
* @brief   drv_scp0_phy_config_wait_txping
* @param     x:00:1ui, 01:2ui, 10:3ui, 11:4ui.
* @retval   null
*/
#define drv_scp0_phy_config_wait_txping(x)\
   do{\
       REG_SCP_CFG->bf.slv_wait_txping = x;\
   }while(0)

/*
* @brief   scp phy master
* @param    en:1
* @retval   null
*/
#define drv_scp0_phy_master()\
     do{ \
            REG_SCP_CFG->bf.master_en = 1;\
       }while(0)

/*
* @brief   scp phy salve
* @param    en:1
* @retval   null
*/
#define drv_scp0_phy_salve()\
     do{ \
            REG_SCP_CFG->bf.master_en = 0; \
       }while(0)


/*
* @brief   for scp sync code width:
* @param   0:follow rx ping/data ui_legth 1:sync fixed 40us
* @retval   null
*/
#define drv_scp0_phy_follow_sync_width_enable()\
     do{ \
             REG_SCP_CFG->bf.sync_width = 0;\
       }while(0)

/*
* @brief   for scp sync code width:
* @param   0:follow rx ping/data ui_legth 1:sync fixed 40us
* @retval   null
*/
#define drv_scp0_phy_fixed_sync_width_enable()\
     do{ \
             REG_SCP_CFG->bf.sync_width = 1; \
       }while(0)


/*
* @brief   drv_scp0_phy_config_ping_low
* @param    en:1
* @retval   null
*/
#define drv_scp0_phy_config_ping_low(x)\
   do{\
       REG_SCP_CFG->bf.ping_low = x;\
   }while(0)

/**
* @param  tx int clr
* @retval None
*/
#define drv_scp0_phy_afc_mode_set(en) \
        do{ \
            REG_SCP_CFG->bf.afc_mode = en; \
        }while(0)
#define drv_scp0_phy_afc_mode_get() (REG_SCP_CFG->bf.afc_mode)

/*
* @brief   scp phy logic reset
* @param    en:1
* @retval   null
*/
#define drv_scp0_phy_logic_reset(x) \
        do{ \
           REG_SCP_RST->bf.logic = x; \
       }while(0)

/*
* @brief   drv_scp0_phy_reset_all
* @param    en:1
* @retval   null
*/
#define drv_scp0_phy_reset_all(x) \
        do{ \
           REG_SCP_RST->bf.all = x; \
       }while(0)

/**
* @brief  scp send data
* @note
* @param  void
* @retval None
*/
#define drv_scp0_phy_send_data(x) \
        do{ \
            REG_SCP_TX_DATA->word = x; \
        }while(0)
/**
* @brief  scp recive data
* @note
* @param  void
* @retval None
*/
#define drv_scp0_phy_rx_data() \
        (REG_SCP_RX_DATA->word & 0xff)


/**
* @brief  check is crc passed
* @note    0:right 1:false
* @param  void
* @retval None
*/
#define drv_scp0_phy_is_crc_ok()\
        (REG_SCP_CRC_RX->word & 0x01)

/**
* @param  mask: tx int mask
* @retval None
*/
#define drv_scp0_phy_set_tx_int_mask(mask)\
    (REG_SCP_TX_INT_MASK->word = (mask))



/**
* @param  mask: rx int mask
* @retval None
*/
#define drv_scp0_phy_set_rx_int_mask(mask)\
    (REG_SCP_RX_INT_MASK->word = (mask))


/**
* @param  rx int get
* @retval None
*/
#define drv_scp0_phy_get_rx_int_flag()\
    (REG_SCP_RX_INT_FLAG->word & 0xff)


/**
* @param  rx int clr
* @retval None
*/
#define drv_scp0_phy_get_rx_int_clr_flag(clr)\
        do{ \
            REG_SCP_RX_INT_FLAG->word = clr; \
        }while(0)



/**
* @param  tx int get
* @retval None
*/
#define drv_scp0_phy_get_tx_int_flag()\
    (REG_SCP_TX_INT_FLAG->word & 0x3f)


/**
* @param  tx int clr
* @retval None
*/
#define drv_scp0_phy_get_tx_int_clr_flag(clr) \
        do{ \
            REG_SCP_TX_INT_FLAG->word = clr; \
        }while(0)

#define drv_scp0_config_rx_reset_width(UI)\
         do{\
            REG_SCP_RESET_WIDTH->word = UI;\
         }while(0)

/******************SCP1*******************/
/*
* @brief   scp phy send ping
* @param    en:1
* @retval   null
*/
#define drv_scp1_phy_send_ping() \
    do{ \
        REG_SCP1_CFG->word |= 0x01; \
   }while(0)


/*
* @brief   scp phy send data
* @param    en:1
* @retval   null
*/
#define drv_scp1_phy_send_data_enable() \
    do{ \
        REG_SCP1_CFG->word |= 0x04; \
   }while(0)

/*
* @brief   receive effective ping width configure
* @param   X:receive effective ping width configure, default is 10%
* @retval   null
*/
#define drv_scp1_phy_config_receive_effective(x)\
   do{\
       REG_SCP1_CFG->bf.ui_time_skew = x;\
   }while(0)


/*
* @brief   drv_scp1_phy_config_wait_txping
* @param     x:00:1ui, 01:2ui, 10:3ui, 11:4ui.
* @retval   null
*/
#define drv_scp1_phy_config_wait_txping(x)\
   do{\
       REG_SCP1_CFG->bf.slv_wait_txping = x;\
   }while(0)

/*
* @brief   scp phy master
* @param    en:1
* @retval   null
*/
#define drv_scp1_phy_master()\
     do{ \
            REG_SCP1_CFG->bf.master_en = 1;\
       }while(0)

/*
* @brief   scp phy salve
* @param    en:1
* @retval   null
*/
#define drv_scp1_phy_salve()\
     do{ \
            REG_SCPREG_SCP1_CFG_CFG->bf.master_en = 0; \
       }while(0)


/*
* @brief   for scp sync code width:
* @param   0:follow rx ping/data ui_legth 1:sync fixed 40us
* @retval   null
*/
#define drv_scp1_phy_follow_sync_width_enable()\
     do{ \
             REG_SCP1_CFG->bf.sync_width = 0;\
       }while(0)

/*
* @brief   for scp sync code width:
* @param   0:follow rx ping/data ui_legth 1:sync fixed 40us
* @retval   null
*/
#define drv_scp1_phy_fixed_sync_width_enable()\
     do{ \
             REG_SCP1_CFG->bf.sync_width = 1; \
       }while(0)


/*
* @brief   drv_scp1_phy_config_ping_low
* @param    en:1
* @retval   null
*/
#define drv_scp1_phy_config_ping_low(x)\
   do{\
       REG_SCP1_CFG->bf.ping_low = x;\
   }while(0)

/**
* @param  tx int clr
* @retval None
*/
#define drv_scp1_phy_afc_mode_set(en) \
        do{ \
            REG_SCP1_CFG->bf.afc_mode = en; \
        }while(0)
#define drv_scp1_phy_afc_mode_get() (REG_SCP1_CFG->bf.afc_mode)

/*
* @brief   scp phy logic reset
* @param    en:1
* @retval   null
*/
#define drv_scp1_phy_logic_reset(x) \
        do{ \
           REG_SCP1_RST->bf.logic = x; \
       }while(0)

/*
* @brief   drv_scp1_phy_reset_all
* @param    en:1
* @retval   null
*/
#define drv_scp1_phy_reset_all(x) \
        do{ \
           REG_SCP1_RST->bf.all = x; \
       }while(0)

/**
* @brief  scp send data
* @note
* @param  void
* @retval None
*/
#define drv_scp1_phy_send_data(x) \
        do{ \
            REG_SCP1_TX_DATA->word = x; \
        }while(0)
/**
* @brief  scp recive data
* @note
* @param  void
* @retval None
*/
#define drv_scp1_phy_rx_data() \
        (REG_SCP1_RX_DATA->word & 0xff)


/**
* @brief  check is crc passed
* @note    0:right 1:false
* @param  void
* @retval None
*/
#define drv_scp1_phy_is_crc_ok()\
        (REG_SCP1_CRC_RX->word & 0x01)

/**
* @param  mask: tx int mask
* @retval None
*/
#define drv_scp1_phy_set_tx_int_mask(mask)\
    (REG_SCP1_TX_INT_MASK->word = (mask))



/**
* @param  mask: rx int mask
* @retval None
*/
#define drv_scp1_phy_set_rx_int_mask(mask)\
    (REG_SCP1_RX_INT_MASK->word = (mask))


/**
* @param  rx int get
* @retval None
*/
#define drv_scp1_phy_get_rx_int_flag()\
    (REG_SCP1_RX_INT_FLAG->word & 0xff)


/**
* @param  rx int clr
* @retval None
*/
#define drv_scp1_phy_get_rx_int_clr_flag(clr)\
        do{ \
            REG_SCP1_RX_INT_FLAG->word = clr; \
        }while(0)



/**
* @param  tx int get
* @retval None
*/
#define drv_scp1_phy_get_tx_int_flag()\
    (REG_SCP1_TX_INT_FLAG->word & 0x3f)


/**
* @param  tx int clr
* @retval None
*/
#define drv_scp1_phy_get_tx_int_clr_flag(clr) \
        do{ \
            REG_SCP1_TX_INT_FLAG->word = clr; \
        }while(0)

#define drv_scp1_config_rx_reset_width(UI)\
         do{\
            REG_SCP1_RESET_WIDTH->word = UI;\
         }while(0)
#endif