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CPS/MXWK_美芯微科/common/rom_inc/protocol/task_scp_prl.h

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初始代码
4 months ago
#ifndef TASK_SCP_PRL_H
#define TASK_SCP_PRL_H
#include "task_scp_phy.h"
#define REG_ATTR_RESV 0x00
#define REG_ATTR_R 0x01
#define REG_ATTR_W 0x02
#define REG_ATTR_M 0x04 /* Multibyte R/W register */
#define REG_ATTR_RW (REG_ATTR_R | REG_ATTR_W)
#define REG_ATTR_MR (REG_ATTR_M | REG_ATTR_R)
#define REG_ATTR_MW (REG_ATTR_M | REG_ATTR_W)
#define REG_ATTR_MRW (REG_ATTR_M | REG_ATTR_RW)
/******************?J???????*****************/
#define R 1
#define RW 2
#define RC 3
#define R_ATTRIBUTE (R|RW)
#define MULTIBYTE 0X04
#define SBRWR 0x0B //??????
#define SBRRD 0x0C //??????
#define MBRWR 0x1B //??????????
#define MBRRD 0x1C //??????????
#define SCP_CMD_ACK 0x08
#define SCP_CMD_NACK 0x03
#define SCP_CMD_ACK_MASK 0x0f
#define SCP_ACK_ERR_MASK 0x80
#define SCP_CMD_RW_MASK 0x0f
/*
* SCP message format
*
* Single byte register write
* host: SBRWR(1) + ADDR(1) + DATA(1) + CRC(1)
* device: ACK(1) + CRC(1)
*
* Single byte register read
* host: SBRRD(1) + ADDR(1 ) + CRC(1)
* device: ACK(1) + DATA(1) + CRC(1)
*
* Multibyte register write
* host: MBRWR(1) + ADDR(1) + LEN(1) + DATA(LEN) + CRC(1)
* device: ACK(1) + CRC(1)
*
* Multibyte register read
* host: MBRRD(1) + ADDR(1) + LEN(1)
* device: ACK(1) + DATA(LEN) + CRC(1)
*/
#define SCP_HOST_MSG_CMD_OFFSET 0x00
#define SCP_HOST_MSG_ADDR_OFFSET 0x01
#define SCP_HOST_MSG_LEN_OFFSET 0x02
#define SCP_HOST_MSG_SBRWR_DATA_OFFSET 0x02
#define SCP_HOST_MSG_MBRWR_DATA_OFFSET 0x03
#define SCP_DEV_MSG_ACK_OFFSET 0x00
#define SCP_DEV_MSG_DATA_OFFSET 0x01
#define SCP_MULTI_BYTE_DATA_MAX_LEN 16
/*
* Adapter type information
*/
#define SCP_ADP_TYPE0 0x7e
#define SCP_ADP_TYPE0_STANDARD_SCP_MASK BIT_SET(7)
#define SCP_ADP_TYPE0_UNDETACH_CABLE_MASK BIT_SET(6)
#define SCP_ADP_TYPE0_TYPE_A_MASK BIT_SET(5)
#define SCP_ADP_TYPE0_TYPE_B_MASK BIT_SET(4)
#define SCP_ADP_TYPE0_B_SC_MASK BIT_SET(3)
#define SCP_ADP_TYPE0_B_NON_LVC_MASK BIT_SET(2)
#define SCP_ADP_TYPE0_PORT_TYPE_MASK (BIT_SET(1) | BIT_SET(0))
#define SCP_ADP_TYPE0_PORT_A 0x00
#define SCP_ADP_TYPE0_PORT_C 0x01
#define SCP_ADP_TYPE1 0x80
#define SCP_ADP_TYPE1_STANDARD_SCP_MASK BIT_SET(7)
#define SCP_ADP_TYPE1_TYPE_B_MASK BIT_SET(4)
#define SCP_ADP_TYPE1_PORT_TYPE_MASK (BIT_SET(1) | BIT_SET(0))
#define SCP_ADP_TYPE1_PORT_A 0x00
#define SCP_ADP_TYPE1_PORT_C 0x01
/* Vendor defined version */
#define SCP_COMPILEDVER_H 0x7c
#define SCP_COMPILEDVER_L 0x7d
/* SCP version xx.yy.zz */
#define SCP_FWVER_H 0x8a
#define SCP_FWVER_L 0x8b
#define SCP_FWVER_L_YYZZ(yy, zz) (((yy) << 4) | (zz))
/*
* SCP A(FCP) device registers
*/
#define FCP_DVCTYPE 0x00
#define FCP_DVCTYPE_5V2A_9V1P67A_12V1P25A 0x00
#define FCP_DVCTYPE_5V2A_9V2A_12V2A 0x01
#define FCP_DVCTYPE_5P2V3A_9V3A_12V3A_15V2P66A_20V2A 0x06
#define FCP_DVCTYPE_5V2A_9V2A_12V2A_15V3A_20V3P25A 0x09
/* SCP specification version */
#define FCP_SPEC_VER 0x01
#define FCP_SPEC_VER_1_30 0x22 /* SCP1.30G */
#define FCP_SCNTL 0x02
#define FCP_SSTAT 0x03
#define FCP_SSTAT_CRCRX_MASK BIT_SET(1)
#define FCP_SSTAT_PARRX_MASK BIT_SET(0)
#define FCP_ID_OUI_0 0x04
#define FCP_ID_OUI_1 0x05
#define FCP_CAPABILITIES 0x20
#define FCP_CAPABILITIES_CONST_PWR_MASK BIT_SET(1)
#define FCP_CAPABILITIES_DISCRETE_VOLTAGE_MASK BIT_SET(0)
#define FCP_DISCRETE_CAPABILITIES0 0x21
#define FCP_DISCRETE_CAPABILITIES0_5V_9V 0x01
#define FCP_DISCRETE_CAPABILITIES0_5V_9V_12V 0x02
#define FCP_MAX_PWR 0x22
#define FCP_MAX_PWR_VAL(p) (p * 2) /* in unit of W */
#define FCP_ADAPTER_STATUS 0x28
#define FCP_ADAPTER_STATUS_UVP_MASK BIT_SET(3)
#define FCP_ADAPTER_STATUS_OVP_MASK BIT_SET(2)
#define FCP_ADAPTER_STATUS_OCP_MASK BIT_SET(1)
#define FCP_ADAPTER_STATUS_OTP_MASK BIT_SET(0)
#define FCP_VOUT_STATUS 0x29 /* in units of 100mV */
#define FCP_VOUT_STATUS_VAL(mv) ((mv) / 100)
#define FCP_OUTPUT_CONTROL 0x2b
#define FCP_OUTPUT_CONTROL_DP_DETECT_DIS_MASK BIT_SET(4)
#define FCP_OUTPUT_CONTROL_VI_CFG_ENBALE_MASK BIT_SET(0)
#define FCP_VOUT_CONFIG 0x2c /* in units of 100mV */
#define FCP_VOUT_CONFIG_VAL(mv) ((mv) / 100)
#define FCP_IOUT_CONFIG 0x2d /* in units of 100mA */
#define FCP_IOUT_CONFIG_VAL(ma) ((ma) / 100)
#define FCP_OUT_CONFIG_MAX_NUM 16
#define FCP_DISCRETE_CAPABILITIES 0x2f
#define FCP_DISCRETE_CAPABILITIES_V_MASK (BIT_SET(7) | BIT_SET(6) | BIT_SET(5) | BIT_SET(4))
#define FCP_DISCRETE_CAPABILITIES_V_SHIFT 4
#define FCP_DISCRETE_CAPABILITIES_I_MASK (BIT_SET(3) | BIT_SET(2) | BIT_SET(1) | BIT_SET(0))
#define FCP_DISCRETE_CAPABILITIES_I_SHIFT 0
#define FCP_DISCRETE_CAPABILITIES_VAL(n) (((n) << FCP_DISCRETE_CAPABILITIES_V_SHIFT) | (n))
#define FCP_OUTPUT_V0 0x30 /* through 0x3f, in units of 100mV */
#define FCP_OUTPUT_V(n) (FCP_OUTPUT_V0 + (n))
#define FCP_OUTPUT_V_STEP 100
#define FCP_OUTPUT_V_VAL(mv) ((mv) / FCP_OUTPUT_V_STEP)
#define FCP_OUTPUT_UVP0 0x40 /* through 0x4f, in units of 100mV */
#define FCP_OUTPUT_UVP(n) (FCP_OUTPUT_UVP0 + (n))
#define FCP_OUTPUT_UVP_STEP 100
#define FCP_OUTPUT_UVP_VAL(mv) ((mv) / FCP_OUTPUT_UVP_STEP)
#define FCP_OUTPUT_I0 0x50 /* through 0x5f, in units of 100mA */
#define FCP_OUTPUT_I(n) (FCP_OUTPUT_I0 + (n))
#define FCP_OUTPUT_I_STEP 100
#define FCP_OUTPUT_I_VAL(ma) ((ma) / FCP_OUTPUT_I_STEP)
/*
* SCP B device registers
*/
#define SCP_B_ADP_TYPE 0x81
#define SCP_B_ADP_TYPE_STD_B 0x10
#define SCP_VENDER_ID_H 0x82
#define SCP_VENDER_ID_L 0x83
#define SCP_MODULE_ID_H 0x84
#define SCP_MODULE_ID_L 0x85
#define SCP_SERIAL_NO_H 0x86 /* year: 2015 + value */
#define SCP_SERIAL_NO_L 0x87 /* week */
#define SCP_CHIP_ID 0x88
#define SCP_HWVER 0x89
#define SCP_ADP_B_TYPE1 0x8d
#define SCP_ADP_B_TYPE1_25W_IWATT 0x00 /* iwatt 5v5a, lvc */
#define SCP_ADP_B_TYPE1_25W_RICH1 0x01 /* richtek1 5v5a, lvc */
#define SCP_ADP_B_TYPE1_25W_RICH2 0x03 /* richtek2 5v5a, lvc */
#define SCP_ADP_B_TYPE1_40W 0x02 /* 10v4a 11v3a, lvc+sc+hv */
#define SCP_ADP_B_TYPE1_40W_1 0x07 /* 10v4a, lvc+sc+hv */
#define SCP_ADP_B_TYPE1_20W 0x03 /* 10v2a 10v1.8a, sc+hv */
#define SCP_ADP_B_TYPE1_65W_MAX 0x04 /* 20v3.25a, lvc+sc+hv */
#define SCP_ADP_B_TYPE1_65W 0x05 /* 20v3.25a, sc+hv */
#define SCP_ADP_B_TYPE1_65W_1 0x08 /* 20v3.25a, sc+hv */
#define SCP_ADP_B_TYPE1_40W_BANK 0x06 /* 10v4a, lvc+sc+hv */
#define SCP_ADP_B_TYPE1_40W_CAR 0x09 /* 10v4a, lvc+sc+hv */
#define SCP_ADP_B_TYPE1_22P5W 0x0a /* 10v2.25a, sc+hv */
#define SCP_ADP_B_TYPE1_22P5W_BANK 0x0b /* wifi pro 5v4.5a 10v2a */
#define SCP_ADP_B_TYPE1_22P5W_CAR 0x0c /* 10v2.25a, sc+hv */
#define SCP_ADP_B_TYPE1_66W 0x0d /* 11v6a, lvc+sc+hv */
#define SCP_ADP_B_TYPE1_66W_CAR 0x0e /* 11v6a */
/* Qiantang River double port adapter typeC+typeA */
#define SCP_ADP_B_TYPE1_QTR_C_60W 0x0f /* 10v4a, 20v3a, lvc+sc+hv */
#define SCP_ADP_B_TYPE1_QTR_C_40W 0x10 /* 10v4a, lvc+sc+hv */
#define SCP_ADP_B_TYPE1_QTR_A_40W 0x11 /* 10v4a, lvc+sc+hv */
#define SCP_ADP_B_TYPE1_QTR_A_22P5W 0x12 /* 10v2.25a, lvc+sc+hv */
#define SCP_ADP_B_TYPE1_66W_BANK 0x13 /* 11v6a */
/* Huangpu River 2.0 three port adapter typeC1+typeA1+typeA2 */
#define SCP_ADP_B_TYPE1_HPR_C_66W 0x14 /* 10v6.6a */
#define SCP_ADP_B_TYPE1_HPR_C_40W 0x15 /* 10v4a 20v2a */
#define SCP_ADP_B_TYPE1_HPR_A_66W 0x16 /* 10v6.6A */
#define SCP_ADP_B_TYPE1_HPR_A_40W 0x17 /* 10v4a 20v2a */
#define SCP_ADP_B_TYPE1_HPR_A_22P5W 0x18 /* 10v2.25a */
#define SCP_ADP_B_TYPE1_NR_40W 0x19 /* 10v4a */
#define SCP_ADP_B_TYPE1_NR_40W_1 0x1a /* 10v4a */
#define SCP_ADP_B_TYPE1_NR_40W_2 0x1b /* 10v4a */
#define SCP_ADP_B_TYPE1_HHR_90W 0x1c /* 20v4.5a */
#define SCP_ADP_B_TYPE1_MJR_66W 0x1d /* 11v6a */
#define SCP_ADP_B_TYPE1_66W_CAR_1 0x1e /* 11v6a */
#define SCP_ADP_B_TYPE1_HPR_C_66W_1 0x1f /* 20v3.2a */
#define SCP_ADP_B_TYPE1_HPR_C_40W_1 0x20 /* 20v2a */
#define SCP_ADP_B_TYPE1_HPR_A_66W_1 0x21 /* 20v3.2a */
#define SCP_ADP_B_TYPE1_HPR_A_40W_1 0x22 /* 20v2a */
#define SCP_ADP_B_TYPE1_HPR_A_22P5W_1 0x23 /* 10v2.25a */
#define SCP_ADP_B_TYPE1_65W_2 0x24 /* 20v3.25a */
#define SCP_ADP_B_TYPE1_NR_40W_3 0x25 /* 10v4a */
#define SCP_ADP_B_TYPE1_JLR_135W 0x26
#define SCP_ADP_B_TYPE1_22P5W_CAR_1 0x27 /* 10v2.25a */
#define SCP_ADP_B_TYPE1_40W_2 0x28 /* 10v4a */
#define SCP_ADP_B_TYPE1_MJR_66W_1 0x29 /* 11v6a */
#define SCP_ADP_B_TYPE1_YLR_100W_CAR 0x2a /* 20v5a */
#define SCP_ADP_B_TYPE1_22P5W_BANK_1 0x2b /* 10v2.25a */
#define SCP_ADP_B_TYPE1_XR_65W_PC 0x2c /* 20v3.25a */
#define SCP_ADP_B_TYPE1_FCR_66W 0x2d /* 20v2a 11V6A */
#define SCP_ADP_B_TYPE1_HHR_90W_1 0x2e /* 20v4.5a */
/* Power Strip three port adapter typeC1+typeC2+typeA */
#define SCP_ADP_B_TYPE1_PS_C_65W 0x2f /* 20v3.25a */
#define SCP_ADP_B_TYPE1_PS_C_40W 0x30 /* 10v4a */
#define SCP_ADP_B_TYPE1_PS_C_40W_1 0x31 /* 10v4a */
#define SCP_ADP_B_TYPE1_PS_C_22P5W 0x32 /* 10v2.25a */
#define SCP_ADP_B_TYPE1_PS_A_40W 0x33 /* 10v4a */
#define SCP_ADP_B_TYPE1_PS_A_22P5W 0x34 /* 10v2.25a */
#define SCP_ADP_B_TYPE1_YLR_100W 0x3a /* 20v5a version2.0 */
#define SCP_FACTORY_ID 0x8e
#define SCP_MAX_PWR 0x90 /* in units of 100mW */
#define SCP_MAX_PWR_A_SHIFT 7
#define SCP_MAX_PWR_VAL(a, b) ((b) | ((a) << SCP_MAX_PWR_A_SHIFT))
#define SCP_CNT_PWR 0x91
#define SCP_MIN_VOUT 0x92 /* in unit of mV */
#define SCP_MAX_VOUT 0x93 /* in unit of mV */
#define SCP_MIN_IOUT 0x94 /* in unit of mA */
#define SCP_MAX_IOUT 0x95 /* in unit of mA */
#define SCP_VI_RANGE_VAL(a, b) ((b) | ((a) << 6))
#define SCP_VSTEP 0x96
#define SCP_VSTEP_A_SHIFT 6
#define SCP_ISTEP 0x97
#define SCP_ISTEP_A_SHIFT 6
#define SCP_MAX_VERR 0x98
#define SCP_MAX_IERR 0x99
#define SCP_MAX_ERR_VAL(a, b) ((b) | ((a) << 7))
#define SCP_MAX_STTIME 0x9A
#define SCP_MAX_RSPTIME 0x9B
#define SCP_MAX_IOUT_EXTEND 0x9c
#define SCP_MAX_POWER_EXTEND 0x9d
#define SCP_CTRL_BYTE0 0xa0
#define SCP_CTRL_BYTE0_OUTPUT_EN_MASK BIT_SET(7)
#define SCP_CTRL_BYTE0_OUTPUT_MODE_MASK BIT_SET(6) /* OUTPUT_MODE has higher priority over RESET */
#define SCP_CTRL_BYTE0_RESET_MASK BIT_SET(5)
#define SCP_CTRL_BYTE0_HWP_MASK BIT_SET(4)
#define SCP_CTRL_BYTE0_ACK_MSG_MASK BIT_SET(3)
#define SCP_CTRL_BYTE0_COT_EN BIT_SET(0)
#define SCP_CTRL_BYTE1 0xa1
#define SCP_CTRL_BYTE1_DP_DEGLITCH_MASK (BIT_SET(4) | BIT_SET(3)) /* in unit of ms */
#define SCP_CTRL_BYTE1_DP_DEGLITCH_SHIFT 3
#define SCP_CTRL_BYTE1_CTIMER_MASK (BIT_SET(2) | BIT_SET(1) | BIT_SET(0)) /* in units of 500ms */
#define SCP_CTIMER_TIMEOUT(s) (s * 2)
#define SCP_STATUS_BYTE0 0xa2
#define SCP_STATUS_BYTE0_OUTPUT_STS_MASK BIT_SET(7)
#define SCP_STATUS_BYTE0_READY_STS_MASK BIT_SET(6)
#define SCP_STATUS_BYTE0_MSG_STS_MASK BIT_SET(5)
#define SCP_STATUS_BYTE0_CC_CV_STS_MASK BIT_SET(4) /* 0: CV, 1: CC */
#define SCP_STATUS_BYTE0_CABLE_STS_MASK BIT_SET(3) /* 1: standard cable */
#define SCP_STATUS_BYTE0_COM_STS_MASK BIT_SET(0) /* 1: CTIMER timeout */
#define SCP_STATUS_BYTE1 0xa3
#define SCP_STATUS_BYTE1_CRCRX_MASK BIT_SET(7)
#define SCP_STATUS_BYTE1_PARRX_MASK BIT_SET(6)
#define SCP_STATUS_BYTE1_VIN_DUMP_MASK BIT_SET(5)
#define SCP_STATUS_BYTE1_OT_MASK BIT_SET(4)
#define SCP_STATUS_BYTE1_COT_MASK BIT_SET(3)
#define SCP_STATUS_BYTE1_OC_MASK BIT_SET(2)
#define SCP_STATUS_BYTE1_OV_MASK BIT_SET(1)
#define SCP_STATUS_BYTE1_UV_MASK BIT_SET(0)
#define SCP_STATUS_BYTE2 0xa4
#define SCP_STATUS_BYTE2_RLAD_OK BIT_SET(7)
#define SCP_SSTS 0xa5
#define SCP_SSTS_DPA_RTO_MASK (BIT_SET(3) | BIT_SET(2) | BIT_SET(1)) /* step: 1/8 */
#define SCP_SSTS_DPA_RTO_MASK_SHIFT 1
#define SCP_SSTS_DERATE_MASK BIT_SET(0)
#define SCP_INSIDE_TMP 0xa6
#define SCP_PORT_TMP 0xa7
#define SCP_READ_VOUT_H 0xa8
#define SCP_READ_VOUT_L 0xa9
#define SCP_READ_IOUT_H 0xaa
#define SCP_READ_IOUT_L 0xab
#define SCP_SREAD_VOUT 0xc8 /* in units of 10mV */
#define SCP_SREAD_VOUT_STEP 10
#define SCP_SREAD_IOUT 0xc9 /* in units of 50mA */
#define SCP_SREAD_IOUT_STEP 50
#define SCP_DAC_VSET_H 0xac
#define SCP_DAC_VSET_L 0xad
#define SCP_DAC_ISET_H 0xae
#define SCP_DAC_ISET_L 0xaf
#define SCP_VSET_BOUNDARY_H 0xb0
#define SCP_VSET_BOUNDARY_L 0xb1
#define SCP_ISET_BOUNDARY_H 0xb2
#define SCP_ISET_BOUNDARY_L 0xb3
#define SCP_MAX_VSET_OFFSET 0xb4
#define SCP_MAX_VSET_OFFSET_A_SHIFT 6
#define SCP_MAX_ISET_OFFSET 0xb5
#define SCP_MAX_ISET_OFFSET_A_SHIFT 6
#define SCP_VSET_H 0xb8
#define SCP_VSET_L 0xb9
#define SCP_ISET_H 0xba
#define SCP_ISET_L 0xbb
#define SCP_VSSET 0xca
#define SCP_VSSET_OFFSET 3000 /* in unit of mV */
#define SCP_VSSET_STEP 10 /* in unit of mV */
#define SCP_VSSET_VAL(reg) (SCP_VSSET_OFFSET + (reg) * (uint16_t)SCP_VSSET_STEP)
#define SCP_ISSET 0xcb
#define SCP_ISSET_STEP 50 /* in unit of mA */
#define SCP_ISSET_VAL(reg) ((uint16_t)(reg) * SCP_ISSET_STEP)
#define SCP_VSET_OFFSET_H 0xbc
#define SCP_VSET_OFFSET_L 0xbd
#define SCP_VSET_OFFSET(h, l) ((((uint16_t)((h) & 0x7f)) << 8) | l)
#define SCP_VSET_OFFSET_NEGATIVE(h) (((h) & 0x80) != 0)
#define SCP_ISET_OFFSET_H 0xbe
#define SCP_ISET_OFFSET_L 0xbf
#define SCP_ISET_OFFSET(h, l) ((((uint16_t)((h) & 0x7f)) << 8) | l)
#define SCP_ISET_OFFSET_NEGATIVE(h) (((h) & 0x80) != 0)
#define SCP_STEP_VSET_OFFSET 0xcc
#define SCP_STEP_VSET_OFFSET_MASK 0x7f
#define SCP_STEP_VSET_OFFSET_NEG_MASK 0x80
#define SCP_STEP_ISET_OFFSET 0xcd
#define SCP_STEP_ISET_OFFSET_MASK 0x7f
#define SCP_STEP_ISET_OFFSET_NEG_MASK 0x80
#define SCP_S_FUN_1 0xce
#define SCP_KEY_IDX_PUBLIC 0x01
#define SCP_KEY_IDX_RELEASE 0xff
#define SCP_S_FUN_2 0xcf
#define SCP_ENCRYPT_ENABLE_MASK BIT_SET(7)
#define SCP_ENCRYPT_COMPLETED_MASK BIT_SET(6)
#define SCP_USBPD_DISABLE_MASK BIT_SET(0)
#define SCP_ENCRYPT_RANDOM_WR_BASE 0xa0
#define SCP_ENCRYPT_RANDOM_WR_SIZE 8
#define SCP_ENCRYPT_RANDOM_RD_BASE 0xa8
#define SCP_ENCRYPT_RANDOM_RD_SIZE 8
#define SCP_ENCRYPT_HASH_RD_BASE 0xb0
#define SCP_ENCRYPT_HASH_RD_SIZE 16
#define SCP_PWR_SEG_NUM 0x8f
#define SCP_PWR_SEG_NUM_MAX 15
#define SCP_PWR_SEG_BASE 0xd0 /* through 0xed */
#define SCP_PWR_VOUT_SEG(n) (SCP_PWR_SEG_BASE + (n - 1) * 2)
#define SCP_PWR_VOUT_SEG_STEP 500 /* in unit of mV */
#define SCP_PWR_IOUT_SEG(n) (SCP_PWR_SEG_BASE + (n - 1) * 2 + 1)
#define SCP_PWR_IOUT_SEG_STEP 100 /* in unit of mA */
struct scp_prl_s;
typedef struct scp_prl_s scp_prl_s;
typedef enum SCP_PROCESS_e
{
SCP_ENTRY_STATUS = 0,
SCP_EXIT_STATUS
} SCP_PROCESS_e;
typedef enum SCP_TX_STATES_e
{
SCP_TX_WAIT_REQUEST = 0,
SCP_TX_WAIT_PING_COMPLETE,
SCP_TX_WAIT_DATA_COMPLETE
} SCP_TX_STATES_e;
typedef enum SCP_RX_STATES_e
{
SCP_RX_WAIT_RECV_COMPLETE = 0,
SCP_RX_DATA_DISPOSE
} SCP_RX_STATES_e;
typedef struct
{
SCP_TX_STATES_e tx_state;
SCP_PROCESS_e tx_process;
} scp_tx_states_s;
typedef struct
{
SCP_RX_STATES_e rx_state;
SCP_PROCESS_e rx_process;
} scp_rx_states_s;
typedef enum SCP_COMM_DISPOSE_STATES_e
{
SCP_COMM_UNKNOWN = 0,
SCP_COMM_NCK,
SCP_COMM_MBRWR,
SCP_COMM_MBRRD,
SCP_COMM_SBRRD,
SCP_COMM_SBRWR
} SCP_COMM_DISPOSE_STATES_e;
typedef union
{
uint8_t byte[2];
struct
{
//byte0
uint8_t scp_int_flag_pkt_get : 1;
uint8_t scp_int_flag_reset_get: 1;
uint8_t scp_int_flag_rx_error: 1;
uint8_t scp_int_flag_crc_eeror: 1;
uint8_t scp_one_pkt_finish : 1;
uint8_t scp_commcationing: 1;
uint8_t scp_parity_error_flag: 1;
uint8_t scp_check_timeout_flag : 1;
//byte1
uint8_t scp_request_ping_sent: 1;
uint8_t scp_send_data_start: 1;
uint8_t scp_int_flag_tx_flag: 1;
uint8_t reserved0: 5;
} bf;
} u_scp_int_flags;
typedef union
{
uint16_t data16;
struct
{
//byte0
uint8_t scp_flag_parity_error: 4;
uint8_t scp_flag_crc_error : 4;
//byte1
uint8_t scp_request_data_sent : 1;/*NOT USED*/
uint8_t scp_afc_identify : 2;
uint8_t scp_encying_flag : 1;/*fix ot process flag*/
uint8_t scp_rcv_cmd_flag: 1;/*1:rcv scp mcn*/
uint8_t scp_rcv_cmd_rw_flag: 1;/*1:rd cmd;0:wr_cmd*/
uint8_t reserved : 2;
} bf;
} u_scp_process_flags;
typedef struct scp_prl_s_flags_s
{
volatile u_scp_int_flags scp_int_flags;
volatile u_scp_process_flags scp_process_flags;
} scp_prl_s_flags_s;
typedef struct scp_prl_callback_s
{
void (*scp_comm_dispose)(uint8_t port, scp_prl_s *scp_prl_passist);
uint8_t (*scp_comm_mbrwr)(uint8_t port, scp_prl_s *scp_prl_passist);
uint8_t (*scp_comm_mbrrd)(uint8_t port, scp_prl_s *scp_prl_passist);
uint8_t (*scp_comm_sbrrd)(uint8_t port, scp_prl_s *scp_prl_passist);
uint8_t (*scp_comm_sbrwr)(uint8_t port, scp_prl_s *scp_prl_passist);
} scp_prl_callback_s;
typedef struct scp_phy_callback_s
{
void (*scp_phy_logic_reset)(uint8_t port, bool enable);
void (*scp_send_pkt)(uint8_t port, uint8_t *buffer, uint8_t len);
void (*scp_phy_disable)(uint8_t port);
void (*scp_phy_reg_init)(uint8_t port);
void (*dpdn_dp_pull_down_resistor_set)(uint8_t port, uint8_t en);
uint8_t (*get_scp_rx_size)(uint8_t port);
uint8_t (*get_scp_phy_is_crc_ok)(uint8_t port);
bool (*scp_phy_afc_mode_check)(uint8_t port);
} scp_phy_callback_s;
struct scp_prl_s
{
scp_prl_s_flags_s scp_prl_flags;
/*add*/
uint8_t scp_rcv_addr;
uint8_t scp_rcv_len;
uint8_t scp_ping_get_cnt;
uint8_t tx_size;
uint8_t rx_size;
volatile uint8_t tx_sent_timeout;
volatile uint8_t tx_ping_sent_time_value;
volatile uint8_t tx_data_sent_time_value;
uint8_t afc_request_index;
uint8_t register_value[256];
uint8_t register_attribute[128];
uint8_t *tx_buffer;
uint8_t *rx_buffer;
const scp_prl_callback_s *scp_prl_callback;
const scp_phy_callback_s *scp_phy_callback;
};
/*
* @brief scp_phy_hook_init
* @param port
* @param scp_prl_passist
* @note
* @retval NULL
*/
void scp_phy_hook_init(uint8_t port, scp_prl_s *scp_prl_passist);
/*
* @brief scp_prl_hook_init
* @param port
* @param scp_prl_passist
* @note null
* @retval null
*/
void scp_prl_hook_init(uint8_t port, scp_prl_s *scp_prl_passist);
/*
* @brief scp_tx_wait_requst
* @param port
* @param scp_prl_passist
* @note null
* @retval null
*/
void scp_tx_wait_requst(uint8_t port, scp_prl_s *scp_prl_passist);
/*
* @brief scp_tx_wait_ping_complete
* @param port
* @param scp_prl_passist
* @note
* @retval NULL
*/
void scp_tx_wait_ping_complete(uint8_t port, scp_prl_s *scp_prl_passist);
/*
* @brief scp_tx_wait_data_complete
* @param port
* @param scp_prl_passist
* @note
* @retval NULL
*/
void scp_tx_wait_data_complete(uint8_t port, scp_prl_s *scp_prl_passist);
/*
* @brief scp_tx_run
* @param port
* @param scp_prl_passist
* @note
* @retval NULL
*/
void scp_tx_run(uint8_t port, scp_prl_s *scp_prl_passist);
/*
* @brief scp_rx_wait_recv_compelte
* @param port
* @param scp_prl_passist
* @note
* @retval NULL
*/
void scp_rx_wait_recv_compelte(uint8_t port, scp_prl_s *scp_prl_passist);
/*
* @brief scp_comm_dispose
* @param port
* @param scp_prl_passist
* @note
* @retval NULL
* *for correct command as follows
*1. command of length is eeror ,just need to response ping
*2. when command of many byte , address len must even number. or else response nck
*3. wrong command ,just need to response ping
*/
void scp_comm_dispose(uint8_t port, scp_prl_s *scp_prl_passist);
/*
* @brief scp_rx_data_dispose
* @param port
* @param scp_prl_passist
* @note
* @retval NULL
*/
void scp_rx_data_dispose(uint8_t port, scp_prl_s *scp_prl_passist);
/*
* @brief scp_rx_run
* @param port
* @param scp_prl_passist
* @note
* @retval NULL
*/
void scp_rx_run(uint8_t port, scp_prl_s *scp_prl_passist);
/*
* @brief scp_comm_mbrwr
* @param port
* @param *scp_prl_passist
* @note //0x1b many_byte write
* @retval NULL
*/
uint8_t scp_comm_mbrwr(uint8_t port, scp_prl_s *scp_prl_passist);
/*
* @brief scp_comm_mbrrd
* @param port
* @param *scp_prl_passist
* @note //0x1c many_byte read
* @retval NULL
*/
uint8_t scp_comm_mbrrd(uint8_t port, scp_prl_s *scp_prl_passist);
/*
* @brief scp_comm_sbrrd
* @param port
* @param *scp_prl_passist
* @note //0x0c byte read
* @retval NULL
*/
uint8_t scp_comm_sbrrd(uint8_t port, scp_prl_s *scp_prl_passist);
/*
* @brief scp_comm_sbrwr
* @param port
* @param *scp_prl_passist
* @note //0x0b byte write
* @retval NULL
*/
uint8_t scp_comm_sbrwr(uint8_t port, scp_prl_s *scp_prl_passist);
/*
* @brief scp_prl_run scp_tx_rx
* @param port
* @param *scp_prl_passist
* @note
* @retval NULL
*/
void scp_prl_run(uint8_t port, scp_prl_s *scp_prl_passist);
/*
* @brief scp_prl_rx_handler
* @param port
* @param *scp_prl_passist
* @note
* @retval NULL
*/
void scp_prl_rx_handler(uint8_t port, scp_prl_s *scp_prl_passist);
#endif