/**
 ******************************************************************************
 * @copyright Copyright (C), 2016-2022, ConvenientPower. Co., Ltd.
 * @file    comp_primary_side.h
 * @version 1.0
 * @author  qing.cheng
 * @date    2023-10-07
 * @brief   Header file of COMP_PRIMARY_SIDE_H module.
 ******************************************************************************
 */
#ifndef _COMP_PRIMARY_SIDE_H_
#define _COMP_PRIMARY_SIDE_H_

#include "core_comm.h"
#include "drv_comm.h"


#include "rom_inc.h"
#include "config.h"

#if ADC_TRIM_ENABLE
#define VD_RD_2P4K      VD_RVDS_TRIM_VALUE
#else
#define VD_RD_2P4K      2400
#endif
#define VD_RP_VALUE     46400

//N * 128
#define N_RATIO         800


#define VD_PEAK_LIMIT   400


typedef struct
{
    uint32_t ac_freq;   //hz
    uint32_t ac_vol;
    uint8_t  vd_peak_cnt;
    uint8_t  ac_high;
    uint8_t ac_cnt;
    uint8_t ac_sample_flag;
    uint16_t high_width;
    uint16_t low_width;

} edge_info_s;

extern edge_info_s g_edge_param;


#define  AC_H_VOL_VPP    254
#define  AC_L_VOL_VPP    150//226000



#if VD_PEAK_DETECT
#define VD_PEAK_TIMEOUT     5
#endif

#if VD_FREQ_DETECT
#define FREQ_CALC_TIME      (0x64)
#define FREQ_CALC_START     (1 << 9)
#endif


#define VD_SCALE_EN         (0 << 5)

#define VD_ANALOG_CONFIG    (0x01 | VD_SCALE_EN)

#define SAMPLE_ON_EN     1
#define BLANK_TIME      (0x04) //83.3/lsb     
#define SAMPLE_TIME     (0x01 << 16)

#define VD_FILTER_0NS       0
#define VD_FILTER_666NS     1
#define VD_FILTER_249NS     2
#define VD_FILTER_498NS     3


#define REG_EXTINT_VD_FREQ_CALC_INT_BASE\
        (0x40013018)


#define REG_FILTER_VD_100MV_COMP_BASE\
        (0x40014020)

#define REG_MSIC_VD_FREQ_CALC_BASE\
        (0x4000f820)

#define REG_MISC_VD_LS_COMP_BASE\
        (0x4000F824)



#define DRV_FILTER_VD_100MV_COMP_MASK_SET(x)\
        do{\
            *((uint32_t *)(REG_FILTER_VD_100MV_COMP_BASE)) |= ((x & 0x03) << 20);\
        }while(0)


#define DRV_EXTINT_VD_LS_CHG_MASK_SET(x)\
        do{\
            *((uint32_t *)(REG_EXTINT_VD_LS_COMP_CHG_INT_BASE)) |= x;\
        }while(0)


#define DRV_EXTINT_VD_LS_CHG_GET_READ()\
        (*((uint32_t *)(REG_EXTINT_VD_LS_COMP_CHG_INT_BASE)))


#define DRV_EXTINT_VD_FREQ_CALC_MASK_SET(x)\
        do{\
            *((uint32_t *)(REG_EXTINT_VD_FREQ_CALC_INT_BASE)) |= x;\
        }while(0)


#define DRV_MISC_VD_LS_COMP_MASK_SET(x)\
        do{\
            *((uint32_t *)(REG_MISC_VD_LS_COMP_BASE)) |= x;\
        }while(0)



#define COMP_VD_RD_2P4K_SET()\
        do{\
            REG_ANALOG_ANA_CTRL->word |= 0x01;\
        }while(0)

#define COMP_VD_RD_2P4K_RESET()\
        do{\
            REG_ANALOG_ANA_CTRL->word &= ~(0x01);\
        }while(0)

#define HAL_GET_VD_FREQ()\
        ((((*((uint32_t *)REG_MSIC_VD_FREQ_CALC_BASE) >> 16) & 0xffff) * 1000) / FREQ_CALC_TIME)


#define HAL_VD_AC_SAMPLE_DISABLE()\
        do{\
            g_edge_param.ac_sample_flag = false;\
        }while(0)



/*
  * @brief  comp_primary_side_init
  * @param  NULL
  * @note
  * @retval NULL
*/
void comp_primary_side_init(void);

/*
  * @brief  comp_vd_peak_timer_config
  * @param  edge_param
  * @note  add timeout, when adc detect vd signal of not rising
  *         that adc interrupt not trigger.
  * @retval NULL
*/
void comp_vd_peak_timer_config(edge_info_s *edge_param);

/*
  * @brief  comp_vd_peak_detect_timeout
  * @param  edge_param
  * @note  vd adc channel timeout check.
  * @retval NULL
*/
void comp_vd_peak_detect_timeout(edge_info_s *edge_param);

/*
  * @brief  comp_vd_detect_ac_vol
  * @param  edge_param
     * Vac = (V_vd / R_vds * (R_vd + R_vds) - Vo) * n / 1.414213
    * Vo:output vol.
    * n:ratio.
    * R_vds:2.4k.
    * R_vd:pull-up resistor.
  * @note  get ac_input vol
  * @retval NULL
*/
void comp_vd_detect_ac_vol(edge_info_s *edge_param);

/*
  * @brief  comp_primary_freq_get
  * @param  NULL
  * @note  NULL
  * @retval NULL
*/
void comp_primary_freq_get(void);

#endif /*HAL_PRIMARY_SIDE_H*/