#ifndef __ADC_DEFINE_H__ #define __ADC_DEFINE_H__ //----------------------------------------------------------------------------- // adc registers definition //----------------------------------------------------------------------------- #pragma anon_unions //----------------------------------------------------------------------------- // registers structures typedef struct { //adc channel enable, decoder is in analog. //0x0 = ch0, 0x1 = ch1, … 0xf = ch15,… 0x14 = ch20 , 0x15 is test channel, 0x16 & 0x17 reserved uint32_t ch_en:5; uint32_t reserved_7_5:3; //adc sampling hold time selection //000:4 adc_clk 001:8 adc_clk 010:12 adc_clk 011:16 adc_clk //100:32 adc_clk 101:64 adc_clk 110:128 adc_clk 111:256 adc_clk uint32_t sh_sel:3; //adc clock divider radio //00:1mhz; 01:500khz; 10:250khz; 11:125khz; uint32_t clk_div:2; //sample total times for average cal: //00:1, totally sample one time then gen interrupt; //01:2, totally sample two times then gen interrupt; //10:4 times; 11:8 times; uint32_t average:2; //if average=00, interface da_adc_chop_sel is controlled by this bit; //if average!=00, interface da_adc_chop_sel is controlled by hw automatically. uint32_t chop_sel:1; //adc block enable. uint32_t en:1; //adc convert start. uint32_t start:1; uint32_t reserved_31_18:14; } REG_adc_cfg_bitfiled_TypeDef; typedef struct { union { __IO REG_adc_cfg_bitfiled_TypeDef bf;//bitfiled __IO uint32_t word; }; } REG_adc_cfg_TypeDef; typedef struct { //adc converted data, available when adc_average_done goes high uint32_t value:12; uint32_t reserved_31_12:20; } REG_adc_data_bitfiled_TypeDef; typedef struct { union { __IO REG_adc_data_bitfiled_TypeDef bf;//bitfiled __IO uint32_t word; }; } REG_adc_data_TypeDef; typedef struct { //adc average times done. write 1 to clear this interrupt. uint32_t avg_done:1; uint32_t reserved_31_1:31; } REG_adc_int_bitfiled_TypeDef; typedef struct { union { __IO REG_adc_int_bitfiled_TypeDef bf;//bitfiled __IO uint32_t word; }; } REG_adc_int_TypeDef; typedef struct { //1: mask this interrupt source; //0: unmask this intterupt source uint32_t avg_done:1; uint32_t reserved_31_1:31; } REG_adc_int_mask_bitfiled_TypeDef; typedef struct { union { __IO REG_adc_int_mask_bitfiled_TypeDef bf;//bitfiled __IO uint32_t word; }; } REG_adc_int_mask_TypeDef; typedef struct { //00 : enable dtb output of adc data; 01: dtb output of adc test;10 or 11:disable dtb output uint32_t en:2; uint32_t reserved_7_2:6; //adc ctrl state machine uint32_t fsm:4; uint32_t reserved_31_12:20; } REG_adc_dbg_bitfiled_TypeDef; typedef struct { union { __IO REG_adc_dbg_bitfiled_TypeDef bf;//bitfiled __IO uint32_t word; }; } REG_adc_dbg_TypeDef; typedef struct { //adc data splicing:{data3,data2,data1,data0} uint32_t value:32; } REG_adc_test_spl_data_bitfiled_TypeDef; typedef struct { union { __IO REG_adc_test_spl_data_bitfiled_TypeDef bf;//bitfiled __IO uint32_t word; }; } REG_adc_test_spl_data_TypeDef; typedef struct { //adc test error cnt max uint32_t error_cnt_max:11; uint32_t reserved_15_11:5; //error max limit uint32_t error_range:7; uint32_t reserved_31_23:9; } REG_adc_adc_test0_bitfiled_TypeDef; typedef struct { union { __IO REG_adc_adc_test0_bitfiled_TypeDef bf;//bitfiled __IO uint32_t word; }; } REG_adc_adc_test0_TypeDef; typedef struct { //adc test pass；0：test fail，1：test pass uint32_t pass:1; //adc test done；1:test done uint32_t done:1; uint32_t reserved_31_2:30; } REG_adc_adc_test1_bitfiled_TypeDef; typedef struct { union { __IO REG_adc_adc_test1_bitfiled_TypeDef bf;//bitfiled __IO uint32_t word; }; } REG_adc_adc_test1_TypeDef; typedef struct { //adc and dac test enable uint32_t en:1; //dac test model initial value uint32_t ini_value:12; //step of dac increase：4’d0-4'd15 limit:(target-ini_value)/inc=integer； uint32_t inc:4; //adc test fail end test en:1 fail and done,0:fail go on uint32_t fail_en:1; //adc test mode for dac output target vaule //2.2v/2048=1lsb uint32_t target:12; uint32_t reserved_31_30:2; } REG_adc_adc_test2_bitfiled_TypeDef; typedef struct { union { __IO REG_adc_adc_test2_bitfiled_TypeDef bf;//bitfiled __IO uint32_t word; }; } REG_adc_adc_test2_TypeDef; typedef struct { //adc test done. write 1 to clear this interrupt. uint32_t done:1; uint32_t reserved_31_1:31; } REG_adc_int_test_bitfiled_TypeDef; typedef struct { union { __IO REG_adc_int_test_bitfiled_TypeDef bf;//bitfiled __IO uint32_t word; }; } REG_adc_int_test_TypeDef; typedef struct { //adc test done mask ;1: mask this interrupt source; uint32_t done:1; uint32_t reserved_31_1:31; } REG_adc_int_mask_test_bitfiled_TypeDef; typedef struct { union { __IO REG_adc_int_mask_test_bitfiled_TypeDef bf;//bitfiled __IO uint32_t word; }; } REG_adc_int_mask_test_TypeDef; //----------------------------------------------------------------------------- // memory map #define REG_ADC_CFG_BASE 0x40008800 #define REG_ADC_DATA_BASE 0x40008804 #define REG_ADC_INT_BASE 0x40008808 #define REG_ADC_INT_MASK_BASE 0x4000880C #define REG_ADC_DBG_BASE 0x40008810 #define REG_ADC_TEST_SPL_DATA_BASE 0x40008814 #define REG_ADC_ADC_TEST0_BASE 0x40008818 #define REG_ADC_ADC_TEST1_BASE 0x4000881C #define REG_ADC_ADC_TEST2_BASE 0x40008820 #define REG_ADC_INT_TEST_BASE 0x40008824 #define REG_ADC_INT_MASK_TEST_BASE 0x40008828 //----------------------------------------------------------------------------- // declaration #define REG_ADC_CFG ((REG_adc_cfg_TypeDef *) REG_ADC_CFG_BASE ) #define REG_ADC_DATA ((REG_adc_data_TypeDef *) REG_ADC_DATA_BASE ) #define REG_ADC_INT ((REG_adc_int_TypeDef *) REG_ADC_INT_BASE ) #define REG_ADC_INT_MASK ((REG_adc_int_mask_TypeDef *) REG_ADC_INT_MASK_BASE ) #define REG_ADC_DBG ((REG_adc_dbg_TypeDef *) REG_ADC_DBG_BASE ) #define REG_ADC_TEST_SPL_DATA ((REG_adc_test_spl_data_TypeDef *) REG_ADC_TEST_SPL_DATA_BASE ) #define REG_ADC_ADC_TEST0 ((REG_adc_adc_test0_TypeDef *) REG_ADC_ADC_TEST0_BASE ) #define REG_ADC_ADC_TEST1 ((REG_adc_adc_test1_TypeDef *) REG_ADC_ADC_TEST1_BASE ) #define REG_ADC_ADC_TEST2 ((REG_adc_adc_test2_TypeDef *) REG_ADC_ADC_TEST2_BASE ) #define REG_ADC_INT_TEST ((REG_adc_int_test_TypeDef *) REG_ADC_INT_TEST_BASE ) #define REG_ADC_INT_MASK_TEST ((REG_adc_int_mask_test_TypeDef *) REG_ADC_INT_MASK_TEST_BASE ) //----------------------------------------------------------------------------- // set #define REG_ADC_CFG_CH_EN_POS 0 #define REG_ADC_CFG_CH_EN_MSK (0x1Ful << REG_ADC_CFG_CH_EN_POS) #define REG_ADC_CFG_CH_EN_SET(num) (((num) << REG_ADC_CFG_CH_EN_POS ) & REG_ADC_CFG_CH_EN_MSK) #define REG_ADC_CFG_SH_SEL_POS 8 #define REG_ADC_CFG_SH_SEL_MSK (0x7ul << REG_ADC_CFG_SH_SEL_POS) #define REG_ADC_CFG_SH_SEL_SET(num) (((num) << REG_ADC_CFG_SH_SEL_POS ) & REG_ADC_CFG_SH_SEL_MSK) #define REG_ADC_CFG_CLK_DIV_POS 11 #define REG_ADC_CFG_CLK_DIV_MSK (0x3ul << REG_ADC_CFG_CLK_DIV_POS) #define REG_ADC_CFG_CLK_DIV_SET(num) (((num) << REG_ADC_CFG_CLK_DIV_POS ) & REG_ADC_CFG_CLK_DIV_MSK) #define REG_ADC_CFG_AVERAGE_POS 13 #define REG_ADC_CFG_AVERAGE_MSK (0x3ul << REG_ADC_CFG_AVERAGE_POS) #define REG_ADC_CFG_AVERAGE_SET(num) (((num) << REG_ADC_CFG_AVERAGE_POS ) & REG_ADC_CFG_AVERAGE_MSK) #define REG_ADC_CFG_CHOP_SEL_POS 15 #define REG_ADC_CFG_CHOP_SEL_MSK (0x1ul << REG_ADC_CFG_CHOP_SEL_POS) #define REG_ADC_CFG_CHOP_SEL_SET(num) (((num) << REG_ADC_CFG_CHOP_SEL_POS ) & REG_ADC_CFG_CHOP_SEL_MSK) #define REG_ADC_CFG_EN_POS 16 #define REG_ADC_CFG_EN_MSK (0x1ul << REG_ADC_CFG_EN_POS) #define REG_ADC_CFG_EN_SET(num) (((num) << REG_ADC_CFG_EN_POS ) & REG_ADC_CFG_EN_MSK) #define REG_ADC_CFG_START_POS 17 #define REG_ADC_CFG_START_MSK (0x1ul << REG_ADC_CFG_START_POS) #define REG_ADC_CFG_START_SET(num) (((num) << REG_ADC_CFG_START_POS ) & REG_ADC_CFG_START_MSK) #define REG_ADC_INT_MASK_AVG_DONE_POS 0 #define REG_ADC_INT_MASK_AVG_DONE_MSK (0x1ul << REG_ADC_INT_MASK_AVG_DONE_POS) #define REG_ADC_INT_MASK_AVG_DONE_SET(num) (((num) << REG_ADC_INT_MASK_AVG_DONE_POS ) & REG_ADC_INT_MASK_AVG_DONE_MSK) #define REG_ADC_DBG_EN_POS 0 #define REG_ADC_DBG_EN_MSK (0x3ul << REG_ADC_DBG_EN_POS) #define REG_ADC_DBG_EN_SET(num) (((num) << REG_ADC_DBG_EN_POS ) & REG_ADC_DBG_EN_MSK) #define REG_ADC_ADC_TEST0_ERROR_CNT_MAX_POS 0 #define REG_ADC_ADC_TEST0_ERROR_CNT_MAX_MSK (0x7FFul << REG_ADC_ADC_TEST0_ERROR_CNT_MAX_POS) #define REG_ADC_ADC_TEST0_ERROR_CNT_MAX_SET(num) (((num) << REG_ADC_ADC_TEST0_ERROR_CNT_MAX_POS ) & REG_ADC_ADC_TEST0_ERROR_CNT_MAX_MSK) #define REG_ADC_ADC_TEST0_ERROR_RANGE_POS 16 #define REG_ADC_ADC_TEST0_ERROR_RANGE_MSK (0x7Ful << REG_ADC_ADC_TEST0_ERROR_RANGE_POS) #define REG_ADC_ADC_TEST0_ERROR_RANGE_SET(num) (((num) << REG_ADC_ADC_TEST0_ERROR_RANGE_POS ) & REG_ADC_ADC_TEST0_ERROR_RANGE_MSK) #define REG_ADC_ADC_TEST2_EN_POS 0 #define REG_ADC_ADC_TEST2_EN_MSK (0x1ul << REG_ADC_ADC_TEST2_EN_POS) #define REG_ADC_ADC_TEST2_EN_SET(num) (((num) << REG_ADC_ADC_TEST2_EN_POS ) & REG_ADC_ADC_TEST2_EN_MSK) #define REG_ADC_ADC_TEST2_INI_VALUE_POS 1 #define REG_ADC_ADC_TEST2_INI_VALUE_MSK (0xFFFul << REG_ADC_ADC_TEST2_INI_VALUE_POS) #define REG_ADC_ADC_TEST2_INI_VALUE_SET(num) (((num) << REG_ADC_ADC_TEST2_INI_VALUE_POS ) & REG_ADC_ADC_TEST2_INI_VALUE_MSK) #define REG_ADC_ADC_TEST2_INC_POS 13 #define REG_ADC_ADC_TEST2_INC_MSK (0xFul << REG_ADC_ADC_TEST2_INC_POS) #define REG_ADC_ADC_TEST2_INC_SET(num) (((num) << REG_ADC_ADC_TEST2_INC_POS ) & REG_ADC_ADC_TEST2_INC_MSK) #define REG_ADC_ADC_TEST2_FAIL_EN_POS 17 #define REG_ADC_ADC_TEST2_FAIL_EN_MSK (0x1ul << REG_ADC_ADC_TEST2_FAIL_EN_POS) #define REG_ADC_ADC_TEST2_FAIL_EN_SET(num) (((num) << REG_ADC_ADC_TEST2_FAIL_EN_POS ) & REG_ADC_ADC_TEST2_FAIL_EN_MSK) #define REG_ADC_ADC_TEST2_TARGET_POS 18 #define REG_ADC_ADC_TEST2_TARGET_MSK (0xFFFul << REG_ADC_ADC_TEST2_TARGET_POS) #define REG_ADC_ADC_TEST2_TARGET_SET(num) (((num) << REG_ADC_ADC_TEST2_TARGET_POS ) & REG_ADC_ADC_TEST2_TARGET_MSK) #define REG_ADC_INT_MASK_TEST_DONE_POS 0 #define REG_ADC_INT_MASK_TEST_DONE_MSK (0x1ul << REG_ADC_INT_MASK_TEST_DONE_POS) #define REG_ADC_INT_MASK_TEST_DONE_SET(num) (((num) << REG_ADC_INT_MASK_TEST_DONE_POS ) & REG_ADC_INT_MASK_TEST_DONE_MSK) #endif /*__ADC_DEFINE_H__*/