#ifndef __ANALOG_DEFINE_H__ #define __ANALOG_DEFINE_H__ //----------------------------------------------------------------------------- // analog registers definition //----------------------------------------------------------------------------- #pragma anon_unions //----------------------------------------------------------------------------- // registers structures typedef struct { //over temperature protection test mode function,60° toggle. uint32_t ot_tm:1; //1:enable over temperature protection uint32_t en_ot:1; //1:enable vin ovuv testmode digital output, register uint32_t vin_ovuv_test_oe:1; //1:enable vinov function uint32_t en_vin_ov:1; //1:enable vin ovp block&output uint32_t vin_en_ovp:1; //enable vin ratio over-voltage protection uint32_t vin_en_rp_ovp:1; //enable vin ratio under-voltage protection uint32_t vin_en_rp_uvp:1; //register-optional vin ovp threshold ; 00: 115%; 01:120%; 10:1125%; 11:130% uint32_t vin_ov_vth:2; //register-optional vin uvp threshold ; 00: 80%; 01:75%; 10:70%; 11:65% uint32_t vin_uv_vth:2; //1:enable vin1 ovuv testmode digital output, register uint32_t vin1_ovuv_test_oe:1; //1:enable vin1ov function uint32_t en_vin1_ov:1; //1:enable vin1 ovp block&output uint32_t vin1_en_ovp:1; //enable vin1 ratio over-voltage protection uint32_t vin1_en_rp_ovp:1; //enable vin1 ratio under-voltage protection uint32_t vin1_en_rp_uvp:1; //register-optional vin1 ovp threshold ; 00: 115%; 01:120%; 10:1125%; 11:130% uint32_t vin1_ov_vth:2; //register-optional vin1 uvp threshold ; 00: 80%; 01:75%; 10:70%; 11:65% uint32_t vin1_uv_vth:2; //1:enable vin2 ovuv testmode digital output, register uint32_t vin2_ovuv_test_oe:1; //1:enable vin2ov function uint32_t en_vin2_ov:1; //1:enable vin2 ovp block&output uint32_t vin2_en_ovp:1; //enable vin2 ratio over-voltage protection uint32_t vin2_en_rp_ovp:1; //enable vin2 ratio under-voltage protection uint32_t vin2_en_rp_uvp:1; //register-optional vin2 ovp threshold ; 00: 115%; 01:120%; 10:1125%; 11:130% uint32_t vin2_ov_vth:2; //register-optional vin2 uvp threshold ; 00: 80%; 01:75%; 10:70%; 11:65% uint32_t vin2_uv_vth:2; uint32_t reserved_31_29:3; } REG_analog_prot_bitfiled_TypeDef; typedef struct { union { __IO REG_analog_prot_bitfiled_TypeDef bf;//bitfiled __IO uint32_t word; }; } REG_analog_prot_TypeDef; typedef struct { //1: short dn and dp with ??o res uint32_t en_dcp:1; //1: enable dn function uint32_t en_dn:1; //1: enable dp function uint32_t en_dp:1; //1: connect 20k res (rdm) on dn uint32_t en_rdn:1; //1: connect 20k res on dp uint32_t en_rdp:1; //1: measure voltage on dn 1st step uint32_t meas_dn:1; //1: measure voltage on dp 1st step uint32_t meas_dp:1; //1: enable qc comparator on dn 2nd step uint32_t qc_comp_dn_en:1; //1: enable qc comparator on dp 2nd step uint32_t qc_comp_dp_en:1; //1: dpdn divder 1/3 to adc; 0: dpdn divder no div, no res, register-optional dpdm scaling factor for adc uint32_t dn_scal_en:1; //1: dpdn divder 1/3 to adc; 0: dpdn divder no div, no res, register-optional dpdm scaling factor for adc uint32_t dp_scal_en:1; //register-optional output high voltage: //00=open; //01=3.3v; //10=1.8v; //11=2.7v uint32_t ref_dac:2; //dp dn pull-up sourcing current //0: open //1:2ua uint32_t cur_en:1; uint32_t reserved_14_14:1; //1: 1.6v/1.3v; 0: 1.2v/1.1v(default) uint32_t vth_sel:1; //register-optional dn pull-high resistance for apple mode //0：open //1：30k omh uint32_t dn_rh_en:1; //register-optional dp pull-high resistance for apple mode //0：open //1：30k omh uint32_t dp_rh_en:1; // uint32_t dn_hvswitch_on:1; // uint32_t dp_hvswitch_on:1; // uint32_t ibias_en:1; //dp1 sink current for cdp detection,enable/disable by register setting,0:disable,1:enalbe uint32_t dp1_sink:1; // uint32_t cdp_src:1; uint32_t reserved_31_23:9; } REG_analog_dpdn1_bitfiled_TypeDef; typedef struct { union { __IO REG_analog_dpdn1_bitfiled_TypeDef bf;//bitfiled __IO uint32_t word; }; } REG_analog_dpdn1_TypeDef; typedef struct { //1: short dn and dp with ??o res uint32_t en_dcp:1; //1: enable dn function uint32_t en_dn:1; //1: enable dp function uint32_t en_dp:1; //1: connect 20k res (rdm) on dn uint32_t en_rdn:1; //1: connect 20k res on dp uint32_t en_rdp:1; //1: measure voltage on dn 1st step uint32_t meas_dn:1; //1: measure voltage on dp 1st step uint32_t meas_dp:1; //1: enable qc comparator on dn 2nd step uint32_t qc_comp_dn_en:1; //1: enable qc comparator on dp 2nd step uint32_t qc_comp_dp_en:1; //1: dpdn divder 1/3 to adc; 0: dpdn divder no div, no res, register-optional dpdm scaling factor for adc uint32_t dn_scal_en:1; //1: dpdn divder 1/3 to adc; 0: dpdn divder no div, no res, register-optional dpdm scaling factor for adc uint32_t dp_scal_en:1; //register-optional output high voltage: //00=open; //01=3.3v; //10=1.8v; //11=2.7v uint32_t ref_dac:2; //dp dn pull-up sourcing current //0: open //1:2ua uint32_t cur_en:1; uint32_t reserved_14_14:1; //1: 1.6v/1.3v; 0: 1.2v/1.1v(default) uint32_t vth_sel:1; //register-optional dn pull-high resistance for apple mode //0：open //1：30k omh uint32_t dn_rh_en:1; //register-optional dp pull-high resistance for apple mode //0：open //1：30k omh uint32_t dp_rh_en:1; // uint32_t dp_hvswitch_on:1; // uint32_t dn_hvswitch_on:1; // uint32_t ibias_en:1; //dp2 sink current for cdp detection,enable/disable by register setting,0:disable,1:enalbe uint32_t dp2_sink:1; // uint32_t cdp_src:1; uint32_t reserved_31_23:9; } REG_analog_dpdn2_bitfiled_TypeDef; typedef struct { union { __IO REG_analog_dpdn2_bitfiled_TypeDef bf;//bitfiled __IO uint32_t word; }; } REG_analog_dpdn2_TypeDef; typedef struct { //adc az comparator bias current select uint32_t ib_cmp_sel:1; //adc input buffer current select uint32_t ib_vbuf_sel:1; uint32_t reserved_31_2:30; } REG_analog_adc_bitfiled_TypeDef; typedef struct { union { __IO REG_analog_adc_bitfiled_TypeDef bf;//bitfiled __IO uint32_t word; }; } REG_analog_adc_TypeDef; typedef struct { //1: osc_24m enable, high active uint32_t en_24m:1; uint32_t reserved_31_1:31; } REG_analog_osc_bitfiled_TypeDef; typedef struct { union { __IO REG_analog_osc_bitfiled_TypeDef bf;//bitfiled __IO uint32_t word; }; } REG_analog_osc_TypeDef; typedef struct { //ls_cs block enable uint32_t en:1; //vb function enable uint32_t vb_en:1; // uint32_t comp_en:1; //current sense wake reference 0:80mv;1:120mv->0:0.45v;1:0.55v uint32_t comp_ref_sel:1; //register-optional current sense amplifier output fliter resistance ;0：500kΩ 1：1000kΩ uint32_t rfilter_sel:1; //enable cs path uint32_t path_sel:1; uint32_t reserved_6_6:1; // uint32_t trim_en:1; // uint32_t trim:1; //current sense soft cfg uint32_t ch_sw:1; uint32_t reserved_31_10:22; } REG_analog_cs1_bitfiled_TypeDef; typedef struct { union { __IO REG_analog_cs1_bitfiled_TypeDef bf;//bitfiled __IO uint32_t word; }; } REG_analog_cs1_TypeDef; typedef struct { //ls_cs block enable uint32_t en:1; //vb function enable uint32_t vb_en:1; // uint32_t comp_en:1; //current sense wake reference 0:80mv;1:120mv->0:0.45v;1:0.55v uint32_t comp_ref_sel:1; //register-optional current sense amplifier output fliter resistance ;0：500kΩ 1：1000kΩ uint32_t rfilter_sel:1; //enable cs path uint32_t path_sel:1; uint32_t reserved_6_6:1; // uint32_t trim_en:1; // uint32_t trim:1; //current sense soft cfg uint32_t ch_sw:1; uint32_t reserved_31_10:22; } REG_analog_cs2_bitfiled_TypeDef; typedef struct { union { __IO REG_analog_cs2_bitfiled_TypeDef bf;//bitfiled __IO uint32_t word; }; } REG_analog_cs2_TypeDef; typedef struct { //register-optional ccx comparator high voltage //0: 1.6v - default usb power //1: 2.6v - // uint32_t ccx_h_th:1; uint32_t reserved_1_1:1; //register-optional ccx comparator low voltage //00/01: 0.2v //10: 0.4v - //11: 0.8v - uint32_t ccx_l_th:2; uint32_t reserved_4_4:1; //1: turn on ccx ovp; 0: turn off ccx ovp uint32_t en_ccx_ovp:1; //0: disable 1: pd buffer enable uint32_t cc_comp_buf_en:1; uint32_t reserved_10_7:4; //1: enable pd db ibias uint32_t db_ibias_en:1; //1: enable pd top uint32_t en_top:1; //select the pd rise time and fall time ; 000=4x;001=3x;010=2x;011=1x;100=8x;101=7x;110=6x;111=5x uint32_t tx_slew_sel:3; //configure the drive strength of the pmos and nmos of the tx driver.ztx_sel<4>=0,increase pmos by 28x,increase nmos by 26y;ztx_sel<3>=1,increase pmos by 16x;ztx_sel<2>=0,increase pmos by 6x;ztx_sel<1>=1,increase nmos by 20x;ztx_sel<0>=0,increase nmos by 6x; uint32_t ztx_sel:6; //1: enable the pd bmc tset uint32_t test_bmc_en:1; //pd txd output test mode. uint32_t txd_tst:1; //register-optional ccx scaling factor for adc;0：open and 1 1: 1000kΩ uint32_t cc1_scal_en:1; //register-optional ccx scaling factor for adc;0：open and 1 1: 1000kΩ uint32_t cc2_scal_en:1; uint32_t reserved_31_26:6; } REG_analog_pd1_bitfiled_TypeDef; typedef struct { union { __IO REG_analog_pd1_bitfiled_TypeDef bf;//bitfiled __IO uint32_t word; }; } REG_analog_pd1_TypeDef; typedef struct { //register-optional ccx comparator high voltage //0: 1.6v - default usb power //1: 2.6v - // uint32_t ccx_h_th:1; uint32_t reserved_1_1:1; //register-optional ccx comparator low voltage //00/01: 0.2v //10: 0.4v - //11: 0.8v - uint32_t ccx_l_th:2; uint32_t reserved_4_4:1; //1: turn on ccx ovp; 0: turn off ccx ovp uint32_t en_ccx_ovp:1; //0: disable 1: pd buffer enable uint32_t cc_comp_buf_en:1; uint32_t reserved_10_7:4; //1: enable pd db ibias uint32_t db_ibias_en:1; //1: enable pd top uint32_t en_top:1; //select the pd rise time and fall time ; 000=4x;001=3x;010=2x;011=1x;100=8x;101=7x;110=6x;111=5x uint32_t tx_slew_sel:3; //configure the drive strength of the pmos and nmos of the tx driver.ztx_sel<4>=0,increase pmos by 28x,increase nmos by 26y;ztx_sel<3>=1,increase pmos by 16x;ztx_sel<2>=0,increase pmos by 6x;ztx_sel<1>=1,increase nmos by 20x;ztx_sel<0>=0,increase nmos by 6x; uint32_t ztx_sel:6; //1: enable the pd bmc tset uint32_t test_bmc_en:1; //pd txd output test mode. uint32_t txd_tst:1; //register-optional ccx scaling factor for adc;0：open and 1 1: 1000kΩ uint32_t cc1_scal_en:1; //register-optional ccx scaling factor for adc;0：open and 1 1: 1000kΩ uint32_t cc2_scal_en:1; uint32_t reserved_31_26:6; } REG_analog_pd2_bitfiled_TypeDef; typedef struct { union { __IO REG_analog_pd2_bitfiled_TypeDef bf;//bitfiled __IO uint32_t word; }; } REG_analog_pd2_TypeDef; typedef struct { //cv standby reference voltage //1. before entering sleep mode, the cv dac voltage is set to the trim value of vst_ref_cv //2. vst_ref_cv is enabled while cv dac is disabled in sleep mode uint32_t ref_sw:1; uint32_t reserved_31_1:31; } REG_analog_cv_loop_bitfiled_TypeDef; typedef struct { union { __IO REG_analog_cv_loop_bitfiled_TypeDef bf;//bitfiled __IO uint32_t word; }; } REG_analog_cv_loop_TypeDef; typedef struct { //atb1 signal selection //0: reserved //<4:1>：adc_tm_sel //<8:5>:ls_cs_tm //<10:9>sel_cs_tm //<14:11>cl_tm_cccv uint32_t atb1_sel:6; //buffer swap uint32_t buf_phase_swap:1; //deafult is 0, register uint32_t atb1_ubuf_ch_en:1; //deafult is 0, register uint32_t atb1_buf_ch_en:1; //deafult is 0, register uint32_t atb2_ch_en:1; //deafult is 0, register uint32_t atb_buf_en:1; //deafult is 0, register uint32_t atb2_ch_atb1int_en:1; uint32_t reserved_15_12:4; //atb2 signal selection //0：reserved //<1>:vin_dis_tm //<2>:vbus_dis_tm uint32_t atb2_sel:4; uint32_t reserved_31_20:12; } REG_analog_tb_bitfiled_TypeDef; typedef struct { union { __IO REG_analog_tb_bitfiled_TypeDef bf;//bitfiled __IO uint32_t word; }; } REG_analog_tb_TypeDef; typedef struct { //dac enable analog circuit //0: disable //1: enable uint32_t en:1; // uint32_t vout_cv_sel:1; uint32_t reserved_31_2:30; } REG_analog_dac_bitfiled_TypeDef; typedef struct { union { __IO REG_analog_dac_bitfiled_TypeDef bf;//bitfiled __IO uint32_t word; }; } REG_analog_dac_TypeDef; typedef struct { //register-optional internal bias current //00: 100ua; //01:20ua; //10:5ua; //11:open uint32_t io1:2; //register-optional internal bias current //00: 100ua; //01:20ua; //10:5ua; //11:open uint32_t io2:2; //set to ifb/ifb1,0:ifb;1:ifb1 uint32_t ibias3_sel:1; //register-optional internal bias current //00: 1000ua; //01:100ua; //10:20ua; //11:open uint32_t ibias3:2; uint32_t reserved_7_7:1; //set to ifb/ifb1,0:ifb;1:ifb1 uint32_t ibias4_sel:1; //register-optional internal bias current //00: 100ua; //01:20ua; //10:5ua; //11:open uint32_t ibias4:2; uint32_t reserved_31_11:21; } REG_analog_pucur_bitfiled_TypeDef; typedef struct { union { __IO REG_analog_pucur_bitfiled_TypeDef bf;//bitfiled __IO uint32_t word; }; } REG_analog_pucur_TypeDef; typedef struct { //ldo1p5 output voltage config: //00: 1.5v; //01: 1.605v; //10:1.35v; //11: 1.65v uint32_t vconfig:2; uint32_t reserved_31_2:30; } REG_analog_ldo1p5v_bitfiled_TypeDef; typedef struct { union { __IO REG_analog_ldo1p5v_bitfiled_TypeDef bf;//bitfiled __IO uint32_t word; }; } REG_analog_ldo1p5v_TypeDef; typedef struct { //1: vd circuit enable uint32_t enable:1; //d2a_vd_sample_time= vd_ls_sample_tst || vd_ls_sample_func(ctrl) uint32_t ls_sample_tst:1; //vd high side sample on , d2a_vd_hl_switch = high_en & (!low_en) uint32_t high_en:1; //vd low side sample on ,cannot cfg high_en low_en =1 meanwhile, uint32_t low_en:1; //1=disable uint32_t dis_mask:1; //register-optional vd rising edge masking time 1:tmask time 240ns 0:tmask time is 120ns uint32_t mask_sel:1; //vd rising edge threshold for ac off detection ,0: 70mv；1：100mv register-optional ringing comparator rising threshold,0: 70mv；1：100mv uint32_t ris_edge_sel:1; //register-optional vd scaling factor for adc, 0：open and 1 1: 1000kΩ &2 uint32_t scale_en:1; // uint32_t ls_res_en:1; uint32_t reserved_31_9:23; } REG_analog_vd_bitfiled_TypeDef; typedef struct { union { __IO REG_analog_vd_bitfiled_TypeDef bf;//bitfiled __IO uint32_t word; }; } REG_analog_vd_TypeDef; typedef struct { //1'b: discharge vin enable uint32_t en0:1; //register-optional vin discharging current //2'b00:50ma //2'b01:75ma //2'b10:100ma //2'b11:125ma uint32_t cur0:2; // uint32_t tm:1; uint32_t reserved_7_4:4; //1'b: discharge vin enable uint32_t en1:1; //register-optional vin1 discharging current //2'b00:50ma //2'b01:75ma //2'b10:100ma //2'b11:125ma uint32_t cur1:2; uint32_t reserved_15_11:5; //1'b: discharge vin enable uint32_t en2:1; //register-optional vin2 discharging current //2'b00:50ma //2'b01:75ma //2'b10:100ma //2'b11:125ma uint32_t cur2:2; uint32_t reserved_31_19:13; } REG_analog_vin_dis_bitfiled_TypeDef; typedef struct { union { __IO REG_analog_vin_dis_bitfiled_TypeDef bf;//bitfiled __IO uint32_t word; }; } REG_analog_vin_dis_TypeDef; typedef struct { //vbus discharge function enable, uint32_t dis_en:1; // uint32_t dis_en_tst:1; //register-optional vbus over-current threshold; 0:0.2v 1:0.3v uint32_t oc_sel:1; //register-optional output short circuit protection；1：enable；0：disable uint32_t oc_en:1; uint32_t reserved_31_4:28; } REG_analog_vbus1_bitfiled_TypeDef; typedef struct { union { __IO REG_analog_vbus1_bitfiled_TypeDef bf;//bitfiled __IO uint32_t word; }; } REG_analog_vbus1_TypeDef; typedef struct { //vbus discharge function enable uint32_t dis_en:1; // uint32_t dis_en_tst:1; //register-optional vbus over-current threshold; 0:0.2v 1:0.3v uint32_t oc_sel:1; //register-optional output short circuit protection；1：enable；0：disable uint32_t oc_en:1; uint32_t reserved_31_4:28; } REG_analog_vbus2_bitfiled_TypeDef; typedef struct { union { __IO REG_analog_vbus2_bitfiled_TypeDef bf;//bitfiled __IO uint32_t word; }; } REG_analog_vbus2_TypeDef; typedef struct { //cc loop block enable //0: disable //1: enable uint32_t loop_en:1; uint32_t reserved_31_1:31; } REG_analog_cc_bitfiled_TypeDef; typedef struct { union { __IO REG_analog_cc_bitfiled_TypeDef bf;//bitfiled __IO uint32_t word; }; } REG_analog_cc_TypeDef; typedef struct { //cv_loop enable //0: disable //1: enable uint32_t loop_en:1; uint32_t reserved_31_1:31; } REG_analog_cv_bitfiled_TypeDef; typedef struct { union { __IO REG_analog_cv_bitfiled_TypeDef bf;//bitfiled __IO uint32_t word; }; } REG_analog_cv_TypeDef; typedef struct { // uint32_t leak_test:1; // uint32_t mode:1; // uint32_t hi:1; // uint32_t low:1; uint32_t reserved_31_4:28; } REG_analog_opto_bitfiled_TypeDef; typedef struct { union { __IO REG_analog_opto_bitfiled_TypeDef bf;//bitfiled __IO uint32_t word; }; } REG_analog_opto_TypeDef; typedef struct { //negative voltage enable uint32_t en_b:1; uint32_t reserved_31_1:31; } REG_analog_debug_bitfiled_TypeDef; typedef struct { union { __IO REG_analog_debug_bitfiled_TypeDef bf;//bitfiled __IO uint32_t word; }; } REG_analog_debug_TypeDef; typedef struct { //d2a_ana_ctrl_spare. bit[0]:ctrl vd rvds,canbe on/off //bit[7:4]: reserved // uint32_t spare:8; uint32_t reserved_31_8:24; } REG_analog_ana_ctrl_bitfiled_TypeDef; typedef struct { union { __IO REG_analog_ana_ctrl_bitfiled_TypeDef bf;//bitfiled __IO uint32_t word; }; } REG_analog_ana_ctrl_TypeDef; typedef struct { //i2c pin function-sel scl //0: gp2 //1:cc1_1 //2: gp6 //3:vfb uint32_t io_sel_scl1:2; uint32_t reserved_3_2:2; //i2c pin function-sel sda //0: gp3 //1:cc2_1 //2: comp1 //3:gp7 uint32_t io_sel_sda1:2; uint32_t reserved_7_6:2; //i2c pin function-sel scl //0,3: gp4 //1:cc1_2 //2: fb2 uint32_t io_sel_scl2:2; uint32_t reserved_11_10:2; //i2c pin function-sel sda //0,3: gp5 //1:cc2_2 //2: comp2 uint32_t io_sel_sda2:2; uint32_t reserved_15_14:2; //00:open //01: 3.3v //10:1.8v //11:2.7v uint32_t vset1:2; //register-optional pull-high resistance; 0:open 1:5k uint32_t rh1:1; uint32_t reserved_23_19:5; //00:open //01: 3.3v //10:1.8v //11:2.7v uint32_t vset2:2; //register-optional pull-high resistance; 0:open 1:5k uint32_t rh2:1; uint32_t reserved_31_27:5; } REG_analog_i2c_bitfiled_TypeDef; typedef struct { union { __IO REG_analog_i2c_bitfiled_TypeDef bf;//bitfiled __IO uint32_t word; }; } REG_analog_i2c_TypeDef; typedef struct { //rx gain selection uint32_t gain_sel:2; //rx vhys selection uint32_t hys_sel:2; //enable pd_rx test function uint32_t test_en:1; //enable pd_rx vref test uint32_t vbias_en:1; uint32_t reserved_31_6:26; } REG_analog_pd1_rx_bitfiled_TypeDef; typedef struct { union { __IO REG_analog_pd1_rx_bitfiled_TypeDef bf;//bitfiled __IO uint32_t word; }; } REG_analog_pd1_rx_TypeDef; typedef struct { //rx gain selection uint32_t gain_sel:2; //rx vhys selection uint32_t hys_sel:2; //enable pd_rx test function uint32_t test_en:1; //enable pd_rx vref test uint32_t vbias_en:1; uint32_t reserved_31_6:26; } REG_analog_pd2_rx_bitfiled_TypeDef; typedef struct { union { __IO REG_analog_pd2_rx_bitfiled_TypeDef bf;//bitfiled __IO uint32_t word; }; } REG_analog_pd2_rx_TypeDef; typedef struct { //lps detection through voltage drop)；1：enable；0：disable uint32_t vds1_en:1; //register-optional voltage drop of the load switch;00:15mv 01:20mv 10: 25mv 11:30mv uint32_t vds1_sel:2; //lps detection through voltage drop)；1：enable；0：disable uint32_t vds2_en:1; //register-optional voltage drop of the load switch;00:15mv 01:20mv 10: 25mv 11:30mv uint32_t vds2_sel:2; uint32_t reserved_31_6:26; } REG_analog_lps_bitfiled_TypeDef; typedef struct { union { __IO REG_analog_lps_bitfiled_TypeDef bf;//bitfiled __IO uint32_t word; }; } REG_analog_lps_TypeDef; typedef struct { //enable cp, firmware programmable gate soft start for capacitive load；1：enable；0：disable uint32_t cp_en:1; //gate soft-start period uint32_t on_sel:2; uint32_t reserved_3_3:1; //0:turn on external power nmos fet; //1:turn off external power nmos fet. uint32_t driver_en:1; //protect gate pull low；0： pull high；1： pull low uint32_t pull_low:1; //gate res load ctrl uint32_t resload:1; //gate uvp；1：enable；0：disable uint32_t uvp_en:1; //gate driver current max uint32_t fast_on:1; // uint32_t hz:1; //enable cp ilim 0:disable 1:enable uint32_t ilim:1; //disable cp ilim selection 0:enable 1:disable uint32_t dis_ilim:1; //vcp output vlotage , analog register uint32_t voltage_sel:3; uint32_t reserved_31_15:17; } REG_analog_gate1_bitfiled_TypeDef; typedef struct { union { __IO REG_analog_gate1_bitfiled_TypeDef bf;//bitfiled __IO uint32_t word; }; } REG_analog_gate1_TypeDef; typedef struct { //enable cp, firmware programmable gate soft start for capacitive load；1：enable；0：disable uint32_t cp_en:1; //gate soft-start period uint32_t on_sel:2; uint32_t reserved_3_3:1; //0:turn on external power nmos fet; //1:turn off external power nmos fet. uint32_t driver_en:1; //protect gate pull low；0： pull high；1： pull low uint32_t pull_low:1; //gate res load ctrl uint32_t resload:1; //gate uvp；1：enable；0：disable uint32_t uvp_en:1; //gate driver current max uint32_t fast_on:1; // uint32_t hz:1; //enable cp ilim 0:disable 1:enable uint32_t ilim:1; //disable cp ilim selection 0:enable 1:disable uint32_t dis_ilim:1; //vcp output vlotage , analog register uint32_t voltage_sel:3; uint32_t reserved_31_15:17; } REG_analog_gate2_bitfiled_TypeDef; typedef struct { union { __IO REG_analog_gate2_bitfiled_TypeDef bf;//bitfiled __IO uint32_t word; }; } REG_analog_gate2_TypeDef; typedef struct { //enable cp, firmware programmable gate soft start for capacitive load；1：enable；0：disable uint32_t cp_en:1; //gate soft-start period uint32_t on_sel:2; uint32_t reserved_3_3:1; //0:turn on external power nmos fet; //1:turn off external power nmos fet. uint32_t driver_en:1; //protect gate pull low；0： pull high；1： pull low uint32_t pull_low:1; //gate res load ctrl uint32_t resload:1; //gate uvp；1：enable；0：disable uint32_t uvp_en:1; //gate driver current max uint32_t fast_on:1; // uint32_t hz:1; //enable cp ilim 0:disable 1:enable uint32_t ilim:1; //disable cp ilim selection 0:enable 1:disable uint32_t dis_ilim:1; //vcp output vlotage , analog register uint32_t voltage_sel:3; uint32_t reserved_31_15:17; } REG_analog_gate3_bitfiled_TypeDef; typedef struct { union { __IO REG_analog_gate3_bitfiled_TypeDef bf;//bitfiled __IO uint32_t word; }; } REG_analog_gate3_TypeDef; typedef struct { //1:enable digital input, 0-9 is gpio, uint32_t ie:10; //1:enable analog input, 0-9 is gpio, uint32_t aie:10; uint32_t reserved_31_20:12; } REG_analog_gp_bitfiled_TypeDef; typedef struct { union { __IO REG_analog_gp_bitfiled_TypeDef bf;//bitfiled __IO uint32_t word; }; } REG_analog_gp_TypeDef; typedef struct { //1:enable digital input uint32_t cc1_1_ie:1; //1:enable digital input uint32_t cc2_1_ie:1; //1:enable digital input uint32_t cc1_2_ie:1; //1:enable digital input uint32_t cc2_2_ie:1; //1:enable digital input uint32_t comp1_ie:1; //1:enable digital input uint32_t fb2_ie:1; //1:enable digital input uint32_t comp2_ie:1; //1:enable digital input uint32_t vfb_ie:1; uint32_t reserved_15_8:8; //1:enable analog input, uint32_t cc1_1_aie:1; //1:enable analog input, uint32_t cc2_1_aie:1; //1:enable analog input, uint32_t cc1_2_aie:1; //1:enable analog input, uint32_t cc2_2_aie:1; //1:enable analog input, uint32_t comp1_aie:1; //1:enable analog input, uint32_t fb2_aie:1; //1:enable analog input, uint32_t comp2_aie:1; //1:enable analog input, uint32_t vfb_aie:1; uint32_t reserved_31_24:8; } REG_analog_io_bitfiled_TypeDef; typedef struct { union { __IO REG_analog_io_bitfiled_TypeDef bf;//bitfiled __IO uint32_t word; }; } REG_analog_io_TypeDef; typedef struct { //1: enable open drain output (default open drain), 16-21 is gpio, 22:cc1_1, 23: cc2_1, 24:cc1_2, 25:cc2_2, 26:fb1, 27:comp1, 28:fb2 , 29:comp2, 30:csp1, 31:csp2 uint32_t oden:18; uint32_t reserved_31_18:14; } REG_analog_gp0_bitfiled_TypeDef; typedef struct { union { __IO REG_analog_gp0_bitfiled_TypeDef bf;//bitfiled __IO uint32_t word; }; } REG_analog_gp0_TypeDef; typedef struct { //1:gp tie high uint32_t h_en:10; //1:gp tie low uint32_t l_en:10; uint32_t reserved_31_20:12; } REG_analog_gp_tie_bitfiled_TypeDef; typedef struct { union { __IO REG_analog_gp_tie_bitfiled_TypeDef bf;//bitfiled __IO uint32_t word; }; } REG_analog_gp_tie_TypeDef; typedef struct { //1:gp tie high uint32_t cc1_1_h_en:1; //1:gp tie high uint32_t cc2_1_h_en:1; //1:gp tie high uint32_t cc1_2_h_en:1; //1:gp tie high uint32_t cc2_2_h_en:1; //1:gp tie high uint32_t comp1_h_en:1; //1:gp tie high uint32_t fb2_h_en:1; //1:gp tie high uint32_t comp2_h_en:1; //1:gp tie high uint32_t vfb_h_en:1; uint32_t reserved_15_8:8; //1:gp tie low uint32_t cc1_1_l_en:1; //1:gp tie low uint32_t cc2_1_l_en:1; //1:gp tie low uint32_t cc1_2_l_en:1; //1:gp tie low uint32_t cc2_2_l_en:1; //1:gp tie low uint32_t comp1_l_en:1; //1:gp tie low uint32_t fb2_l_en:1; //1:gp tie low uint32_t comp2_l_en:1; //1:gp tie low uint32_t vfb_l_en:1; uint32_t reserved_31_24:8; } REG_analog_io_tie_bitfiled_TypeDef; typedef struct { union { __IO REG_analog_io_tie_bitfiled_TypeDef bf;//bitfiled __IO uint32_t word; }; } REG_analog_io_tie_TypeDef; typedef struct { //for mtp cp test vddh cfg uint32_t ldo5p7v_en:1; uint32_t reserved_31_1:31; } REG_analog_mtp_bitfiled_TypeDef; typedef struct { union { __IO REG_analog_mtp_bitfiled_TypeDef bf;//bitfiled __IO uint32_t word; }; } REG_analog_mtp_TypeDef; typedef struct { // uint32_t sel:1; uint32_t reserved_31_1:31; } REG_analog_vin_bitfiled_TypeDef; typedef struct { union { __IO REG_analog_vin_bitfiled_TypeDef bf;//bitfiled __IO uint32_t word; }; } REG_analog_vin_TypeDef; typedef struct { // uint32_t leak_en:1; uint32_t reserved_31_1:31; } REG_analog_csn1_bitfiled_TypeDef; typedef struct { union { __IO REG_analog_csn1_bitfiled_TypeDef bf;//bitfiled __IO uint32_t word; }; } REG_analog_csn1_TypeDef; typedef struct { // uint32_t leak_en:1; uint32_t reserved_31_1:31; } REG_analog_csn2_bitfiled_TypeDef; typedef struct { union { __IO REG_analog_csn2_bitfiled_TypeDef bf;//bitfiled __IO uint32_t word; }; } REG_analog_csn2_TypeDef; typedef struct { //comp enable 0:disable ,1:enable uint32_t gmcomp_en:1; //register-optional transconductance1 of error amplifier,0:200ua/v,1;100ua/v uint32_t comp_gmset:1; //register-optional transconductance1 of current loop error amplifier,0:50/250 ua/v,1:100/500ua/v uint32_t cc_gmset:1; uint32_t reserved_3_3:1; //register-optional transconductance 1 of voltage loop error amplifier,0:75ua/v,1;150ua/v uint32_t cv_gmset:1; uint32_t reserved_5_5:1; //d2a_chose_fb_path uint32_t fbpath_en:1; //internal zero point resistor1 for cc loop compensation;00:- ; 01:1k; 10:5k;11:10k uint32_t rz:2; //protect fb pull high；1： enable；0： disable； uint32_t fbpullhi:1; uint32_t reserved_31_10:22; } REG_analog_fb1_bitfiled_TypeDef; typedef struct { union { __IO REG_analog_fb1_bitfiled_TypeDef bf;//bitfiled __IO uint32_t word; }; } REG_analog_fb1_TypeDef; typedef struct { //fbcv enable 0:disable ,1:enable uint32_t en:1; uint32_t reserved_31_1:31; } REG_analog_fb1_fbcv_bitfiled_TypeDef; typedef struct { union { __IO REG_analog_fb1_fbcv_bitfiled_TypeDef bf;//bitfiled __IO uint32_t word; }; } REG_analog_fb1_fbcv_TypeDef; typedef struct { // uint32_t mode:1; uint32_t reserved_31_1:31; } REG_analog_fb1_fb_bitfiled_TypeDef; typedef struct { union { __IO REG_analog_fb1_fb_bitfiled_TypeDef bf;//bitfiled __IO uint32_t word; }; } REG_analog_fb1_fb_TypeDef; typedef struct { //comp enable 0:disable ,1:enable uint32_t gmcomp_en:1; //register-optional transconductance1 of error amplifier,0:200ua/v,1;100ua/v uint32_t comp_gmset:1; //register-optional transconductance1 of current loop error amplifier,0:50/250 ua/v,1:100/500ua/v uint32_t cc_gmset:1; uint32_t reserved_3_3:1; //register-optional transconductance 1 of voltage loop error amplifier,0:75ua/v,1;150ua/v uint32_t cv_gmset:1; uint32_t reserved_5_5:1; //d2a_chose_fb_path uint32_t fbpath_en:1; //internal zero point resistor1 for cc loop compensation;00:- ; 01:1k; 10:5k;11:10k uint32_t rz:2; //protect fb pull high；1： enable；0： disable； uint32_t fbpullhi:1; uint32_t reserved_31_10:22; } REG_analog_fb2_bitfiled_TypeDef; typedef struct { union { __IO REG_analog_fb2_bitfiled_TypeDef bf;//bitfiled __IO uint32_t word; }; } REG_analog_fb2_TypeDef; typedef struct { //fbcv enable 0:disable ,1:enable uint32_t en:1; uint32_t reserved_31_1:31; } REG_analog_fb2_fbcv_bitfiled_TypeDef; typedef struct { union { __IO REG_analog_fb2_fbcv_bitfiled_TypeDef bf;//bitfiled __IO uint32_t word; }; } REG_analog_fb2_fbcv_TypeDef; typedef struct { // uint32_t mode:1; uint32_t reserved_31_1:31; } REG_analog_fb2_fb_bitfiled_TypeDef; typedef struct { union { __IO REG_analog_fb2_fb_bitfiled_TypeDef bf;//bitfiled __IO uint32_t word; }; } REG_analog_fb2_fb_TypeDef; typedef struct { //1'= ot triggered uint32_t ot:1; uint32_t reserved_31_1:31; } REG_analog_prot_chip_bitfiled_TypeDef; typedef struct { union { __IO REG_analog_prot_chip_bitfiled_TypeDef bf;//bitfiled __IO uint32_t word; }; } REG_analog_prot_chip_TypeDef; typedef struct { //vin > k*vref_cv (k=1.15/1.2/1.25) uint32_t ov:1; //ratio protection uv uint32_t ratiop_uv:1; //ratio protection ov uint32_t ratiop_ov:1; uint32_t reserved_31_3:29; } REG_analog_vin0_bitfiled_TypeDef; typedef struct { union { __IO REG_analog_vin0_bitfiled_TypeDef bf;//bitfiled __IO uint32_t word; }; } REG_analog_vin0_TypeDef; typedef struct { //vin > k*vref_cv (k=1.15/1.2/1.25) uint32_t ov:1; //ratio protection uv uint32_t ratiop_uv:1; //ratio protection ov uint32_t ratiop_ov:1; uint32_t reserved_31_3:29; } REG_analog_vin1_bitfiled_TypeDef; typedef struct { union { __IO REG_analog_vin1_bitfiled_TypeDef bf;//bitfiled __IO uint32_t word; }; } REG_analog_vin1_TypeDef; typedef struct { //vin > k*vref_cv (k=1.15/1.2/1.25) uint32_t ov:1; //ratio protection uv uint32_t ratiop_uv:1; //ratio protection ov uint32_t ratiop_ov:1; uint32_t reserved_31_3:29; } REG_analog_vin2_bitfiled_TypeDef; typedef struct { union { __IO REG_analog_vin2_bitfiled_TypeDef bf;//bitfiled __IO uint32_t word; }; } REG_analog_vin2_TypeDef; typedef struct { //dn gt 0.4v uint32_t comp_0p4v_dn:1; //dn gt 2.0v uint32_t comp_2p0v_dn:1; //dp gt 0.4v uint32_t comp_0p4v_dp:1; //dp gt 2.0v uint32_t comp_2p0v_dp:1; //1: dp/dn voltage higher than 5.5v uint32_t ov:1; uint32_t reserved_31_5:27; } REG_analog_dpdn10_bitfiled_TypeDef; typedef struct { union { __IO REG_analog_dpdn10_bitfiled_TypeDef bf;//bitfiled __IO uint32_t word; }; } REG_analog_dpdn10_TypeDef; typedef struct { //dn gt 0.4v uint32_t comp_0p4v_dn:1; //dn gt 2.0v uint32_t comp_2p0v_dn:1; //dp gt 0.4v uint32_t comp_0p4v_dp:1; //dp gt 2.0v uint32_t comp_2p0v_dp:1; //1: dp/dn voltage higher than 5.5v uint32_t ov:1; uint32_t reserved_31_5:27; } REG_analog_dpdn20_bitfiled_TypeDef; typedef struct { union { __IO REG_analog_dpdn20_bitfiled_TypeDef bf;//bitfiled __IO uint32_t word; }; } REG_analog_dpdn20_TypeDef; typedef struct { //pd cc1 low level(0.8v) comparator output uint32_t cc1_comp_vlth:1; //pd cc1 high level comparator output uint32_t cc1_comp_vhth:1; //pd cc2 low level(0.8v) comparator output uint32_t cc2_comp_vlth:1; //pd cc2 high level comparator output uint32_t cc2_comp_vhth:1; //1=measured cc* input is higher than 2.6v/2.8v/3.0v uint32_t cc1_comp_detach:1; //1=measured cc* input is higher than 2.6v/2.8v/3.0v uint32_t cc2_comp_detach:1; //pd_rxd_deb uint32_t rxd:1; //pd_vcon_oc_deb uint32_t vcon_oc:1; //pd_ccx_ovp_deb uint32_t ccx_ovp:1; uint32_t reserved_31_9:23; } REG_analog_pd10_bitfiled_TypeDef; typedef struct { union { __IO REG_analog_pd10_bitfiled_TypeDef bf;//bitfiled __IO uint32_t word; }; } REG_analog_pd10_TypeDef; typedef struct { //pd cc1 low level(0.8v) comparator output uint32_t cc1_comp_vlth:1; //pd cc1 high level comparator output uint32_t cc1_comp_vhth:1; //pd cc2 low level(0.8v) comparator output uint32_t cc2_comp_vlth:1; //pd cc2 high level comparator output uint32_t cc2_comp_vhth:1; //1=measured cc* input is higher than 2.6v/2.8v/3.0v uint32_t cc1_comp_detach:1; //1=measured cc* input is higher than 2.6v/2.8v/3.0v uint32_t cc2_comp_detach:1; //pd_rxd_deb uint32_t rxd:1; //pd_vcon_oc_deb uint32_t vcon_oc:1; //pd_ccx_ovp_deb uint32_t ccx_ovp:1; uint32_t reserved_31_9:23; } REG_analog_pd20_bitfiled_TypeDef; typedef struct { union { __IO REG_analog_pd20_bitfiled_TypeDef bf;//bitfiled __IO uint32_t word; }; } REG_analog_pd20_TypeDef; typedef struct { //cs_wake1 deb uint32_t wake:1; uint32_t reserved_31_1:31; } REG_analog_cs10_bitfiled_TypeDef; typedef struct { union { __IO REG_analog_cs10_bitfiled_TypeDef bf;//bitfiled __IO uint32_t word; }; } REG_analog_cs10_TypeDef; typedef struct { //cs_wake2 deb uint32_t wake:1; uint32_t reserved_31_1:31; } REG_analog_cs20_bitfiled_TypeDef; typedef struct { union { __IO REG_analog_cs20_bitfiled_TypeDef bf;//bitfiled __IO uint32_t word; }; } REG_analog_cs20_TypeDef; typedef struct { //gp_i dp_deb uint32_t dp1:1; //gp_i_dn_deb uint32_t dn1:1; //gp_i dp_deb uint32_t dp2:1; //gp_i dn_deb uint32_t dn2:1; uint32_t reserved_31_4:28; } REG_analog_gp_i_bitfiled_TypeDef; typedef struct { union { __IO REG_analog_gp_i_bitfiled_TypeDef bf;//bitfiled __IO uint32_t word; }; } REG_analog_gp_i_TypeDef; typedef struct { //v2_ocp_deb uint32_t ocp:1; uint32_t reserved_31_1:31; } REG_analog_v2_bitfiled_TypeDef; typedef struct { union { __IO REG_analog_v2_bitfiled_TypeDef bf;//bitfiled __IO uint32_t word; }; } REG_analog_v2_TypeDef; typedef struct { //short_vds_comp_vbus1_oc_deb uint32_t oc:1; uint32_t reserved_31_1:31; } REG_analog_vbus10_bitfiled_TypeDef; typedef struct { union { __IO REG_analog_vbus10_bitfiled_TypeDef bf;//bitfiled __IO uint32_t word; }; } REG_analog_vbus10_TypeDef; typedef struct { //short_vds_comp_vbus1_oc_deb uint32_t oc:1; uint32_t reserved_31_1:31; } REG_analog_vbus20_bitfiled_TypeDef; typedef struct { union { __IO REG_analog_vbus20_bitfiled_TypeDef bf;//bitfiled __IO uint32_t word; }; } REG_analog_vbus20_TypeDef; typedef struct { //gate on status uint32_t drive_on:1; //cp saturation uint32_t sat:1; //gate uvp flag uint32_t uvp:1; uint32_t reserved_31_3:29; } REG_analog_gate10_bitfiled_TypeDef; typedef struct { union { __IO REG_analog_gate10_bitfiled_TypeDef bf;//bitfiled __IO uint32_t word; }; } REG_analog_gate10_TypeDef; typedef struct { //gate on status uint32_t drive_on:1; //cp saturation uint32_t sat:1; //gate1 uvp flag uint32_t uvp:1; uint32_t reserved_31_3:29; } REG_analog_gate20_bitfiled_TypeDef; typedef struct { union { __IO REG_analog_gate20_bitfiled_TypeDef bf;//bitfiled __IO uint32_t word; }; } REG_analog_gate20_TypeDef; typedef struct { //gate on status uint32_t drive_on:1; //cp saturation uint32_t sat:1; //gate2 uvp flag uint32_t uvp:1; uint32_t reserved_31_3:29; } REG_analog_gate30_bitfiled_TypeDef; typedef struct { union { __IO REG_analog_gate30_bitfiled_TypeDef bf;//bitfiled __IO uint32_t word; }; } REG_analog_gate30_TypeDef; typedef struct { //lps detection through voltage drop) uint32_t vds1:1; //lps detection through voltage drop) uint32_t vds2:1; uint32_t reserved_31_2:30; } REG_analog_lps0_bitfiled_TypeDef; typedef struct { union { __IO REG_analog_lps0_bitfiled_TypeDef bf;//bitfiled __IO uint32_t word; }; } REG_analog_lps0_TypeDef; typedef struct { //from metal uint32_t product_id:8; //from metal uint32_t device_id:8; uint32_t reserved_31_16:16; } REG_analog_ADDR4000FB00_bitfiled_TypeDef; typedef struct { union { __IO REG_analog_ADDR4000FB00_bitfiled_TypeDef bf;//bitfiled __IO uint32_t word; }; } REG_analog_ADDR4000FB00_TypeDef; //----------------------------------------------------------------------------- // memory map #define REG_ANALOG_PROT_BASE 0x4000F800 #define REG_ANALOG_DPDN1_BASE 0x4000F804 #define REG_ANALOG_DPDN2_BASE 0x4000F808 #define REG_ANALOG_ADC_BASE 0x4000F810 #define REG_ANALOG_OSC_BASE 0x4000F814 #define REG_ANALOG_CS1_BASE 0x4000F818 #define REG_ANALOG_CS2_BASE 0x4000F81C #define REG_ANALOG_PD1_BASE 0x4000F820 #define REG_ANALOG_PD2_BASE 0x4000F824 #define REG_ANALOG_CV_LOOP_BASE 0x4000F830 #define REG_ANALOG_TB_BASE 0x4000F834 #define REG_ANALOG_DAC_BASE 0x4000F838 #define REG_ANALOG_PUCUR_BASE 0x4000F83C #define REG_ANALOG_LDO1P5V_BASE 0x4000F840 #define REG_ANALOG_VD_BASE 0x4000F848 #define REG_ANALOG_VIN_DIS_BASE 0x4000F84C #define REG_ANALOG_VBUS1_BASE 0x4000F850 #define REG_ANALOG_VBUS2_BASE 0x4000F854 #define REG_ANALOG_CC_BASE 0x4000F858 #define REG_ANALOG_CV_BASE 0x4000F85C #define REG_ANALOG_OPTO_BASE 0x4000F860 #define REG_ANALOG_DEBUG_BASE 0x4000F864 #define REG_ANALOG_ANA_CTRL_BASE 0x4000F868 #define REG_ANALOG_I2C_BASE 0x4000F86C #define REG_ANALOG_PD1_RX_BASE 0x4000F878 #define REG_ANALOG_PD2_RX_BASE 0x4000F87C #define REG_ANALOG_LPS_BASE 0x4000F880 #define REG_ANALOG_GATE1_BASE 0x4000F884 #define REG_ANALOG_GATE2_BASE 0x4000F888 #define REG_ANALOG_GATE3_BASE 0x4000F88C #define REG_ANALOG_GP_BASE 0x4000F890 #define REG_ANALOG_IO_BASE 0x4000F894 #define REG_ANALOG_GP0_BASE 0x4000F898 #define REG_ANALOG_GP_TIE_BASE 0x4000F89C #define REG_ANALOG_IO_TIE_BASE 0x4000F8A0 #define REG_ANALOG_MTP_BASE 0x4000F8A4 #define REG_ANALOG_VIN_BASE 0x4000F8A8 #define REG_ANALOG_CSN1_BASE 0x4000F8AC #define REG_ANALOG_CSN2_BASE 0x4000F8B0 #define REG_ANALOG_FB1_BASE 0x4000F8B4 #define REG_ANALOG_FB1_FBCV_BASE 0x4000F8B8 #define REG_ANALOG_FB1_FB_BASE 0x4000F8BC #define REG_ANALOG_FB2_BASE 0x4000F8C0 #define REG_ANALOG_FB2_FBCV_BASE 0x4000F8C4 #define REG_ANALOG_FB2_FB_BASE 0x4000F8C8 #define REG_ANALOG_PROT_CHIP_BASE 0x4000FA00 #define REG_ANALOG_VIN0_BASE 0x4000FA04 #define REG_ANALOG_VIN1_BASE 0x4000FA08 #define REG_ANALOG_VIN2_BASE 0x4000FA0C #define REG_ANALOG_DPDN10_BASE 0x4000FA10 #define REG_ANALOG_DPDN20_BASE 0x4000FA18 #define REG_ANALOG_PD10_BASE 0x4000FA20 #define REG_ANALOG_PD20_BASE 0x4000FA24 #define REG_ANALOG_CS10_BASE 0x4000FA28 #define REG_ANALOG_CS20_BASE 0x4000FA2C #define REG_ANALOG_GP_I_BASE 0x4000FA30 #define REG_ANALOG_V2_BASE 0x4000FA38 #define REG_ANALOG_VBUS10_BASE 0x4000FA3C #define REG_ANALOG_VBUS20_BASE 0x4000FA40 #define REG_ANALOG_GATE10_BASE 0x4000FA44 #define REG_ANALOG_GATE20_BASE 0x4000FA48 #define REG_ANALOG_GATE30_BASE 0x4000FA4C #define REG_ANALOG_LPS0_BASE 0x4000FA50 #define REG_ANALOG_ADDR4000FB00_BASE 0x4000FB00 //----------------------------------------------------------------------------- // declaration #define REG_ANALOG_PROT ((REG_analog_prot_TypeDef *) REG_ANALOG_PROT_BASE ) #define REG_ANALOG_DPDN1 ((REG_analog_dpdn1_TypeDef *) REG_ANALOG_DPDN1_BASE ) #define REG_ANALOG_DPDN2 ((REG_analog_dpdn2_TypeDef *) REG_ANALOG_DPDN2_BASE ) #define REG_ANALOG_ADC ((REG_analog_adc_TypeDef *) REG_ANALOG_ADC_BASE ) #define REG_ANALOG_OSC ((REG_analog_osc_TypeDef *) REG_ANALOG_OSC_BASE ) #define REG_ANALOG_CS1 ((REG_analog_cs1_TypeDef *) REG_ANALOG_CS1_BASE ) #define REG_ANALOG_CS2 ((REG_analog_cs2_TypeDef *) REG_ANALOG_CS2_BASE ) #define REG_ANALOG_PD1 ((REG_analog_pd1_TypeDef *) REG_ANALOG_PD1_BASE ) #define REG_ANALOG_PD2 ((REG_analog_pd2_TypeDef *) REG_ANALOG_PD2_BASE ) #define REG_ANALOG_CV_LOOP ((REG_analog_cv_loop_TypeDef *) REG_ANALOG_CV_LOOP_BASE ) #define REG_ANALOG_TB ((REG_analog_tb_TypeDef *) REG_ANALOG_TB_BASE ) #define REG_ANALOG_DAC ((REG_analog_dac_TypeDef *) REG_ANALOG_DAC_BASE ) #define REG_ANALOG_PUCUR ((REG_analog_pucur_TypeDef *) REG_ANALOG_PUCUR_BASE ) #define REG_ANALOG_LDO1P5V ((REG_analog_ldo1p5v_TypeDef *) REG_ANALOG_LDO1P5V_BASE ) #define REG_ANALOG_VD ((REG_analog_vd_TypeDef *) REG_ANALOG_VD_BASE ) #define REG_ANALOG_VIN_DIS ((REG_analog_vin_dis_TypeDef *) REG_ANALOG_VIN_DIS_BASE ) #define REG_ANALOG_VBUS1 ((REG_analog_vbus1_TypeDef *) REG_ANALOG_VBUS1_BASE ) #define REG_ANALOG_VBUS2 ((REG_analog_vbus2_TypeDef *) REG_ANALOG_VBUS2_BASE ) #define REG_ANALOG_CC ((REG_analog_cc_TypeDef *) REG_ANALOG_CC_BASE ) #define REG_ANALOG_CV ((REG_analog_cv_TypeDef *) REG_ANALOG_CV_BASE ) #define REG_ANALOG_OPTO ((REG_analog_opto_TypeDef *) REG_ANALOG_OPTO_BASE ) #define REG_ANALOG_DEBUG ((REG_analog_debug_TypeDef *) REG_ANALOG_DEBUG_BASE ) #define REG_ANALOG_ANA_CTRL ((REG_analog_ana_ctrl_TypeDef *) REG_ANALOG_ANA_CTRL_BASE ) #define REG_ANALOG_I2C ((REG_analog_i2c_TypeDef *) REG_ANALOG_I2C_BASE ) #define REG_ANALOG_PD1_RX ((REG_analog_pd1_rx_TypeDef *) REG_ANALOG_PD1_RX_BASE ) #define REG_ANALOG_PD2_RX ((REG_analog_pd2_rx_TypeDef *) REG_ANALOG_PD2_RX_BASE ) #define REG_ANALOG_LPS ((REG_analog_lps_TypeDef *) REG_ANALOG_LPS_BASE ) #define REG_ANALOG_GATE1 ((REG_analog_gate1_TypeDef *) REG_ANALOG_GATE1_BASE ) #define REG_ANALOG_GATE2 ((REG_analog_gate2_TypeDef *) REG_ANALOG_GATE2_BASE ) #define REG_ANALOG_GATE3 ((REG_analog_gate3_TypeDef *) REG_ANALOG_GATE3_BASE ) #define REG_ANALOG_GP ((REG_analog_gp_TypeDef *) REG_ANALOG_GP_BASE ) #define REG_ANALOG_IO ((REG_analog_io_TypeDef *) REG_ANALOG_IO_BASE ) #define REG_ANALOG_GP0 ((REG_analog_gp0_TypeDef *) REG_ANALOG_GP0_BASE ) #define REG_ANALOG_GP_TIE ((REG_analog_gp_tie_TypeDef *) REG_ANALOG_GP_TIE_BASE ) #define REG_ANALOG_IO_TIE ((REG_analog_io_tie_TypeDef *) REG_ANALOG_IO_TIE_BASE ) #define REG_ANALOG_MTP ((REG_analog_mtp_TypeDef *) REG_ANALOG_MTP_BASE ) #define REG_ANALOG_VIN ((REG_analog_vin_TypeDef *) REG_ANALOG_VIN_BASE ) #define REG_ANALOG_CSN1 ((REG_analog_csn1_TypeDef *) REG_ANALOG_CSN1_BASE ) #define REG_ANALOG_CSN2 ((REG_analog_csn2_TypeDef *) REG_ANALOG_CSN2_BASE ) #define REG_ANALOG_FB1 ((REG_analog_fb1_TypeDef *) REG_ANALOG_FB1_BASE ) #define REG_ANALOG_FB1_FBCV ((REG_analog_fb1_fbcv_TypeDef *) REG_ANALOG_FB1_FBCV_BASE ) #define REG_ANALOG_FB1_FB ((REG_analog_fb1_fb_TypeDef *) REG_ANALOG_FB1_FB_BASE ) #define REG_ANALOG_FB2 ((REG_analog_fb2_TypeDef *) REG_ANALOG_FB2_BASE ) #define REG_ANALOG_FB2_FBCV ((REG_analog_fb2_fbcv_TypeDef *) REG_ANALOG_FB2_FBCV_BASE ) #define REG_ANALOG_FB2_FB ((REG_analog_fb2_fb_TypeDef *) REG_ANALOG_FB2_FB_BASE ) #define REG_ANALOG_PROT_CHIP ((REG_analog_prot_chip_TypeDef *) REG_ANALOG_PROT_CHIP_BASE ) #define REG_ANALOG_VIN0 ((REG_analog_vin0_TypeDef *) REG_ANALOG_VIN0_BASE ) #define REG_ANALOG_VIN1 ((REG_analog_vin1_TypeDef *) REG_ANALOG_VIN1_BASE ) #define REG_ANALOG_VIN2 ((REG_analog_vin2_TypeDef *) REG_ANALOG_VIN2_BASE ) #define REG_ANALOG_DPDN10 ((REG_analog_dpdn10_TypeDef *) REG_ANALOG_DPDN10_BASE ) #define REG_ANALOG_DPDN20 ((REG_analog_dpdn20_TypeDef *) REG_ANALOG_DPDN20_BASE ) #define REG_ANALOG_PD10 ((REG_analog_pd10_TypeDef *) REG_ANALOG_PD10_BASE ) #define REG_ANALOG_PD20 ((REG_analog_pd20_TypeDef *) REG_ANALOG_PD20_BASE ) #define REG_ANALOG_CS10 ((REG_analog_cs10_TypeDef *) REG_ANALOG_CS10_BASE ) #define REG_ANALOG_CS20 ((REG_analog_cs20_TypeDef *) REG_ANALOG_CS20_BASE ) #define REG_ANALOG_GP_I ((REG_analog_gp_i_TypeDef *) REG_ANALOG_GP_I_BASE ) #define REG_ANALOG_V2 ((REG_analog_v2_TypeDef *) REG_ANALOG_V2_BASE ) #define REG_ANALOG_VBUS10 ((REG_analog_vbus10_TypeDef *) REG_ANALOG_VBUS10_BASE ) #define REG_ANALOG_VBUS20 ((REG_analog_vbus20_TypeDef *) REG_ANALOG_VBUS20_BASE ) #define REG_ANALOG_GATE10 ((REG_analog_gate10_TypeDef *) REG_ANALOG_GATE10_BASE ) #define REG_ANALOG_GATE20 ((REG_analog_gate20_TypeDef *) REG_ANALOG_GATE20_BASE ) #define REG_ANALOG_GATE30 ((REG_analog_gate30_TypeDef *) REG_ANALOG_GATE30_BASE ) #define REG_ANALOG_LPS0 ((REG_analog_lps0_TypeDef *) REG_ANALOG_LPS0_BASE ) #define REG_ANALOG_ADDR4000FB00 ((REG_analog_ADDR4000FB00_TypeDef *) REG_ANALOG_ADDR4000FB00_BASE ) //----------------------------------------------------------------------------- // set #define REG_ANALOG_PROT_OT_TM_POS 0 #define REG_ANALOG_PROT_OT_TM_MSK (0x1ul << REG_ANALOG_PROT_OT_TM_POS) #define REG_ANALOG_PROT_OT_TM_SET(num) (((num) << REG_ANALOG_PROT_OT_TM_POS ) & REG_ANALOG_PROT_OT_TM_MSK) #define REG_ANALOG_PROT_EN_OT_POS 1 #define REG_ANALOG_PROT_EN_OT_MSK (0x1ul << REG_ANALOG_PROT_EN_OT_POS) #define REG_ANALOG_PROT_EN_OT_SET(num) (((num) << REG_ANALOG_PROT_EN_OT_POS ) & REG_ANALOG_PROT_EN_OT_MSK) #define REG_ANALOG_PROT_VIN_OVUV_TEST_OE_POS 2 #define REG_ANALOG_PROT_VIN_OVUV_TEST_OE_MSK (0x1ul << REG_ANALOG_PROT_VIN_OVUV_TEST_OE_POS) #define REG_ANALOG_PROT_VIN_OVUV_TEST_OE_SET(num) (((num) << REG_ANALOG_PROT_VIN_OVUV_TEST_OE_POS ) & REG_ANALOG_PROT_VIN_OVUV_TEST_OE_MSK) #define REG_ANALOG_PROT_EN_VIN_OV_POS 3 #define REG_ANALOG_PROT_EN_VIN_OV_MSK (0x1ul << REG_ANALOG_PROT_EN_VIN_OV_POS) #define REG_ANALOG_PROT_EN_VIN_OV_SET(num) (((num) << REG_ANALOG_PROT_EN_VIN_OV_POS ) & REG_ANALOG_PROT_EN_VIN_OV_MSK) #define REG_ANALOG_PROT_VIN_EN_OVP_POS 4 #define REG_ANALOG_PROT_VIN_EN_OVP_MSK (0x1ul << REG_ANALOG_PROT_VIN_EN_OVP_POS) #define REG_ANALOG_PROT_VIN_EN_OVP_SET(num) (((num) << REG_ANALOG_PROT_VIN_EN_OVP_POS ) & REG_ANALOG_PROT_VIN_EN_OVP_MSK) #define REG_ANALOG_PROT_VIN_EN_RP_OVP_POS 5 #define REG_ANALOG_PROT_VIN_EN_RP_OVP_MSK (0x1ul << REG_ANALOG_PROT_VIN_EN_RP_OVP_POS) #define REG_ANALOG_PROT_VIN_EN_RP_OVP_SET(num) (((num) << REG_ANALOG_PROT_VIN_EN_RP_OVP_POS ) & REG_ANALOG_PROT_VIN_EN_RP_OVP_MSK) #define REG_ANALOG_PROT_VIN_EN_RP_UVP_POS 6 #define REG_ANALOG_PROT_VIN_EN_RP_UVP_MSK (0x1ul << REG_ANALOG_PROT_VIN_EN_RP_UVP_POS) #define REG_ANALOG_PROT_VIN_EN_RP_UVP_SET(num) (((num) << REG_ANALOG_PROT_VIN_EN_RP_UVP_POS ) & REG_ANALOG_PROT_VIN_EN_RP_UVP_MSK) #define REG_ANALOG_PROT_VIN_OV_VTH_POS 7 #define REG_ANALOG_PROT_VIN_OV_VTH_MSK (0x3ul << REG_ANALOG_PROT_VIN_OV_VTH_POS) #define REG_ANALOG_PROT_VIN_OV_VTH_SET(num) (((num) << REG_ANALOG_PROT_VIN_OV_VTH_POS ) & REG_ANALOG_PROT_VIN_OV_VTH_MSK) #define REG_ANALOG_PROT_VIN_UV_VTH_POS 9 #define REG_ANALOG_PROT_VIN_UV_VTH_MSK (0x3ul << REG_ANALOG_PROT_VIN_UV_VTH_POS) #define REG_ANALOG_PROT_VIN_UV_VTH_SET(num) (((num) << REG_ANALOG_PROT_VIN_UV_VTH_POS ) & REG_ANALOG_PROT_VIN_UV_VTH_MSK) #define REG_ANALOG_PROT_VIN1_OVUV_TEST_OE_POS 11 #define REG_ANALOG_PROT_VIN1_OVUV_TEST_OE_MSK (0x1ul << REG_ANALOG_PROT_VIN1_OVUV_TEST_OE_POS) #define REG_ANALOG_PROT_VIN1_OVUV_TEST_OE_SET(num) (((num) << REG_ANALOG_PROT_VIN1_OVUV_TEST_OE_POS ) & REG_ANALOG_PROT_VIN1_OVUV_TEST_OE_MSK) #define REG_ANALOG_PROT_EN_VIN1_OV_POS 12 #define REG_ANALOG_PROT_EN_VIN1_OV_MSK (0x1ul << REG_ANALOG_PROT_EN_VIN1_OV_POS) #define REG_ANALOG_PROT_EN_VIN1_OV_SET(num) (((num) << REG_ANALOG_PROT_EN_VIN1_OV_POS ) & REG_ANALOG_PROT_EN_VIN1_OV_MSK) #define REG_ANALOG_PROT_VIN1_EN_OVP_POS 13 #define REG_ANALOG_PROT_VIN1_EN_OVP_MSK (0x1ul << REG_ANALOG_PROT_VIN1_EN_OVP_POS) #define REG_ANALOG_PROT_VIN1_EN_OVP_SET(num) (((num) << REG_ANALOG_PROT_VIN1_EN_OVP_POS ) & REG_ANALOG_PROT_VIN1_EN_OVP_MSK) #define REG_ANALOG_PROT_VIN1_EN_RP_OVP_POS 14 #define REG_ANALOG_PROT_VIN1_EN_RP_OVP_MSK (0x1ul << REG_ANALOG_PROT_VIN1_EN_RP_OVP_POS) #define REG_ANALOG_PROT_VIN1_EN_RP_OVP_SET(num) (((num) << REG_ANALOG_PROT_VIN1_EN_RP_OVP_POS ) & REG_ANALOG_PROT_VIN1_EN_RP_OVP_MSK) #define REG_ANALOG_PROT_VIN1_EN_RP_UVP_POS 15 #define REG_ANALOG_PROT_VIN1_EN_RP_UVP_MSK (0x1ul << REG_ANALOG_PROT_VIN1_EN_RP_UVP_POS) #define REG_ANALOG_PROT_VIN1_EN_RP_UVP_SET(num) (((num) << REG_ANALOG_PROT_VIN1_EN_RP_UVP_POS ) & REG_ANALOG_PROT_VIN1_EN_RP_UVP_MSK) #define REG_ANALOG_PROT_VIN1_OV_VTH_POS 16 #define REG_ANALOG_PROT_VIN1_OV_VTH_MSK (0x3ul << REG_ANALOG_PROT_VIN1_OV_VTH_POS) #define REG_ANALOG_PROT_VIN1_OV_VTH_SET(num) (((num) << REG_ANALOG_PROT_VIN1_OV_VTH_POS ) & REG_ANALOG_PROT_VIN1_OV_VTH_MSK) #define REG_ANALOG_PROT_VIN1_UV_VTH_POS 18 #define REG_ANALOG_PROT_VIN1_UV_VTH_MSK (0x3ul << REG_ANALOG_PROT_VIN1_UV_VTH_POS) #define REG_ANALOG_PROT_VIN1_UV_VTH_SET(num) (((num) << REG_ANALOG_PROT_VIN1_UV_VTH_POS ) & REG_ANALOG_PROT_VIN1_UV_VTH_MSK) #define REG_ANALOG_PROT_VIN2_OVUV_TEST_OE_POS 20 #define REG_ANALOG_PROT_VIN2_OVUV_TEST_OE_MSK (0x1ul << REG_ANALOG_PROT_VIN2_OVUV_TEST_OE_POS) #define REG_ANALOG_PROT_VIN2_OVUV_TEST_OE_SET(num) (((num) << REG_ANALOG_PROT_VIN2_OVUV_TEST_OE_POS ) & REG_ANALOG_PROT_VIN2_OVUV_TEST_OE_MSK) #define REG_ANALOG_PROT_EN_VIN2_OV_POS 21 #define REG_ANALOG_PROT_EN_VIN2_OV_MSK (0x1ul << REG_ANALOG_PROT_EN_VIN2_OV_POS) #define REG_ANALOG_PROT_EN_VIN2_OV_SET(num) (((num) << REG_ANALOG_PROT_EN_VIN2_OV_POS ) & REG_ANALOG_PROT_EN_VIN2_OV_MSK) #define REG_ANALOG_PROT_VIN2_EN_OVP_POS 22 #define REG_ANALOG_PROT_VIN2_EN_OVP_MSK (0x1ul << REG_ANALOG_PROT_VIN2_EN_OVP_POS) #define REG_ANALOG_PROT_VIN2_EN_OVP_SET(num) (((num) << REG_ANALOG_PROT_VIN2_EN_OVP_POS ) & REG_ANALOG_PROT_VIN2_EN_OVP_MSK) #define REG_ANALOG_PROT_VIN2_EN_RP_OVP_POS 23 #define REG_ANALOG_PROT_VIN2_EN_RP_OVP_MSK (0x1ul << REG_ANALOG_PROT_VIN2_EN_RP_OVP_POS) #define REG_ANALOG_PROT_VIN2_EN_RP_OVP_SET(num) (((num) << REG_ANALOG_PROT_VIN2_EN_RP_OVP_POS ) & REG_ANALOG_PROT_VIN2_EN_RP_OVP_MSK) #define REG_ANALOG_PROT_VIN2_EN_RP_UVP_POS 24 #define REG_ANALOG_PROT_VIN2_EN_RP_UVP_MSK (0x1ul << REG_ANALOG_PROT_VIN2_EN_RP_UVP_POS) #define REG_ANALOG_PROT_VIN2_EN_RP_UVP_SET(num) (((num) << REG_ANALOG_PROT_VIN2_EN_RP_UVP_POS ) & REG_ANALOG_PROT_VIN2_EN_RP_UVP_MSK) #define REG_ANALOG_PROT_VIN2_OV_VTH_POS 25 #define REG_ANALOG_PROT_VIN2_OV_VTH_MSK (0x3ul << REG_ANALOG_PROT_VIN2_OV_VTH_POS) #define REG_ANALOG_PROT_VIN2_OV_VTH_SET(num) (((num) << REG_ANALOG_PROT_VIN2_OV_VTH_POS ) & REG_ANALOG_PROT_VIN2_OV_VTH_MSK) #define REG_ANALOG_PROT_VIN2_UV_VTH_POS 27 #define REG_ANALOG_PROT_VIN2_UV_VTH_MSK (0x3ul << REG_ANALOG_PROT_VIN2_UV_VTH_POS) #define REG_ANALOG_PROT_VIN2_UV_VTH_SET(num) (((num) << REG_ANALOG_PROT_VIN2_UV_VTH_POS ) & REG_ANALOG_PROT_VIN2_UV_VTH_MSK) #define REG_ANALOG_DPDN1_EN_DCP_POS 0 #define REG_ANALOG_DPDN1_EN_DCP_MSK (0x1ul << REG_ANALOG_DPDN1_EN_DCP_POS) #define REG_ANALOG_DPDN1_EN_DCP_SET(num) (((num) << REG_ANALOG_DPDN1_EN_DCP_POS ) & REG_ANALOG_DPDN1_EN_DCP_MSK) #define REG_ANALOG_DPDN1_EN_DN_POS 1 #define REG_ANALOG_DPDN1_EN_DN_MSK (0x1ul << REG_ANALOG_DPDN1_EN_DN_POS) #define REG_ANALOG_DPDN1_EN_DN_SET(num) (((num) << REG_ANALOG_DPDN1_EN_DN_POS ) & REG_ANALOG_DPDN1_EN_DN_MSK) #define REG_ANALOG_DPDN1_EN_DP_POS 2 #define REG_ANALOG_DPDN1_EN_DP_MSK (0x1ul << REG_ANALOG_DPDN1_EN_DP_POS) #define REG_ANALOG_DPDN1_EN_DP_SET(num) (((num) << REG_ANALOG_DPDN1_EN_DP_POS ) & REG_ANALOG_DPDN1_EN_DP_MSK) #define REG_ANALOG_DPDN1_EN_RDN_POS 3 #define REG_ANALOG_DPDN1_EN_RDN_MSK (0x1ul << REG_ANALOG_DPDN1_EN_RDN_POS) #define REG_ANALOG_DPDN1_EN_RDN_SET(num) (((num) << REG_ANALOG_DPDN1_EN_RDN_POS ) & REG_ANALOG_DPDN1_EN_RDN_MSK) #define REG_ANALOG_DPDN1_EN_RDP_POS 4 #define REG_ANALOG_DPDN1_EN_RDP_MSK (0x1ul << REG_ANALOG_DPDN1_EN_RDP_POS) #define REG_ANALOG_DPDN1_EN_RDP_SET(num) (((num) << REG_ANALOG_DPDN1_EN_RDP_POS ) & REG_ANALOG_DPDN1_EN_RDP_MSK) #define REG_ANALOG_DPDN1_MEAS_DN_POS 5 #define REG_ANALOG_DPDN1_MEAS_DN_MSK (0x1ul << REG_ANALOG_DPDN1_MEAS_DN_POS) #define REG_ANALOG_DPDN1_MEAS_DN_SET(num) (((num) << REG_ANALOG_DPDN1_MEAS_DN_POS ) & REG_ANALOG_DPDN1_MEAS_DN_MSK) #define REG_ANALOG_DPDN1_MEAS_DP_POS 6 #define REG_ANALOG_DPDN1_MEAS_DP_MSK (0x1ul << REG_ANALOG_DPDN1_MEAS_DP_POS) #define REG_ANALOG_DPDN1_MEAS_DP_SET(num) (((num) << REG_ANALOG_DPDN1_MEAS_DP_POS ) & REG_ANALOG_DPDN1_MEAS_DP_MSK) #define REG_ANALOG_DPDN1_QC_COMP_DN_EN_POS 7 #define REG_ANALOG_DPDN1_QC_COMP_DN_EN_MSK (0x1ul << REG_ANALOG_DPDN1_QC_COMP_DN_EN_POS) #define REG_ANALOG_DPDN1_QC_COMP_DN_EN_SET(num) (((num) << REG_ANALOG_DPDN1_QC_COMP_DN_EN_POS ) & REG_ANALOG_DPDN1_QC_COMP_DN_EN_MSK) #define REG_ANALOG_DPDN1_QC_COMP_DP_EN_POS 8 #define REG_ANALOG_DPDN1_QC_COMP_DP_EN_MSK (0x1ul << REG_ANALOG_DPDN1_QC_COMP_DP_EN_POS) #define REG_ANALOG_DPDN1_QC_COMP_DP_EN_SET(num) (((num) << REG_ANALOG_DPDN1_QC_COMP_DP_EN_POS ) & REG_ANALOG_DPDN1_QC_COMP_DP_EN_MSK) #define REG_ANALOG_DPDN1_DN_SCAL_EN_POS 9 #define REG_ANALOG_DPDN1_DN_SCAL_EN_MSK (0x1ul << REG_ANALOG_DPDN1_DN_SCAL_EN_POS) #define REG_ANALOG_DPDN1_DN_SCAL_EN_SET(num) (((num) << REG_ANALOG_DPDN1_DN_SCAL_EN_POS ) & REG_ANALOG_DPDN1_DN_SCAL_EN_MSK) #define REG_ANALOG_DPDN1_DP_SCAL_EN_POS 10 #define REG_ANALOG_DPDN1_DP_SCAL_EN_MSK (0x1ul << REG_ANALOG_DPDN1_DP_SCAL_EN_POS) #define REG_ANALOG_DPDN1_DP_SCAL_EN_SET(num) (((num) << REG_ANALOG_DPDN1_DP_SCAL_EN_POS ) & REG_ANALOG_DPDN1_DP_SCAL_EN_MSK) #define REG_ANALOG_DPDN1_REF_DAC_POS 11 #define REG_ANALOG_DPDN1_REF_DAC_MSK (0x3ul << REG_ANALOG_DPDN1_REF_DAC_POS) #define REG_ANALOG_DPDN1_REF_DAC_SET(num) (((num) << REG_ANALOG_DPDN1_REF_DAC_POS ) & REG_ANALOG_DPDN1_REF_DAC_MSK) #define REG_ANALOG_DPDN1_CUR_EN_POS 13 #define REG_ANALOG_DPDN1_CUR_EN_MSK (0x1ul << REG_ANALOG_DPDN1_CUR_EN_POS) #define REG_ANALOG_DPDN1_CUR_EN_SET(num) (((num) << REG_ANALOG_DPDN1_CUR_EN_POS ) & REG_ANALOG_DPDN1_CUR_EN_MSK) #define REG_ANALOG_DPDN1_VTH_SEL_POS 15 #define REG_ANALOG_DPDN1_VTH_SEL_MSK (0x1ul << REG_ANALOG_DPDN1_VTH_SEL_POS) #define REG_ANALOG_DPDN1_VTH_SEL_SET(num) (((num) << REG_ANALOG_DPDN1_VTH_SEL_POS ) & REG_ANALOG_DPDN1_VTH_SEL_MSK) #define REG_ANALOG_DPDN1_DN_RH_EN_POS 16 #define REG_ANALOG_DPDN1_DN_RH_EN_MSK (0x1ul << REG_ANALOG_DPDN1_DN_RH_EN_POS) #define REG_ANALOG_DPDN1_DN_RH_EN_SET(num) (((num) << REG_ANALOG_DPDN1_DN_RH_EN_POS ) & REG_ANALOG_DPDN1_DN_RH_EN_MSK) #define REG_ANALOG_DPDN1_DP_RH_EN_POS 17 #define REG_ANALOG_DPDN1_DP_RH_EN_MSK (0x1ul << REG_ANALOG_DPDN1_DP_RH_EN_POS) #define REG_ANALOG_DPDN1_DP_RH_EN_SET(num) (((num) << REG_ANALOG_DPDN1_DP_RH_EN_POS ) & REG_ANALOG_DPDN1_DP_RH_EN_MSK) #define REG_ANALOG_DPDN1_DN_HVSWITCH_ON_POS 18 #define REG_ANALOG_DPDN1_DN_HVSWITCH_ON_MSK (0x1ul << REG_ANALOG_DPDN1_DN_HVSWITCH_ON_POS) #define REG_ANALOG_DPDN1_DN_HVSWITCH_ON_SET(num) (((num) << REG_ANALOG_DPDN1_DN_HVSWITCH_ON_POS ) & REG_ANALOG_DPDN1_DN_HVSWITCH_ON_MSK) #define REG_ANALOG_DPDN1_DP_HVSWITCH_ON_POS 19 #define REG_ANALOG_DPDN1_DP_HVSWITCH_ON_MSK (0x1ul << REG_ANALOG_DPDN1_DP_HVSWITCH_ON_POS) #define REG_ANALOG_DPDN1_DP_HVSWITCH_ON_SET(num) (((num) << REG_ANALOG_DPDN1_DP_HVSWITCH_ON_POS ) & REG_ANALOG_DPDN1_DP_HVSWITCH_ON_MSK) #define REG_ANALOG_DPDN1_IBIAS_EN_POS 20 #define REG_ANALOG_DPDN1_IBIAS_EN_MSK (0x1ul << REG_ANALOG_DPDN1_IBIAS_EN_POS) #define REG_ANALOG_DPDN1_IBIAS_EN_SET(num) (((num) << REG_ANALOG_DPDN1_IBIAS_EN_POS ) & REG_ANALOG_DPDN1_IBIAS_EN_MSK) #define REG_ANALOG_DPDN1_DP1_SINK_POS 21 #define REG_ANALOG_DPDN1_DP1_SINK_MSK (0x1ul << REG_ANALOG_DPDN1_DP1_SINK_POS) #define REG_ANALOG_DPDN1_DP1_SINK_SET(num) (((num) << REG_ANALOG_DPDN1_DP1_SINK_POS ) & REG_ANALOG_DPDN1_DP1_SINK_MSK) #define REG_ANALOG_DPDN1_CDP_SRC_POS 22 #define REG_ANALOG_DPDN1_CDP_SRC_MSK (0x1ul << REG_ANALOG_DPDN1_CDP_SRC_POS) #define REG_ANALOG_DPDN1_CDP_SRC_SET(num) (((num) << REG_ANALOG_DPDN1_CDP_SRC_POS ) & REG_ANALOG_DPDN1_CDP_SRC_MSK) #define REG_ANALOG_DPDN2_EN_DCP_POS 0 #define REG_ANALOG_DPDN2_EN_DCP_MSK (0x1ul << REG_ANALOG_DPDN2_EN_DCP_POS) #define REG_ANALOG_DPDN2_EN_DCP_SET(num) (((num) << REG_ANALOG_DPDN2_EN_DCP_POS ) & REG_ANALOG_DPDN2_EN_DCP_MSK) #define REG_ANALOG_DPDN2_EN_DN_POS 1 #define REG_ANALOG_DPDN2_EN_DN_MSK (0x1ul << REG_ANALOG_DPDN2_EN_DN_POS) #define REG_ANALOG_DPDN2_EN_DN_SET(num) (((num) << REG_ANALOG_DPDN2_EN_DN_POS ) & REG_ANALOG_DPDN2_EN_DN_MSK) #define REG_ANALOG_DPDN2_EN_DP_POS 2 #define REG_ANALOG_DPDN2_EN_DP_MSK (0x1ul << REG_ANALOG_DPDN2_EN_DP_POS) #define REG_ANALOG_DPDN2_EN_DP_SET(num) (((num) << REG_ANALOG_DPDN2_EN_DP_POS ) & REG_ANALOG_DPDN2_EN_DP_MSK) #define REG_ANALOG_DPDN2_EN_RDN_POS 3 #define REG_ANALOG_DPDN2_EN_RDN_MSK (0x1ul << REG_ANALOG_DPDN2_EN_RDN_POS) #define REG_ANALOG_DPDN2_EN_RDN_SET(num) (((num) << REG_ANALOG_DPDN2_EN_RDN_POS ) & REG_ANALOG_DPDN2_EN_RDN_MSK) #define REG_ANALOG_DPDN2_EN_RDP_POS 4 #define REG_ANALOG_DPDN2_EN_RDP_MSK (0x1ul << REG_ANALOG_DPDN2_EN_RDP_POS) #define REG_ANALOG_DPDN2_EN_RDP_SET(num) (((num) << REG_ANALOG_DPDN2_EN_RDP_POS ) & REG_ANALOG_DPDN2_EN_RDP_MSK) #define REG_ANALOG_DPDN2_MEAS_DN_POS 5 #define REG_ANALOG_DPDN2_MEAS_DN_MSK (0x1ul << REG_ANALOG_DPDN2_MEAS_DN_POS) #define REG_ANALOG_DPDN2_MEAS_DN_SET(num) (((num) << REG_ANALOG_DPDN2_MEAS_DN_POS ) & REG_ANALOG_DPDN2_MEAS_DN_MSK) #define REG_ANALOG_DPDN2_MEAS_DP_POS 6 #define REG_ANALOG_DPDN2_MEAS_DP_MSK (0x1ul << REG_ANALOG_DPDN2_MEAS_DP_POS) #define REG_ANALOG_DPDN2_MEAS_DP_SET(num) (((num) << REG_ANALOG_DPDN2_MEAS_DP_POS ) & REG_ANALOG_DPDN2_MEAS_DP_MSK) #define REG_ANALOG_DPDN2_QC_COMP_DN_EN_POS 7 #define REG_ANALOG_DPDN2_QC_COMP_DN_EN_MSK (0x1ul << REG_ANALOG_DPDN2_QC_COMP_DN_EN_POS) #define REG_ANALOG_DPDN2_QC_COMP_DN_EN_SET(num) (((num) << REG_ANALOG_DPDN2_QC_COMP_DN_EN_POS ) & REG_ANALOG_DPDN2_QC_COMP_DN_EN_MSK) #define REG_ANALOG_DPDN2_QC_COMP_DP_EN_POS 8 #define REG_ANALOG_DPDN2_QC_COMP_DP_EN_MSK (0x1ul << REG_ANALOG_DPDN2_QC_COMP_DP_EN_POS) #define REG_ANALOG_DPDN2_QC_COMP_DP_EN_SET(num) (((num) << REG_ANALOG_DPDN2_QC_COMP_DP_EN_POS ) & REG_ANALOG_DPDN2_QC_COMP_DP_EN_MSK) #define REG_ANALOG_DPDN2_DN_SCAL_EN_POS 9 #define REG_ANALOG_DPDN2_DN_SCAL_EN_MSK (0x1ul << REG_ANALOG_DPDN2_DN_SCAL_EN_POS) #define REG_ANALOG_DPDN2_DN_SCAL_EN_SET(num) (((num) << REG_ANALOG_DPDN2_DN_SCAL_EN_POS ) & REG_ANALOG_DPDN2_DN_SCAL_EN_MSK) #define REG_ANALOG_DPDN2_DP_SCAL_EN_POS 10 #define REG_ANALOG_DPDN2_DP_SCAL_EN_MSK (0x1ul << REG_ANALOG_DPDN2_DP_SCAL_EN_POS) #define REG_ANALOG_DPDN2_DP_SCAL_EN_SET(num) (((num) << REG_ANALOG_DPDN2_DP_SCAL_EN_POS ) & REG_ANALOG_DPDN2_DP_SCAL_EN_MSK) #define REG_ANALOG_DPDN2_REF_DAC_POS 11 #define REG_ANALOG_DPDN2_REF_DAC_MSK (0x3ul << REG_ANALOG_DPDN2_REF_DAC_POS) #define REG_ANALOG_DPDN2_REF_DAC_SET(num) (((num) << REG_ANALOG_DPDN2_REF_DAC_POS ) & REG_ANALOG_DPDN2_REF_DAC_MSK) #define REG_ANALOG_DPDN2_CUR_EN_POS 13 #define REG_ANALOG_DPDN2_CUR_EN_MSK (0x1ul << REG_ANALOG_DPDN2_CUR_EN_POS) #define REG_ANALOG_DPDN2_CUR_EN_SET(num) (((num) << REG_ANALOG_DPDN2_CUR_EN_POS ) & REG_ANALOG_DPDN2_CUR_EN_MSK) #define REG_ANALOG_DPDN2_VTH_SEL_POS 15 #define REG_ANALOG_DPDN2_VTH_SEL_MSK (0x1ul << REG_ANALOG_DPDN2_VTH_SEL_POS) #define REG_ANALOG_DPDN2_VTH_SEL_SET(num) (((num) << REG_ANALOG_DPDN2_VTH_SEL_POS ) & REG_ANALOG_DPDN2_VTH_SEL_MSK) #define REG_ANALOG_DPDN2_DN_RH_EN_POS 16 #define REG_ANALOG_DPDN2_DN_RH_EN_MSK (0x1ul << REG_ANALOG_DPDN2_DN_RH_EN_POS) #define REG_ANALOG_DPDN2_DN_RH_EN_SET(num) (((num) << REG_ANALOG_DPDN2_DN_RH_EN_POS ) & REG_ANALOG_DPDN2_DN_RH_EN_MSK) #define REG_ANALOG_DPDN2_DP_RH_EN_POS 17 #define REG_ANALOG_DPDN2_DP_RH_EN_MSK (0x1ul << REG_ANALOG_DPDN2_DP_RH_EN_POS) #define REG_ANALOG_DPDN2_DP_RH_EN_SET(num) (((num) << REG_ANALOG_DPDN2_DP_RH_EN_POS ) & REG_ANALOG_DPDN2_DP_RH_EN_MSK) #define REG_ANALOG_DPDN2_DP_HVSWITCH_ON_POS 18 #define REG_ANALOG_DPDN2_DP_HVSWITCH_ON_MSK (0x1ul << REG_ANALOG_DPDN2_DP_HVSWITCH_ON_POS) #define REG_ANALOG_DPDN2_DP_HVSWITCH_ON_SET(num) (((num) << REG_ANALOG_DPDN2_DP_HVSWITCH_ON_POS ) & REG_ANALOG_DPDN2_DP_HVSWITCH_ON_MSK) #define REG_ANALOG_DPDN2_DN_HVSWITCH_ON_POS 19 #define REG_ANALOG_DPDN2_DN_HVSWITCH_ON_MSK (0x1ul << REG_ANALOG_DPDN2_DN_HVSWITCH_ON_POS) #define REG_ANALOG_DPDN2_DN_HVSWITCH_ON_SET(num) (((num) << REG_ANALOG_DPDN2_DN_HVSWITCH_ON_POS ) & REG_ANALOG_DPDN2_DN_HVSWITCH_ON_MSK) #define REG_ANALOG_DPDN2_IBIAS_EN_POS 20 #define REG_ANALOG_DPDN2_IBIAS_EN_MSK (0x1ul << REG_ANALOG_DPDN2_IBIAS_EN_POS) #define REG_ANALOG_DPDN2_IBIAS_EN_SET(num) (((num) << REG_ANALOG_DPDN2_IBIAS_EN_POS ) & REG_ANALOG_DPDN2_IBIAS_EN_MSK) #define REG_ANALOG_DPDN2_DP2_SINK_POS 21 #define REG_ANALOG_DPDN2_DP2_SINK_MSK (0x1ul << REG_ANALOG_DPDN2_DP2_SINK_POS) #define REG_ANALOG_DPDN2_DP2_SINK_SET(num) (((num) << REG_ANALOG_DPDN2_DP2_SINK_POS ) & REG_ANALOG_DPDN2_DP2_SINK_MSK) #define REG_ANALOG_DPDN2_CDP_SRC_POS 22 #define REG_ANALOG_DPDN2_CDP_SRC_MSK (0x1ul << REG_ANALOG_DPDN2_CDP_SRC_POS) #define REG_ANALOG_DPDN2_CDP_SRC_SET(num) (((num) << REG_ANALOG_DPDN2_CDP_SRC_POS ) & REG_ANALOG_DPDN2_CDP_SRC_MSK) #define REG_ANALOG_ADC_IB_CMP_SEL_POS 0 #define REG_ANALOG_ADC_IB_CMP_SEL_MSK (0x1ul << REG_ANALOG_ADC_IB_CMP_SEL_POS) #define REG_ANALOG_ADC_IB_CMP_SEL_SET(num) (((num) << REG_ANALOG_ADC_IB_CMP_SEL_POS ) & REG_ANALOG_ADC_IB_CMP_SEL_MSK) #define REG_ANALOG_ADC_IB_VBUF_SEL_POS 1 #define REG_ANALOG_ADC_IB_VBUF_SEL_MSK (0x1ul << REG_ANALOG_ADC_IB_VBUF_SEL_POS) #define REG_ANALOG_ADC_IB_VBUF_SEL_SET(num) (((num) << REG_ANALOG_ADC_IB_VBUF_SEL_POS ) & REG_ANALOG_ADC_IB_VBUF_SEL_MSK) #define REG_ANALOG_OSC_EN_24M_POS 0 #define REG_ANALOG_OSC_EN_24M_MSK (0x1ul << REG_ANALOG_OSC_EN_24M_POS) #define REG_ANALOG_OSC_EN_24M_SET(num) (((num) << REG_ANALOG_OSC_EN_24M_POS ) & REG_ANALOG_OSC_EN_24M_MSK) #define REG_ANALOG_CS1_EN_POS 0 #define REG_ANALOG_CS1_EN_MSK (0x1ul << REG_ANALOG_CS1_EN_POS) #define REG_ANALOG_CS1_EN_SET(num) (((num) << REG_ANALOG_CS1_EN_POS ) & REG_ANALOG_CS1_EN_MSK) #define REG_ANALOG_CS1_VB_EN_POS 1 #define REG_ANALOG_CS1_VB_EN_MSK (0x1ul << REG_ANALOG_CS1_VB_EN_POS) #define REG_ANALOG_CS1_VB_EN_SET(num) (((num) << REG_ANALOG_CS1_VB_EN_POS ) & REG_ANALOG_CS1_VB_EN_MSK) #define REG_ANALOG_CS1_COMP_EN_POS 2 #define REG_ANALOG_CS1_COMP_EN_MSK (0x1ul << REG_ANALOG_CS1_COMP_EN_POS) #define REG_ANALOG_CS1_COMP_EN_SET(num) (((num) << REG_ANALOG_CS1_COMP_EN_POS ) & REG_ANALOG_CS1_COMP_EN_MSK) #define REG_ANALOG_CS1_COMP_REF_SEL_POS 3 #define REG_ANALOG_CS1_COMP_REF_SEL_MSK (0x1ul << REG_ANALOG_CS1_COMP_REF_SEL_POS) #define REG_ANALOG_CS1_COMP_REF_SEL_SET(num) (((num) << REG_ANALOG_CS1_COMP_REF_SEL_POS ) & REG_ANALOG_CS1_COMP_REF_SEL_MSK) #define REG_ANALOG_CS1_RFILTER_SEL_POS 4 #define REG_ANALOG_CS1_RFILTER_SEL_MSK (0x1ul << REG_ANALOG_CS1_RFILTER_SEL_POS) #define REG_ANALOG_CS1_RFILTER_SEL_SET(num) (((num) << REG_ANALOG_CS1_RFILTER_SEL_POS ) & REG_ANALOG_CS1_RFILTER_SEL_MSK) #define REG_ANALOG_CS1_PATH_SEL_POS 5 #define REG_ANALOG_CS1_PATH_SEL_MSK (0x1ul << REG_ANALOG_CS1_PATH_SEL_POS) #define REG_ANALOG_CS1_PATH_SEL_SET(num) (((num) << REG_ANALOG_CS1_PATH_SEL_POS ) & REG_ANALOG_CS1_PATH_SEL_MSK) #define REG_ANALOG_CS1_TRIM_EN_POS 7 #define REG_ANALOG_CS1_TRIM_EN_MSK (0x1ul << REG_ANALOG_CS1_TRIM_EN_POS) #define REG_ANALOG_CS1_TRIM_EN_SET(num) (((num) << REG_ANALOG_CS1_TRIM_EN_POS ) & REG_ANALOG_CS1_TRIM_EN_MSK) #define REG_ANALOG_CS1_TRIM_POS 8 #define REG_ANALOG_CS1_TRIM_MSK (0x1ul << REG_ANALOG_CS1_TRIM_POS) #define REG_ANALOG_CS1_TRIM_SET(num) (((num) << REG_ANALOG_CS1_TRIM_POS ) & REG_ANALOG_CS1_TRIM_MSK) #define REG_ANALOG_CS1_CH_SW_POS 9 #define REG_ANALOG_CS1_CH_SW_MSK (0x1ul << REG_ANALOG_CS1_CH_SW_POS) #define REG_ANALOG_CS1_CH_SW_SET(num) (((num) << REG_ANALOG_CS1_CH_SW_POS ) & REG_ANALOG_CS1_CH_SW_MSK) #define REG_ANALOG_CS2_EN_POS 0 #define REG_ANALOG_CS2_EN_MSK (0x1ul << REG_ANALOG_CS2_EN_POS) #define REG_ANALOG_CS2_EN_SET(num) (((num) << REG_ANALOG_CS2_EN_POS ) & REG_ANALOG_CS2_EN_MSK) #define REG_ANALOG_CS2_VB_EN_POS 1 #define REG_ANALOG_CS2_VB_EN_MSK (0x1ul << REG_ANALOG_CS2_VB_EN_POS) #define REG_ANALOG_CS2_VB_EN_SET(num) (((num) << REG_ANALOG_CS2_VB_EN_POS ) & REG_ANALOG_CS2_VB_EN_MSK) #define REG_ANALOG_CS2_COMP_EN_POS 2 #define REG_ANALOG_CS2_COMP_EN_MSK (0x1ul << REG_ANALOG_CS2_COMP_EN_POS) #define REG_ANALOG_CS2_COMP_EN_SET(num) (((num) << REG_ANALOG_CS2_COMP_EN_POS ) & REG_ANALOG_CS2_COMP_EN_MSK) #define REG_ANALOG_CS2_COMP_REF_SEL_POS 3 #define REG_ANALOG_CS2_COMP_REF_SEL_MSK (0x1ul << REG_ANALOG_CS2_COMP_REF_SEL_POS) #define REG_ANALOG_CS2_COMP_REF_SEL_SET(num) (((num) << REG_ANALOG_CS2_COMP_REF_SEL_POS ) & REG_ANALOG_CS2_COMP_REF_SEL_MSK) #define REG_ANALOG_CS2_RFILTER_SEL_POS 4 #define REG_ANALOG_CS2_RFILTER_SEL_MSK (0x1ul << REG_ANALOG_CS2_RFILTER_SEL_POS) #define REG_ANALOG_CS2_RFILTER_SEL_SET(num) (((num) << REG_ANALOG_CS2_RFILTER_SEL_POS ) & REG_ANALOG_CS2_RFILTER_SEL_MSK) #define REG_ANALOG_CS2_PATH_SEL_POS 5 #define REG_ANALOG_CS2_PATH_SEL_MSK (0x1ul << REG_ANALOG_CS2_PATH_SEL_POS) #define REG_ANALOG_CS2_PATH_SEL_SET(num) (((num) << REG_ANALOG_CS2_PATH_SEL_POS ) & REG_ANALOG_CS2_PATH_SEL_MSK) #define REG_ANALOG_CS2_TRIM_EN_POS 7 #define REG_ANALOG_CS2_TRIM_EN_MSK (0x1ul << REG_ANALOG_CS2_TRIM_EN_POS) #define REG_ANALOG_CS2_TRIM_EN_SET(num) (((num) << REG_ANALOG_CS2_TRIM_EN_POS ) & REG_ANALOG_CS2_TRIM_EN_MSK) #define REG_ANALOG_CS2_TRIM_POS 8 #define REG_ANALOG_CS2_TRIM_MSK (0x1ul << REG_ANALOG_CS2_TRIM_POS) #define REG_ANALOG_CS2_TRIM_SET(num) (((num) << REG_ANALOG_CS2_TRIM_POS ) & REG_ANALOG_CS2_TRIM_MSK) #define REG_ANALOG_CS2_CH_SW_POS 9 #define REG_ANALOG_CS2_CH_SW_MSK (0x1ul << REG_ANALOG_CS2_CH_SW_POS) #define REG_ANALOG_CS2_CH_SW_SET(num) (((num) << REG_ANALOG_CS2_CH_SW_POS ) & REG_ANALOG_CS2_CH_SW_MSK) #define REG_ANALOG_PD1_CCX_H_TH_POS 0 #define REG_ANALOG_PD1_CCX_H_TH_MSK (0x1ul << REG_ANALOG_PD1_CCX_H_TH_POS) #define REG_ANALOG_PD1_CCX_H_TH_SET(num) (((num) << REG_ANALOG_PD1_CCX_H_TH_POS ) & REG_ANALOG_PD1_CCX_H_TH_MSK) #define REG_ANALOG_PD1_CCX_L_TH_POS 2 #define REG_ANALOG_PD1_CCX_L_TH_MSK (0x3ul << REG_ANALOG_PD1_CCX_L_TH_POS) #define REG_ANALOG_PD1_CCX_L_TH_SET(num) (((num) << REG_ANALOG_PD1_CCX_L_TH_POS ) & REG_ANALOG_PD1_CCX_L_TH_MSK) #define REG_ANALOG_PD1_EN_CCX_OVP_POS 5 #define REG_ANALOG_PD1_EN_CCX_OVP_MSK (0x1ul << REG_ANALOG_PD1_EN_CCX_OVP_POS) #define REG_ANALOG_PD1_EN_CCX_OVP_SET(num) (((num) << REG_ANALOG_PD1_EN_CCX_OVP_POS ) & REG_ANALOG_PD1_EN_CCX_OVP_MSK) #define REG_ANALOG_PD1_CC_COMP_BUF_EN_POS 6 #define REG_ANALOG_PD1_CC_COMP_BUF_EN_MSK (0x1ul << REG_ANALOG_PD1_CC_COMP_BUF_EN_POS) #define REG_ANALOG_PD1_CC_COMP_BUF_EN_SET(num) (((num) << REG_ANALOG_PD1_CC_COMP_BUF_EN_POS ) & REG_ANALOG_PD1_CC_COMP_BUF_EN_MSK) #define REG_ANALOG_PD1_DB_IBIAS_EN_POS 11 #define REG_ANALOG_PD1_DB_IBIAS_EN_MSK (0x1ul << REG_ANALOG_PD1_DB_IBIAS_EN_POS) #define REG_ANALOG_PD1_DB_IBIAS_EN_SET(num) (((num) << REG_ANALOG_PD1_DB_IBIAS_EN_POS ) & REG_ANALOG_PD1_DB_IBIAS_EN_MSK) #define REG_ANALOG_PD1_EN_TOP_POS 12 #define REG_ANALOG_PD1_EN_TOP_MSK (0x1ul << REG_ANALOG_PD1_EN_TOP_POS) #define REG_ANALOG_PD1_EN_TOP_SET(num) (((num) << REG_ANALOG_PD1_EN_TOP_POS ) & REG_ANALOG_PD1_EN_TOP_MSK) #define REG_ANALOG_PD1_TX_SLEW_SEL_POS 13 #define REG_ANALOG_PD1_TX_SLEW_SEL_MSK (0x7ul << REG_ANALOG_PD1_TX_SLEW_SEL_POS) #define REG_ANALOG_PD1_TX_SLEW_SEL_SET(num) (((num) << REG_ANALOG_PD1_TX_SLEW_SEL_POS ) & REG_ANALOG_PD1_TX_SLEW_SEL_MSK) #define REG_ANALOG_PD1_ZTX_SEL_POS 16 #define REG_ANALOG_PD1_ZTX_SEL_MSK (0x3Ful << REG_ANALOG_PD1_ZTX_SEL_POS) #define REG_ANALOG_PD1_ZTX_SEL_SET(num) (((num) << REG_ANALOG_PD1_ZTX_SEL_POS ) & REG_ANALOG_PD1_ZTX_SEL_MSK) #define REG_ANALOG_PD1_TEST_BMC_EN_POS 22 #define REG_ANALOG_PD1_TEST_BMC_EN_MSK (0x1ul << REG_ANALOG_PD1_TEST_BMC_EN_POS) #define REG_ANALOG_PD1_TEST_BMC_EN_SET(num) (((num) << REG_ANALOG_PD1_TEST_BMC_EN_POS ) & REG_ANALOG_PD1_TEST_BMC_EN_MSK) #define REG_ANALOG_PD1_TXD_TST_POS 23 #define REG_ANALOG_PD1_TXD_TST_MSK (0x1ul << REG_ANALOG_PD1_TXD_TST_POS) #define REG_ANALOG_PD1_TXD_TST_SET(num) (((num) << REG_ANALOG_PD1_TXD_TST_POS ) & REG_ANALOG_PD1_TXD_TST_MSK) #define REG_ANALOG_PD1_CC1_SCAL_EN_POS 24 #define REG_ANALOG_PD1_CC1_SCAL_EN_MSK (0x1ul << REG_ANALOG_PD1_CC1_SCAL_EN_POS) #define REG_ANALOG_PD1_CC1_SCAL_EN_SET(num) (((num) << REG_ANALOG_PD1_CC1_SCAL_EN_POS ) & REG_ANALOG_PD1_CC1_SCAL_EN_MSK) #define REG_ANALOG_PD1_CC2_SCAL_EN_POS 25 #define REG_ANALOG_PD1_CC2_SCAL_EN_MSK (0x1ul << REG_ANALOG_PD1_CC2_SCAL_EN_POS) #define REG_ANALOG_PD1_CC2_SCAL_EN_SET(num) (((num) << REG_ANALOG_PD1_CC2_SCAL_EN_POS ) & REG_ANALOG_PD1_CC2_SCAL_EN_MSK) #define REG_ANALOG_PD2_CCX_H_TH_POS 0 #define REG_ANALOG_PD2_CCX_H_TH_MSK (0x1ul << REG_ANALOG_PD2_CCX_H_TH_POS) #define REG_ANALOG_PD2_CCX_H_TH_SET(num) (((num) << REG_ANALOG_PD2_CCX_H_TH_POS ) & REG_ANALOG_PD2_CCX_H_TH_MSK) #define REG_ANALOG_PD2_CCX_L_TH_POS 2 #define REG_ANALOG_PD2_CCX_L_TH_MSK (0x3ul << REG_ANALOG_PD2_CCX_L_TH_POS) #define REG_ANALOG_PD2_CCX_L_TH_SET(num) (((num) << REG_ANALOG_PD2_CCX_L_TH_POS ) & REG_ANALOG_PD2_CCX_L_TH_MSK) #define REG_ANALOG_PD2_EN_CCX_OVP_POS 5 #define REG_ANALOG_PD2_EN_CCX_OVP_MSK (0x1ul << REG_ANALOG_PD2_EN_CCX_OVP_POS) #define REG_ANALOG_PD2_EN_CCX_OVP_SET(num) (((num) << REG_ANALOG_PD2_EN_CCX_OVP_POS ) & REG_ANALOG_PD2_EN_CCX_OVP_MSK) #define REG_ANALOG_PD2_CC_COMP_BUF_EN_POS 6 #define REG_ANALOG_PD2_CC_COMP_BUF_EN_MSK (0x1ul << REG_ANALOG_PD2_CC_COMP_BUF_EN_POS) #define REG_ANALOG_PD2_CC_COMP_BUF_EN_SET(num) (((num) << REG_ANALOG_PD2_CC_COMP_BUF_EN_POS ) & REG_ANALOG_PD2_CC_COMP_BUF_EN_MSK) #define REG_ANALOG_PD2_DB_IBIAS_EN_POS 11 #define REG_ANALOG_PD2_DB_IBIAS_EN_MSK (0x1ul << REG_ANALOG_PD2_DB_IBIAS_EN_POS) #define REG_ANALOG_PD2_DB_IBIAS_EN_SET(num) (((num) << REG_ANALOG_PD2_DB_IBIAS_EN_POS ) & REG_ANALOG_PD2_DB_IBIAS_EN_MSK) #define REG_ANALOG_PD2_EN_TOP_POS 12 #define REG_ANALOG_PD2_EN_TOP_MSK (0x1ul << REG_ANALOG_PD2_EN_TOP_POS) #define REG_ANALOG_PD2_EN_TOP_SET(num) (((num) << REG_ANALOG_PD2_EN_TOP_POS ) & REG_ANALOG_PD2_EN_TOP_MSK) #define REG_ANALOG_PD2_TX_SLEW_SEL_POS 13 #define REG_ANALOG_PD2_TX_SLEW_SEL_MSK (0x7ul << REG_ANALOG_PD2_TX_SLEW_SEL_POS) #define REG_ANALOG_PD2_TX_SLEW_SEL_SET(num) (((num) << REG_ANALOG_PD2_TX_SLEW_SEL_POS ) & REG_ANALOG_PD2_TX_SLEW_SEL_MSK) #define REG_ANALOG_PD2_ZTX_SEL_POS 16 #define REG_ANALOG_PD2_ZTX_SEL_MSK (0x3Ful << REG_ANALOG_PD2_ZTX_SEL_POS) #define REG_ANALOG_PD2_ZTX_SEL_SET(num) (((num) << REG_ANALOG_PD2_ZTX_SEL_POS ) & REG_ANALOG_PD2_ZTX_SEL_MSK) #define REG_ANALOG_PD2_TEST_BMC_EN_POS 22 #define REG_ANALOG_PD2_TEST_BMC_EN_MSK (0x1ul << REG_ANALOG_PD2_TEST_BMC_EN_POS) #define REG_ANALOG_PD2_TEST_BMC_EN_SET(num) (((num) << REG_ANALOG_PD2_TEST_BMC_EN_POS ) & REG_ANALOG_PD2_TEST_BMC_EN_MSK) #define REG_ANALOG_PD2_TXD_TST_POS 23 #define REG_ANALOG_PD2_TXD_TST_MSK (0x1ul << REG_ANALOG_PD2_TXD_TST_POS) #define REG_ANALOG_PD2_TXD_TST_SET(num) (((num) << REG_ANALOG_PD2_TXD_TST_POS ) & REG_ANALOG_PD2_TXD_TST_MSK) #define REG_ANALOG_PD2_CC1_SCAL_EN_POS 24 #define REG_ANALOG_PD2_CC1_SCAL_EN_MSK (0x1ul << REG_ANALOG_PD2_CC1_SCAL_EN_POS) #define REG_ANALOG_PD2_CC1_SCAL_EN_SET(num) (((num) << REG_ANALOG_PD2_CC1_SCAL_EN_POS ) & REG_ANALOG_PD2_CC1_SCAL_EN_MSK) #define REG_ANALOG_PD2_CC2_SCAL_EN_POS 25 #define REG_ANALOG_PD2_CC2_SCAL_EN_MSK (0x1ul << REG_ANALOG_PD2_CC2_SCAL_EN_POS) #define REG_ANALOG_PD2_CC2_SCAL_EN_SET(num) (((num) << REG_ANALOG_PD2_CC2_SCAL_EN_POS ) & REG_ANALOG_PD2_CC2_SCAL_EN_MSK) #define REG_ANALOG_CV_LOOP_REF_SW_POS 0 #define REG_ANALOG_CV_LOOP_REF_SW_MSK (0x1ul << REG_ANALOG_CV_LOOP_REF_SW_POS) #define REG_ANALOG_CV_LOOP_REF_SW_SET(num) (((num) << REG_ANALOG_CV_LOOP_REF_SW_POS ) & REG_ANALOG_CV_LOOP_REF_SW_MSK) #define REG_ANALOG_TB_ATB1_SEL_POS 0 #define REG_ANALOG_TB_ATB1_SEL_MSK (0x3Ful << REG_ANALOG_TB_ATB1_SEL_POS) #define REG_ANALOG_TB_ATB1_SEL_SET(num) (((num) << REG_ANALOG_TB_ATB1_SEL_POS ) & REG_ANALOG_TB_ATB1_SEL_MSK) #define REG_ANALOG_TB_BUF_PHASE_SWAP_POS 6 #define REG_ANALOG_TB_BUF_PHASE_SWAP_MSK (0x1ul << REG_ANALOG_TB_BUF_PHASE_SWAP_POS) #define REG_ANALOG_TB_BUF_PHASE_SWAP_SET(num) (((num) << REG_ANALOG_TB_BUF_PHASE_SWAP_POS ) & REG_ANALOG_TB_BUF_PHASE_SWAP_MSK) #define REG_ANALOG_TB_ATB1_UBUF_CH_EN_POS 7 #define REG_ANALOG_TB_ATB1_UBUF_CH_EN_MSK (0x1ul << REG_ANALOG_TB_ATB1_UBUF_CH_EN_POS) #define REG_ANALOG_TB_ATB1_UBUF_CH_EN_SET(num) (((num) << REG_ANALOG_TB_ATB1_UBUF_CH_EN_POS ) & REG_ANALOG_TB_ATB1_UBUF_CH_EN_MSK) #define REG_ANALOG_TB_ATB1_BUF_CH_EN_POS 8 #define REG_ANALOG_TB_ATB1_BUF_CH_EN_MSK (0x1ul << REG_ANALOG_TB_ATB1_BUF_CH_EN_POS) #define REG_ANALOG_TB_ATB1_BUF_CH_EN_SET(num) (((num) << REG_ANALOG_TB_ATB1_BUF_CH_EN_POS ) & REG_ANALOG_TB_ATB1_BUF_CH_EN_MSK) #define REG_ANALOG_TB_ATB2_CH_EN_POS 9 #define REG_ANALOG_TB_ATB2_CH_EN_MSK (0x1ul << REG_ANALOG_TB_ATB2_CH_EN_POS) #define REG_ANALOG_TB_ATB2_CH_EN_SET(num) (((num) << REG_ANALOG_TB_ATB2_CH_EN_POS ) & REG_ANALOG_TB_ATB2_CH_EN_MSK) #define REG_ANALOG_TB_ATB_BUF_EN_POS 10 #define REG_ANALOG_TB_ATB_BUF_EN_MSK (0x1ul << REG_ANALOG_TB_ATB_BUF_EN_POS) #define REG_ANALOG_TB_ATB_BUF_EN_SET(num) (((num) << REG_ANALOG_TB_ATB_BUF_EN_POS ) & REG_ANALOG_TB_ATB_BUF_EN_MSK) #define REG_ANALOG_TB_ATB2_CH_ATB1INT_EN_POS 11 #define REG_ANALOG_TB_ATB2_CH_ATB1INT_EN_MSK (0x1ul << REG_ANALOG_TB_ATB2_CH_ATB1INT_EN_POS) #define REG_ANALOG_TB_ATB2_CH_ATB1INT_EN_SET(num) (((num) << REG_ANALOG_TB_ATB2_CH_ATB1INT_EN_POS ) & REG_ANALOG_TB_ATB2_CH_ATB1INT_EN_MSK) #define REG_ANALOG_TB_ATB2_SEL_POS 16 #define REG_ANALOG_TB_ATB2_SEL_MSK (0xFul << REG_ANALOG_TB_ATB2_SEL_POS) #define REG_ANALOG_TB_ATB2_SEL_SET(num) (((num) << REG_ANALOG_TB_ATB2_SEL_POS ) & REG_ANALOG_TB_ATB2_SEL_MSK) #define REG_ANALOG_DAC_EN_POS 0 #define REG_ANALOG_DAC_EN_MSK (0x1ul << REG_ANALOG_DAC_EN_POS) #define REG_ANALOG_DAC_EN_SET(num) (((num) << REG_ANALOG_DAC_EN_POS ) & REG_ANALOG_DAC_EN_MSK) #define REG_ANALOG_DAC_VOUT_CV_SEL_POS 1 #define REG_ANALOG_DAC_VOUT_CV_SEL_MSK (0x1ul << REG_ANALOG_DAC_VOUT_CV_SEL_POS) #define REG_ANALOG_DAC_VOUT_CV_SEL_SET(num) (((num) << REG_ANALOG_DAC_VOUT_CV_SEL_POS ) & REG_ANALOG_DAC_VOUT_CV_SEL_MSK) #define REG_ANALOG_PUCUR_IO1_POS 0 #define REG_ANALOG_PUCUR_IO1_MSK (0x3ul << REG_ANALOG_PUCUR_IO1_POS) #define REG_ANALOG_PUCUR_IO1_SET(num) (((num) << REG_ANALOG_PUCUR_IO1_POS ) & REG_ANALOG_PUCUR_IO1_MSK) #define REG_ANALOG_PUCUR_IO2_POS 2 #define REG_ANALOG_PUCUR_IO2_MSK (0x3ul << REG_ANALOG_PUCUR_IO2_POS) #define REG_ANALOG_PUCUR_IO2_SET(num) (((num) << REG_ANALOG_PUCUR_IO2_POS ) & REG_ANALOG_PUCUR_IO2_MSK) #define REG_ANALOG_PUCUR_IBIAS3_SEL_POS 4 #define REG_ANALOG_PUCUR_IBIAS3_SEL_MSK (0x1ul << REG_ANALOG_PUCUR_IBIAS3_SEL_POS) #define REG_ANALOG_PUCUR_IBIAS3_SEL_SET(num) (((num) << REG_ANALOG_PUCUR_IBIAS3_SEL_POS ) & REG_ANALOG_PUCUR_IBIAS3_SEL_MSK) #define REG_ANALOG_PUCUR_IBIAS3_POS 5 #define REG_ANALOG_PUCUR_IBIAS3_MSK (0x3ul << REG_ANALOG_PUCUR_IBIAS3_POS) #define REG_ANALOG_PUCUR_IBIAS3_SET(num) (((num) << REG_ANALOG_PUCUR_IBIAS3_POS ) & REG_ANALOG_PUCUR_IBIAS3_MSK) #define REG_ANALOG_PUCUR_IBIAS4_SEL_POS 8 #define REG_ANALOG_PUCUR_IBIAS4_SEL_MSK (0x1ul << REG_ANALOG_PUCUR_IBIAS4_SEL_POS) #define REG_ANALOG_PUCUR_IBIAS4_SEL_SET(num) (((num) << REG_ANALOG_PUCUR_IBIAS4_SEL_POS ) & REG_ANALOG_PUCUR_IBIAS4_SEL_MSK) #define REG_ANALOG_PUCUR_IBIAS4_POS 9 #define REG_ANALOG_PUCUR_IBIAS4_MSK (0x3ul << REG_ANALOG_PUCUR_IBIAS4_POS) #define REG_ANALOG_PUCUR_IBIAS4_SET(num) (((num) << REG_ANALOG_PUCUR_IBIAS4_POS ) & REG_ANALOG_PUCUR_IBIAS4_MSK) #define REG_ANALOG_LDO1P5V_VCONFIG_POS 0 #define REG_ANALOG_LDO1P5V_VCONFIG_MSK (0x3ul << REG_ANALOG_LDO1P5V_VCONFIG_POS) #define REG_ANALOG_LDO1P5V_VCONFIG_SET(num) (((num) << REG_ANALOG_LDO1P5V_VCONFIG_POS ) & REG_ANALOG_LDO1P5V_VCONFIG_MSK) #define REG_ANALOG_VD_ENABLE_POS 0 #define REG_ANALOG_VD_ENABLE_MSK (0x1ul << REG_ANALOG_VD_ENABLE_POS) #define REG_ANALOG_VD_ENABLE_SET(num) (((num) << REG_ANALOG_VD_ENABLE_POS ) & REG_ANALOG_VD_ENABLE_MSK) #define REG_ANALOG_VD_LS_SAMPLE_TST_POS 1 #define REG_ANALOG_VD_LS_SAMPLE_TST_MSK (0x1ul << REG_ANALOG_VD_LS_SAMPLE_TST_POS) #define REG_ANALOG_VD_LS_SAMPLE_TST_SET(num) (((num) << REG_ANALOG_VD_LS_SAMPLE_TST_POS ) & REG_ANALOG_VD_LS_SAMPLE_TST_MSK) #define REG_ANALOG_VD_DIS_MASK_POS 4 #define REG_ANALOG_VD_DIS_MASK_MSK (0x1ul << REG_ANALOG_VD_DIS_MASK_POS) #define REG_ANALOG_VD_DIS_MASK_SET(num) (((num) << REG_ANALOG_VD_DIS_MASK_POS ) & REG_ANALOG_VD_DIS_MASK_MSK) #define REG_ANALOG_VD_MASK_SEL_POS 5 #define REG_ANALOG_VD_MASK_SEL_MSK (0x1ul << REG_ANALOG_VD_MASK_SEL_POS) #define REG_ANALOG_VD_MASK_SEL_SET(num) (((num) << REG_ANALOG_VD_MASK_SEL_POS ) & REG_ANALOG_VD_MASK_SEL_MSK) #define REG_ANALOG_VD_RIS_EDGE_SEL_POS 6 #define REG_ANALOG_VD_RIS_EDGE_SEL_MSK (0x1ul << REG_ANALOG_VD_RIS_EDGE_SEL_POS) #define REG_ANALOG_VD_RIS_EDGE_SEL_SET(num) (((num) << REG_ANALOG_VD_RIS_EDGE_SEL_POS ) & REG_ANALOG_VD_RIS_EDGE_SEL_MSK) #define REG_ANALOG_VD_SCALE_EN_POS 7 #define REG_ANALOG_VD_SCALE_EN_MSK (0x1ul << REG_ANALOG_VD_SCALE_EN_POS) #define REG_ANALOG_VD_SCALE_EN_SET(num) (((num) << REG_ANALOG_VD_SCALE_EN_POS ) & REG_ANALOG_VD_SCALE_EN_MSK) #define REG_ANALOG_VD_LS_RES_EN_POS 8 #define REG_ANALOG_VD_LS_RES_EN_MSK (0x1ul << REG_ANALOG_VD_LS_RES_EN_POS) #define REG_ANALOG_VD_LS_RES_EN_SET(num) (((num) << REG_ANALOG_VD_LS_RES_EN_POS ) & REG_ANALOG_VD_LS_RES_EN_MSK) #define REG_ANALOG_VIN_DIS_EN0_POS 0 #define REG_ANALOG_VIN_DIS_EN0_MSK (0x1ul << REG_ANALOG_VIN_DIS_EN0_POS) #define REG_ANALOG_VIN_DIS_EN0_SET(num) (((num) << REG_ANALOG_VIN_DIS_EN0_POS ) & REG_ANALOG_VIN_DIS_EN0_MSK) #define REG_ANALOG_VIN_DIS_CUR0_POS 1 #define REG_ANALOG_VIN_DIS_CUR0_MSK (0x3ul << REG_ANALOG_VIN_DIS_CUR0_POS) #define REG_ANALOG_VIN_DIS_CUR0_SET(num) (((num) << REG_ANALOG_VIN_DIS_CUR0_POS ) & REG_ANALOG_VIN_DIS_CUR0_MSK) #define REG_ANALOG_VIN_DIS_TM_POS 3 #define REG_ANALOG_VIN_DIS_TM_MSK (0x1ul << REG_ANALOG_VIN_DIS_TM_POS) #define REG_ANALOG_VIN_DIS_TM_SET(num) (((num) << REG_ANALOG_VIN_DIS_TM_POS ) & REG_ANALOG_VIN_DIS_TM_MSK) #define REG_ANALOG_VIN_DIS_EN1_POS 8 #define REG_ANALOG_VIN_DIS_EN1_MSK (0x1ul << REG_ANALOG_VIN_DIS_EN1_POS) #define REG_ANALOG_VIN_DIS_EN1_SET(num) (((num) << REG_ANALOG_VIN_DIS_EN1_POS ) & REG_ANALOG_VIN_DIS_EN1_MSK) #define REG_ANALOG_VIN_DIS_CUR1_POS 9 #define REG_ANALOG_VIN_DIS_CUR1_MSK (0x3ul << REG_ANALOG_VIN_DIS_CUR1_POS) #define REG_ANALOG_VIN_DIS_CUR1_SET(num) (((num) << REG_ANALOG_VIN_DIS_CUR1_POS ) & REG_ANALOG_VIN_DIS_CUR1_MSK) #define REG_ANALOG_VIN_DIS_EN2_POS 16 #define REG_ANALOG_VIN_DIS_EN2_MSK (0x1ul << REG_ANALOG_VIN_DIS_EN2_POS) #define REG_ANALOG_VIN_DIS_EN2_SET(num) (((num) << REG_ANALOG_VIN_DIS_EN2_POS ) & REG_ANALOG_VIN_DIS_EN2_MSK) #define REG_ANALOG_VIN_DIS_CUR2_POS 17 #define REG_ANALOG_VIN_DIS_CUR2_MSK (0x3ul << REG_ANALOG_VIN_DIS_CUR2_POS) #define REG_ANALOG_VIN_DIS_CUR2_SET(num) (((num) << REG_ANALOG_VIN_DIS_CUR2_POS ) & REG_ANALOG_VIN_DIS_CUR2_MSK) #define REG_ANALOG_VBUS1_DIS_EN_POS 0 #define REG_ANALOG_VBUS1_DIS_EN_MSK (0x1ul << REG_ANALOG_VBUS1_DIS_EN_POS) #define REG_ANALOG_VBUS1_DIS_EN_SET(num) (((num) << REG_ANALOG_VBUS1_DIS_EN_POS ) & REG_ANALOG_VBUS1_DIS_EN_MSK) #define REG_ANALOG_VBUS1_DIS_EN_TST_POS 1 #define REG_ANALOG_VBUS1_DIS_EN_TST_MSK (0x1ul << REG_ANALOG_VBUS1_DIS_EN_TST_POS) #define REG_ANALOG_VBUS1_DIS_EN_TST_SET(num) (((num) << REG_ANALOG_VBUS1_DIS_EN_TST_POS ) & REG_ANALOG_VBUS1_DIS_EN_TST_MSK) #define REG_ANALOG_VBUS1_OC_SEL_POS 2 #define REG_ANALOG_VBUS1_OC_SEL_MSK (0x1ul << REG_ANALOG_VBUS1_OC_SEL_POS) #define REG_ANALOG_VBUS1_OC_SEL_SET(num) (((num) << REG_ANALOG_VBUS1_OC_SEL_POS ) & REG_ANALOG_VBUS1_OC_SEL_MSK) #define REG_ANALOG_VBUS1_OC_EN_POS 3 #define REG_ANALOG_VBUS1_OC_EN_MSK (0x1ul << REG_ANALOG_VBUS1_OC_EN_POS) #define REG_ANALOG_VBUS1_OC_EN_SET(num) (((num) << REG_ANALOG_VBUS1_OC_EN_POS ) & REG_ANALOG_VBUS1_OC_EN_MSK) #define REG_ANALOG_VBUS2_DIS_EN_POS 0 #define REG_ANALOG_VBUS2_DIS_EN_MSK (0x1ul << REG_ANALOG_VBUS2_DIS_EN_POS) #define REG_ANALOG_VBUS2_DIS_EN_SET(num) (((num) << REG_ANALOG_VBUS2_DIS_EN_POS ) & REG_ANALOG_VBUS2_DIS_EN_MSK) #define REG_ANALOG_VBUS2_DIS_EN_TST_POS 1 #define REG_ANALOG_VBUS2_DIS_EN_TST_MSK (0x1ul << REG_ANALOG_VBUS2_DIS_EN_TST_POS) #define REG_ANALOG_VBUS2_DIS_EN_TST_SET(num) (((num) << REG_ANALOG_VBUS2_DIS_EN_TST_POS ) & REG_ANALOG_VBUS2_DIS_EN_TST_MSK) #define REG_ANALOG_VBUS2_OC_SEL_POS 2 #define REG_ANALOG_VBUS2_OC_SEL_MSK (0x1ul << REG_ANALOG_VBUS2_OC_SEL_POS) #define REG_ANALOG_VBUS2_OC_SEL_SET(num) (((num) << REG_ANALOG_VBUS2_OC_SEL_POS ) & REG_ANALOG_VBUS2_OC_SEL_MSK) #define REG_ANALOG_VBUS2_OC_EN_POS 3 #define REG_ANALOG_VBUS2_OC_EN_MSK (0x1ul << REG_ANALOG_VBUS2_OC_EN_POS) #define REG_ANALOG_VBUS2_OC_EN_SET(num) (((num) << REG_ANALOG_VBUS2_OC_EN_POS ) & REG_ANALOG_VBUS2_OC_EN_MSK) #define REG_ANALOG_CC_LOOP_EN_POS 0 #define REG_ANALOG_CC_LOOP_EN_MSK (0x1ul << REG_ANALOG_CC_LOOP_EN_POS) #define REG_ANALOG_CC_LOOP_EN_SET(num) (((num) << REG_ANALOG_CC_LOOP_EN_POS ) & REG_ANALOG_CC_LOOP_EN_MSK) #define REG_ANALOG_CV_LOOP_EN_POS 0 #define REG_ANALOG_CV_LOOP_EN_MSK (0x1ul << REG_ANALOG_CV_LOOP_EN_POS) #define REG_ANALOG_CV_LOOP_EN_SET(num) (((num) << REG_ANALOG_CV_LOOP_EN_POS ) & REG_ANALOG_CV_LOOP_EN_MSK) #define REG_ANALOG_OPTO_LEAK_TEST_POS 0 #define REG_ANALOG_OPTO_LEAK_TEST_MSK (0x1ul << REG_ANALOG_OPTO_LEAK_TEST_POS) #define REG_ANALOG_OPTO_LEAK_TEST_SET(num) (((num) << REG_ANALOG_OPTO_LEAK_TEST_POS ) & REG_ANALOG_OPTO_LEAK_TEST_MSK) #define REG_ANALOG_OPTO_MODE_POS 1 #define REG_ANALOG_OPTO_MODE_MSK (0x1ul << REG_ANALOG_OPTO_MODE_POS) #define REG_ANALOG_OPTO_MODE_SET(num) (((num) << REG_ANALOG_OPTO_MODE_POS ) & REG_ANALOG_OPTO_MODE_MSK) #define REG_ANALOG_OPTO_HI_POS 2 #define REG_ANALOG_OPTO_HI_MSK (0x1ul << REG_ANALOG_OPTO_HI_POS) #define REG_ANALOG_OPTO_HI_SET(num) (((num) << REG_ANALOG_OPTO_HI_POS ) & REG_ANALOG_OPTO_HI_MSK) #define REG_ANALOG_OPTO_LOW_POS 3 #define REG_ANALOG_OPTO_LOW_MSK (0x1ul << REG_ANALOG_OPTO_LOW_POS) #define REG_ANALOG_OPTO_LOW_SET(num) (((num) << REG_ANALOG_OPTO_LOW_POS ) & REG_ANALOG_OPTO_LOW_MSK) #define REG_ANALOG_DEBUG_EN_B_POS 0 #define REG_ANALOG_DEBUG_EN_B_MSK (0x1ul << REG_ANALOG_DEBUG_EN_B_POS) #define REG_ANALOG_DEBUG_EN_B_SET(num) (((num) << REG_ANALOG_DEBUG_EN_B_POS ) & REG_ANALOG_DEBUG_EN_B_MSK) #define REG_ANALOG_ANA_CTRL_SPARE_POS 0 #define REG_ANALOG_ANA_CTRL_SPARE_MSK (0xFFul << REG_ANALOG_ANA_CTRL_SPARE_POS) #define REG_ANALOG_ANA_CTRL_SPARE_SET(num) (((num) << REG_ANALOG_ANA_CTRL_SPARE_POS ) & REG_ANALOG_ANA_CTRL_SPARE_MSK) #define REG_ANALOG_I2C_IO_SEL_SCL1_POS 0 #define REG_ANALOG_I2C_IO_SEL_SCL1_MSK (0x3ul << REG_ANALOG_I2C_IO_SEL_SCL1_POS) #define REG_ANALOG_I2C_IO_SEL_SCL1_SET(num) (((num) << REG_ANALOG_I2C_IO_SEL_SCL1_POS ) & REG_ANALOG_I2C_IO_SEL_SCL1_MSK) #define REG_ANALOG_I2C_IO_SEL_SDA1_POS 4 #define REG_ANALOG_I2C_IO_SEL_SDA1_MSK (0x3ul << REG_ANALOG_I2C_IO_SEL_SDA1_POS) #define REG_ANALOG_I2C_IO_SEL_SDA1_SET(num) (((num) << REG_ANALOG_I2C_IO_SEL_SDA1_POS ) & REG_ANALOG_I2C_IO_SEL_SDA1_MSK) #define REG_ANALOG_I2C_IO_SEL_SCL2_POS 8 #define REG_ANALOG_I2C_IO_SEL_SCL2_MSK (0x3ul << REG_ANALOG_I2C_IO_SEL_SCL2_POS) #define REG_ANALOG_I2C_IO_SEL_SCL2_SET(num) (((num) << REG_ANALOG_I2C_IO_SEL_SCL2_POS ) & REG_ANALOG_I2C_IO_SEL_SCL2_MSK) #define REG_ANALOG_I2C_IO_SEL_SDA2_POS 12 #define REG_ANALOG_I2C_IO_SEL_SDA2_MSK (0x3ul << REG_ANALOG_I2C_IO_SEL_SDA2_POS) #define REG_ANALOG_I2C_IO_SEL_SDA2_SET(num) (((num) << REG_ANALOG_I2C_IO_SEL_SDA2_POS ) & REG_ANALOG_I2C_IO_SEL_SDA2_MSK) #define REG_ANALOG_I2C_VSET1_POS 16 #define REG_ANALOG_I2C_VSET1_MSK (0x3ul << REG_ANALOG_I2C_VSET1_POS) #define REG_ANALOG_I2C_VSET1_SET(num) (((num) << REG_ANALOG_I2C_VSET1_POS ) & REG_ANALOG_I2C_VSET1_MSK) #define REG_ANALOG_I2C_RH1_POS 18 #define REG_ANALOG_I2C_RH1_MSK (0x1ul << REG_ANALOG_I2C_RH1_POS) #define REG_ANALOG_I2C_RH1_SET(num) (((num) << REG_ANALOG_I2C_RH1_POS ) & REG_ANALOG_I2C_RH1_MSK) #define REG_ANALOG_I2C_VSET2_POS 24 #define REG_ANALOG_I2C_VSET2_MSK (0x3ul << REG_ANALOG_I2C_VSET2_POS) #define REG_ANALOG_I2C_VSET2_SET(num) (((num) << REG_ANALOG_I2C_VSET2_POS ) & REG_ANALOG_I2C_VSET2_MSK) #define REG_ANALOG_I2C_RH2_POS 26 #define REG_ANALOG_I2C_RH2_MSK (0x1ul << REG_ANALOG_I2C_RH2_POS) #define REG_ANALOG_I2C_RH2_SET(num) (((num) << REG_ANALOG_I2C_RH2_POS ) & REG_ANALOG_I2C_RH2_MSK) #define REG_ANALOG_PD1_RX_GAIN_SEL_POS 0 #define REG_ANALOG_PD1_RX_GAIN_SEL_MSK (0x3ul << REG_ANALOG_PD1_RX_GAIN_SEL_POS) #define REG_ANALOG_PD1_RX_GAIN_SEL_SET(num) (((num) << REG_ANALOG_PD1_RX_GAIN_SEL_POS ) & REG_ANALOG_PD1_RX_GAIN_SEL_MSK) #define REG_ANALOG_PD1_RX_HYS_SEL_POS 2 #define REG_ANALOG_PD1_RX_HYS_SEL_MSK (0x3ul << REG_ANALOG_PD1_RX_HYS_SEL_POS) #define REG_ANALOG_PD1_RX_HYS_SEL_SET(num) (((num) << REG_ANALOG_PD1_RX_HYS_SEL_POS ) & REG_ANALOG_PD1_RX_HYS_SEL_MSK) #define REG_ANALOG_PD1_RX_TEST_EN_POS 4 #define REG_ANALOG_PD1_RX_TEST_EN_MSK (0x1ul << REG_ANALOG_PD1_RX_TEST_EN_POS) #define REG_ANALOG_PD1_RX_TEST_EN_SET(num) (((num) << REG_ANALOG_PD1_RX_TEST_EN_POS ) & REG_ANALOG_PD1_RX_TEST_EN_MSK) #define REG_ANALOG_PD1_RX_VBIAS_EN_POS 5 #define REG_ANALOG_PD1_RX_VBIAS_EN_MSK (0x1ul << REG_ANALOG_PD1_RX_VBIAS_EN_POS) #define REG_ANALOG_PD1_RX_VBIAS_EN_SET(num) (((num) << REG_ANALOG_PD1_RX_VBIAS_EN_POS ) & REG_ANALOG_PD1_RX_VBIAS_EN_MSK) #define REG_ANALOG_PD2_RX_GAIN_SEL_POS 0 #define REG_ANALOG_PD2_RX_GAIN_SEL_MSK (0x3ul << REG_ANALOG_PD2_RX_GAIN_SEL_POS) #define REG_ANALOG_PD2_RX_GAIN_SEL_SET(num) (((num) << REG_ANALOG_PD2_RX_GAIN_SEL_POS ) & REG_ANALOG_PD2_RX_GAIN_SEL_MSK) #define REG_ANALOG_PD2_RX_HYS_SEL_POS 2 #define REG_ANALOG_PD2_RX_HYS_SEL_MSK (0x3ul << REG_ANALOG_PD2_RX_HYS_SEL_POS) #define REG_ANALOG_PD2_RX_HYS_SEL_SET(num) (((num) << REG_ANALOG_PD2_RX_HYS_SEL_POS ) & REG_ANALOG_PD2_RX_HYS_SEL_MSK) #define REG_ANALOG_PD2_RX_TEST_EN_POS 4 #define REG_ANALOG_PD2_RX_TEST_EN_MSK (0x1ul << REG_ANALOG_PD2_RX_TEST_EN_POS) #define REG_ANALOG_PD2_RX_TEST_EN_SET(num) (((num) << REG_ANALOG_PD2_RX_TEST_EN_POS ) & REG_ANALOG_PD2_RX_TEST_EN_MSK) #define REG_ANALOG_PD2_RX_VBIAS_EN_POS 5 #define REG_ANALOG_PD2_RX_VBIAS_EN_MSK (0x1ul << REG_ANALOG_PD2_RX_VBIAS_EN_POS) #define REG_ANALOG_PD2_RX_VBIAS_EN_SET(num) (((num) << REG_ANALOG_PD2_RX_VBIAS_EN_POS ) & REG_ANALOG_PD2_RX_VBIAS_EN_MSK) #define REG_ANALOG_LPS_VDS1_EN_POS 0 #define REG_ANALOG_LPS_VDS1_EN_MSK (0x1ul << REG_ANALOG_LPS_VDS1_EN_POS) #define REG_ANALOG_LPS_VDS1_EN_SET(num) (((num) << REG_ANALOG_LPS_VDS1_EN_POS ) & REG_ANALOG_LPS_VDS1_EN_MSK) #define REG_ANALOG_LPS_VDS1_SEL_POS 1 #define REG_ANALOG_LPS_VDS1_SEL_MSK (0x3ul << REG_ANALOG_LPS_VDS1_SEL_POS) #define REG_ANALOG_LPS_VDS1_SEL_SET(num) (((num) << REG_ANALOG_LPS_VDS1_SEL_POS ) & REG_ANALOG_LPS_VDS1_SEL_MSK) #define REG_ANALOG_LPS_VDS2_EN_POS 3 #define REG_ANALOG_LPS_VDS2_EN_MSK (0x1ul << REG_ANALOG_LPS_VDS2_EN_POS) #define REG_ANALOG_LPS_VDS2_EN_SET(num) (((num) << REG_ANALOG_LPS_VDS2_EN_POS ) & REG_ANALOG_LPS_VDS2_EN_MSK) #define REG_ANALOG_LPS_VDS2_SEL_POS 4 #define REG_ANALOG_LPS_VDS2_SEL_MSK (0x3ul << REG_ANALOG_LPS_VDS2_SEL_POS) #define REG_ANALOG_LPS_VDS2_SEL_SET(num) (((num) << REG_ANALOG_LPS_VDS2_SEL_POS ) & REG_ANALOG_LPS_VDS2_SEL_MSK) #define REG_ANALOG_GATE1_CP_EN_POS 0 #define REG_ANALOG_GATE1_CP_EN_MSK (0x1ul << REG_ANALOG_GATE1_CP_EN_POS) #define REG_ANALOG_GATE1_CP_EN_SET(num) (((num) << REG_ANALOG_GATE1_CP_EN_POS ) & REG_ANALOG_GATE1_CP_EN_MSK) #define REG_ANALOG_GATE1_ON_SEL_POS 1 #define REG_ANALOG_GATE1_ON_SEL_MSK (0x3ul << REG_ANALOG_GATE1_ON_SEL_POS) #define REG_ANALOG_GATE1_ON_SEL_SET(num) (((num) << REG_ANALOG_GATE1_ON_SEL_POS ) & REG_ANALOG_GATE1_ON_SEL_MSK) #define REG_ANALOG_GATE1_DRIVER_EN_POS 4 #define REG_ANALOG_GATE1_DRIVER_EN_MSK (0x1ul << REG_ANALOG_GATE1_DRIVER_EN_POS) #define REG_ANALOG_GATE1_DRIVER_EN_SET(num) (((num) << REG_ANALOG_GATE1_DRIVER_EN_POS ) & REG_ANALOG_GATE1_DRIVER_EN_MSK) #define REG_ANALOG_GATE1_PULL_LOW_POS 5 #define REG_ANALOG_GATE1_PULL_LOW_MSK (0x1ul << REG_ANALOG_GATE1_PULL_LOW_POS) #define REG_ANALOG_GATE1_PULL_LOW_SET(num) (((num) << REG_ANALOG_GATE1_PULL_LOW_POS ) & REG_ANALOG_GATE1_PULL_LOW_MSK) #define REG_ANALOG_GATE1_RESLOAD_POS 6 #define REG_ANALOG_GATE1_RESLOAD_MSK (0x1ul << REG_ANALOG_GATE1_RESLOAD_POS) #define REG_ANALOG_GATE1_RESLOAD_SET(num) (((num) << REG_ANALOG_GATE1_RESLOAD_POS ) & REG_ANALOG_GATE1_RESLOAD_MSK) #define REG_ANALOG_GATE1_UVP_EN_POS 7 #define REG_ANALOG_GATE1_UVP_EN_MSK (0x1ul << REG_ANALOG_GATE1_UVP_EN_POS) #define REG_ANALOG_GATE1_UVP_EN_SET(num) (((num) << REG_ANALOG_GATE1_UVP_EN_POS ) & REG_ANALOG_GATE1_UVP_EN_MSK) #define REG_ANALOG_GATE1_FAST_ON_POS 8 #define REG_ANALOG_GATE1_FAST_ON_MSK (0x1ul << REG_ANALOG_GATE1_FAST_ON_POS) #define REG_ANALOG_GATE1_FAST_ON_SET(num) (((num) << REG_ANALOG_GATE1_FAST_ON_POS ) & REG_ANALOG_GATE1_FAST_ON_MSK) #define REG_ANALOG_GATE1_HZ_POS 9 #define REG_ANALOG_GATE1_HZ_MSK (0x1ul << REG_ANALOG_GATE1_HZ_POS) #define REG_ANALOG_GATE1_HZ_SET(num) (((num) << REG_ANALOG_GATE1_HZ_POS ) & REG_ANALOG_GATE1_HZ_MSK) #define REG_ANALOG_GATE1_ILIM_POS 10 #define REG_ANALOG_GATE1_ILIM_MSK (0x1ul << REG_ANALOG_GATE1_ILIM_POS) #define REG_ANALOG_GATE1_ILIM_SET(num) (((num) << REG_ANALOG_GATE1_ILIM_POS ) & REG_ANALOG_GATE1_ILIM_MSK) #define REG_ANALOG_GATE1_DIS_ILIM_POS 11 #define REG_ANALOG_GATE1_DIS_ILIM_MSK (0x1ul << REG_ANALOG_GATE1_DIS_ILIM_POS) #define REG_ANALOG_GATE1_DIS_ILIM_SET(num) (((num) << REG_ANALOG_GATE1_DIS_ILIM_POS ) & REG_ANALOG_GATE1_DIS_ILIM_MSK) #define REG_ANALOG_GATE1_VOLTAGE_SEL_POS 12 #define REG_ANALOG_GATE1_VOLTAGE_SEL_MSK (0x7ul << REG_ANALOG_GATE1_VOLTAGE_SEL_POS) #define REG_ANALOG_GATE1_VOLTAGE_SEL_SET(num) (((num) << REG_ANALOG_GATE1_VOLTAGE_SEL_POS ) & REG_ANALOG_GATE1_VOLTAGE_SEL_MSK) #define REG_ANALOG_GATE2_CP_EN_POS 0 #define REG_ANALOG_GATE2_CP_EN_MSK (0x1ul << REG_ANALOG_GATE2_CP_EN_POS) #define REG_ANALOG_GATE2_CP_EN_SET(num) (((num) << REG_ANALOG_GATE2_CP_EN_POS ) & REG_ANALOG_GATE2_CP_EN_MSK) #define REG_ANALOG_GATE2_ON_SEL_POS 1 #define REG_ANALOG_GATE2_ON_SEL_MSK (0x3ul << REG_ANALOG_GATE2_ON_SEL_POS) #define REG_ANALOG_GATE2_ON_SEL_SET(num) (((num) << REG_ANALOG_GATE2_ON_SEL_POS ) & REG_ANALOG_GATE2_ON_SEL_MSK) #define REG_ANALOG_GATE2_DRIVER_EN_POS 4 #define REG_ANALOG_GATE2_DRIVER_EN_MSK (0x1ul << REG_ANALOG_GATE2_DRIVER_EN_POS) #define REG_ANALOG_GATE2_DRIVER_EN_SET(num) (((num) << REG_ANALOG_GATE2_DRIVER_EN_POS ) & REG_ANALOG_GATE2_DRIVER_EN_MSK) #define REG_ANALOG_GATE2_PULL_LOW_POS 5 #define REG_ANALOG_GATE2_PULL_LOW_MSK (0x1ul << REG_ANALOG_GATE2_PULL_LOW_POS) #define REG_ANALOG_GATE2_PULL_LOW_SET(num) (((num) << REG_ANALOG_GATE2_PULL_LOW_POS ) & REG_ANALOG_GATE2_PULL_LOW_MSK) #define REG_ANALOG_GATE2_RESLOAD_POS 6 #define REG_ANALOG_GATE2_RESLOAD_MSK (0x1ul << REG_ANALOG_GATE2_RESLOAD_POS) #define REG_ANALOG_GATE2_RESLOAD_SET(num) (((num) << REG_ANALOG_GATE2_RESLOAD_POS ) & REG_ANALOG_GATE2_RESLOAD_MSK) #define REG_ANALOG_GATE2_UVP_EN_POS 7 #define REG_ANALOG_GATE2_UVP_EN_MSK (0x1ul << REG_ANALOG_GATE2_UVP_EN_POS) #define REG_ANALOG_GATE2_UVP_EN_SET(num) (((num) << REG_ANALOG_GATE2_UVP_EN_POS ) & REG_ANALOG_GATE2_UVP_EN_MSK) #define REG_ANALOG_GATE2_FAST_ON_POS 8 #define REG_ANALOG_GATE2_FAST_ON_MSK (0x1ul << REG_ANALOG_GATE2_FAST_ON_POS) #define REG_ANALOG_GATE2_FAST_ON_SET(num) (((num) << REG_ANALOG_GATE2_FAST_ON_POS ) & REG_ANALOG_GATE2_FAST_ON_MSK) #define REG_ANALOG_GATE2_HZ_POS 9 #define REG_ANALOG_GATE2_HZ_MSK (0x1ul << REG_ANALOG_GATE2_HZ_POS) #define REG_ANALOG_GATE2_HZ_SET(num) (((num) << REG_ANALOG_GATE2_HZ_POS ) & REG_ANALOG_GATE2_HZ_MSK) #define REG_ANALOG_GATE2_ILIM_POS 10 #define REG_ANALOG_GATE2_ILIM_MSK (0x1ul << REG_ANALOG_GATE2_ILIM_POS) #define REG_ANALOG_GATE2_ILIM_SET(num) (((num) << REG_ANALOG_GATE2_ILIM_POS ) & REG_ANALOG_GATE2_ILIM_MSK) #define REG_ANALOG_GATE2_DIS_ILIM_POS 11 #define REG_ANALOG_GATE2_DIS_ILIM_MSK (0x1ul << REG_ANALOG_GATE2_DIS_ILIM_POS) #define REG_ANALOG_GATE2_DIS_ILIM_SET(num) (((num) << REG_ANALOG_GATE2_DIS_ILIM_POS ) & REG_ANALOG_GATE2_DIS_ILIM_MSK) #define REG_ANALOG_GATE2_VOLTAGE_SEL_POS 12 #define REG_ANALOG_GATE2_VOLTAGE_SEL_MSK (0x7ul << REG_ANALOG_GATE2_VOLTAGE_SEL_POS) #define REG_ANALOG_GATE2_VOLTAGE_SEL_SET(num) (((num) << REG_ANALOG_GATE2_VOLTAGE_SEL_POS ) & REG_ANALOG_GATE2_VOLTAGE_SEL_MSK) #define REG_ANALOG_GATE3_CP_EN_POS 0 #define REG_ANALOG_GATE3_CP_EN_MSK (0x1ul << REG_ANALOG_GATE3_CP_EN_POS) #define REG_ANALOG_GATE3_CP_EN_SET(num) (((num) << REG_ANALOG_GATE3_CP_EN_POS ) & REG_ANALOG_GATE3_CP_EN_MSK) #define REG_ANALOG_GATE3_ON_SEL_POS 1 #define REG_ANALOG_GATE3_ON_SEL_MSK (0x3ul << REG_ANALOG_GATE3_ON_SEL_POS) #define REG_ANALOG_GATE3_ON_SEL_SET(num) (((num) << REG_ANALOG_GATE3_ON_SEL_POS ) & REG_ANALOG_GATE3_ON_SEL_MSK) #define REG_ANALOG_GATE3_DRIVER_EN_POS 4 #define REG_ANALOG_GATE3_DRIVER_EN_MSK (0x1ul << REG_ANALOG_GATE3_DRIVER_EN_POS) #define REG_ANALOG_GATE3_DRIVER_EN_SET(num) (((num) << REG_ANALOG_GATE3_DRIVER_EN_POS ) & REG_ANALOG_GATE3_DRIVER_EN_MSK) #define REG_ANALOG_GATE3_PULL_LOW_POS 5 #define REG_ANALOG_GATE3_PULL_LOW_MSK (0x1ul << REG_ANALOG_GATE3_PULL_LOW_POS) #define REG_ANALOG_GATE3_PULL_LOW_SET(num) (((num) << REG_ANALOG_GATE3_PULL_LOW_POS ) & REG_ANALOG_GATE3_PULL_LOW_MSK) #define REG_ANALOG_GATE3_RESLOAD_POS 6 #define REG_ANALOG_GATE3_RESLOAD_MSK (0x1ul << REG_ANALOG_GATE3_RESLOAD_POS) #define REG_ANALOG_GATE3_RESLOAD_SET(num) (((num) << REG_ANALOG_GATE3_RESLOAD_POS ) & REG_ANALOG_GATE3_RESLOAD_MSK) #define REG_ANALOG_GATE3_UVP_EN_POS 7 #define REG_ANALOG_GATE3_UVP_EN_MSK (0x1ul << REG_ANALOG_GATE3_UVP_EN_POS) #define REG_ANALOG_GATE3_UVP_EN_SET(num) (((num) << REG_ANALOG_GATE3_UVP_EN_POS ) & REG_ANALOG_GATE3_UVP_EN_MSK) #define REG_ANALOG_GATE3_FAST_ON_POS 8 #define REG_ANALOG_GATE3_FAST_ON_MSK (0x1ul << REG_ANALOG_GATE3_FAST_ON_POS) #define REG_ANALOG_GATE3_FAST_ON_SET(num) (((num) << REG_ANALOG_GATE3_FAST_ON_POS ) & REG_ANALOG_GATE3_FAST_ON_MSK) #define REG_ANALOG_GATE3_HZ_POS 9 #define REG_ANALOG_GATE3_HZ_MSK (0x1ul << REG_ANALOG_GATE3_HZ_POS) #define REG_ANALOG_GATE3_HZ_SET(num) (((num) << REG_ANALOG_GATE3_HZ_POS ) & REG_ANALOG_GATE3_HZ_MSK) #define REG_ANALOG_GATE3_ILIM_POS 10 #define REG_ANALOG_GATE3_ILIM_MSK (0x1ul << REG_ANALOG_GATE3_ILIM_POS) #define REG_ANALOG_GATE3_ILIM_SET(num) (((num) << REG_ANALOG_GATE3_ILIM_POS ) & REG_ANALOG_GATE3_ILIM_MSK) #define REG_ANALOG_GATE3_DIS_ILIM_POS 11 #define REG_ANALOG_GATE3_DIS_ILIM_MSK (0x1ul << REG_ANALOG_GATE3_DIS_ILIM_POS) #define REG_ANALOG_GATE3_DIS_ILIM_SET(num) (((num) << REG_ANALOG_GATE3_DIS_ILIM_POS ) & REG_ANALOG_GATE3_DIS_ILIM_MSK) #define REG_ANALOG_GATE3_VOLTAGE_SEL_POS 12 #define REG_ANALOG_GATE3_VOLTAGE_SEL_MSK (0x7ul << REG_ANALOG_GATE3_VOLTAGE_SEL_POS) #define REG_ANALOG_GATE3_VOLTAGE_SEL_SET(num) (((num) << REG_ANALOG_GATE3_VOLTAGE_SEL_POS ) & REG_ANALOG_GATE3_VOLTAGE_SEL_MSK) #define REG_ANALOG_GP_IE_POS 0 #define REG_ANALOG_GP_IE_MSK (0x3FFul << REG_ANALOG_GP_IE_POS) #define REG_ANALOG_GP_IE_SET(num) (((num) << REG_ANALOG_GP_IE_POS ) & REG_ANALOG_GP_IE_MSK) #define REG_ANALOG_GP_AIE_POS 10 #define REG_ANALOG_GP_AIE_MSK (0x3FFul << REG_ANALOG_GP_AIE_POS) #define REG_ANALOG_GP_AIE_SET(num) (((num) << REG_ANALOG_GP_AIE_POS ) & REG_ANALOG_GP_AIE_MSK) #define REG_ANALOG_IO_CC1_1_IE_POS 0 #define REG_ANALOG_IO_CC1_1_IE_MSK (0x1ul << REG_ANALOG_IO_CC1_1_IE_POS) #define REG_ANALOG_IO_CC1_1_IE_SET(num) (((num) << REG_ANALOG_IO_CC1_1_IE_POS ) & REG_ANALOG_IO_CC1_1_IE_MSK) #define REG_ANALOG_IO_CC2_1_IE_POS 1 #define REG_ANALOG_IO_CC2_1_IE_MSK (0x1ul << REG_ANALOG_IO_CC2_1_IE_POS) #define REG_ANALOG_IO_CC2_1_IE_SET(num) (((num) << REG_ANALOG_IO_CC2_1_IE_POS ) & REG_ANALOG_IO_CC2_1_IE_MSK) #define REG_ANALOG_IO_CC1_2_IE_POS 2 #define REG_ANALOG_IO_CC1_2_IE_MSK (0x1ul << REG_ANALOG_IO_CC1_2_IE_POS) #define REG_ANALOG_IO_CC1_2_IE_SET(num) (((num) << REG_ANALOG_IO_CC1_2_IE_POS ) & REG_ANALOG_IO_CC1_2_IE_MSK) #define REG_ANALOG_IO_CC2_2_IE_POS 3 #define REG_ANALOG_IO_CC2_2_IE_MSK (0x1ul << REG_ANALOG_IO_CC2_2_IE_POS) #define REG_ANALOG_IO_CC2_2_IE_SET(num) (((num) << REG_ANALOG_IO_CC2_2_IE_POS ) & REG_ANALOG_IO_CC2_2_IE_MSK) #define REG_ANALOG_IO_COMP1_IE_POS 4 #define REG_ANALOG_IO_COMP1_IE_MSK (0x1ul << REG_ANALOG_IO_COMP1_IE_POS) #define REG_ANALOG_IO_COMP1_IE_SET(num) (((num) << REG_ANALOG_IO_COMP1_IE_POS ) & REG_ANALOG_IO_COMP1_IE_MSK) #define REG_ANALOG_IO_FB2_IE_POS 5 #define REG_ANALOG_IO_FB2_IE_MSK (0x1ul << REG_ANALOG_IO_FB2_IE_POS) #define REG_ANALOG_IO_FB2_IE_SET(num) (((num) << REG_ANALOG_IO_FB2_IE_POS ) & REG_ANALOG_IO_FB2_IE_MSK) #define REG_ANALOG_IO_COMP2_IE_POS 6 #define REG_ANALOG_IO_COMP2_IE_MSK (0x1ul << REG_ANALOG_IO_COMP2_IE_POS) #define REG_ANALOG_IO_COMP2_IE_SET(num) (((num) << REG_ANALOG_IO_COMP2_IE_POS ) & REG_ANALOG_IO_COMP2_IE_MSK) #define REG_ANALOG_IO_VFB_IE_POS 7 #define REG_ANALOG_IO_VFB_IE_MSK (0x1ul << REG_ANALOG_IO_VFB_IE_POS) #define REG_ANALOG_IO_VFB_IE_SET(num) (((num) << REG_ANALOG_IO_VFB_IE_POS ) & REG_ANALOG_IO_VFB_IE_MSK) #define REG_ANALOG_IO_CC1_1_AIE_POS 16 #define REG_ANALOG_IO_CC1_1_AIE_MSK (0x1ul << REG_ANALOG_IO_CC1_1_AIE_POS) #define REG_ANALOG_IO_CC1_1_AIE_SET(num) (((num) << REG_ANALOG_IO_CC1_1_AIE_POS ) & REG_ANALOG_IO_CC1_1_AIE_MSK) #define REG_ANALOG_IO_CC2_1_AIE_POS 17 #define REG_ANALOG_IO_CC2_1_AIE_MSK (0x1ul << REG_ANALOG_IO_CC2_1_AIE_POS) #define REG_ANALOG_IO_CC2_1_AIE_SET(num) (((num) << REG_ANALOG_IO_CC2_1_AIE_POS ) & REG_ANALOG_IO_CC2_1_AIE_MSK) #define REG_ANALOG_IO_CC1_2_AIE_POS 18 #define REG_ANALOG_IO_CC1_2_AIE_MSK (0x1ul << REG_ANALOG_IO_CC1_2_AIE_POS) #define REG_ANALOG_IO_CC1_2_AIE_SET(num) (((num) << REG_ANALOG_IO_CC1_2_AIE_POS ) & REG_ANALOG_IO_CC1_2_AIE_MSK) #define REG_ANALOG_IO_CC2_2_AIE_POS 19 #define REG_ANALOG_IO_CC2_2_AIE_MSK (0x1ul << REG_ANALOG_IO_CC2_2_AIE_POS) #define REG_ANALOG_IO_CC2_2_AIE_SET(num) (((num) << REG_ANALOG_IO_CC2_2_AIE_POS ) & REG_ANALOG_IO_CC2_2_AIE_MSK) #define REG_ANALOG_IO_COMP1_AIE_POS 20 #define REG_ANALOG_IO_COMP1_AIE_MSK (0x1ul << REG_ANALOG_IO_COMP1_AIE_POS) #define REG_ANALOG_IO_COMP1_AIE_SET(num) (((num) << REG_ANALOG_IO_COMP1_AIE_POS ) & REG_ANALOG_IO_COMP1_AIE_MSK) #define REG_ANALOG_IO_FB2_AIE_POS 21 #define REG_ANALOG_IO_FB2_AIE_MSK (0x1ul << REG_ANALOG_IO_FB2_AIE_POS) #define REG_ANALOG_IO_FB2_AIE_SET(num) (((num) << REG_ANALOG_IO_FB2_AIE_POS ) & REG_ANALOG_IO_FB2_AIE_MSK) #define REG_ANALOG_IO_COMP2_AIE_POS 22 #define REG_ANALOG_IO_COMP2_AIE_MSK (0x1ul << REG_ANALOG_IO_COMP2_AIE_POS) #define REG_ANALOG_IO_COMP2_AIE_SET(num) (((num) << REG_ANALOG_IO_COMP2_AIE_POS ) & REG_ANALOG_IO_COMP2_AIE_MSK) #define REG_ANALOG_IO_VFB_AIE_POS 23 #define REG_ANALOG_IO_VFB_AIE_MSK (0x1ul << REG_ANALOG_IO_VFB_AIE_POS) #define REG_ANALOG_IO_VFB_AIE_SET(num) (((num) << REG_ANALOG_IO_VFB_AIE_POS ) & REG_ANALOG_IO_VFB_AIE_MSK) #define REG_ANALOG_GP0_ODEN_POS 0 #define REG_ANALOG_GP0_ODEN_MSK (0x3FFFFul << REG_ANALOG_GP0_ODEN_POS) #define REG_ANALOG_GP0_ODEN_SET(num) (((num) << REG_ANALOG_GP0_ODEN_POS ) & REG_ANALOG_GP0_ODEN_MSK) #define REG_ANALOG_GP_TIE_H_EN_POS 0 #define REG_ANALOG_GP_TIE_H_EN_MSK (0x3FFul << REG_ANALOG_GP_TIE_H_EN_POS) #define REG_ANALOG_GP_TIE_H_EN_SET(num) (((num) << REG_ANALOG_GP_TIE_H_EN_POS ) & REG_ANALOG_GP_TIE_H_EN_MSK) #define REG_ANALOG_GP_TIE_L_EN_POS 10 #define REG_ANALOG_GP_TIE_L_EN_MSK (0x3FFul << REG_ANALOG_GP_TIE_L_EN_POS) #define REG_ANALOG_GP_TIE_L_EN_SET(num) (((num) << REG_ANALOG_GP_TIE_L_EN_POS ) & REG_ANALOG_GP_TIE_L_EN_MSK) #define REG_ANALOG_IO_TIE_CC1_1_H_EN_POS 0 #define REG_ANALOG_IO_TIE_CC1_1_H_EN_MSK (0x1ul << REG_ANALOG_IO_TIE_CC1_1_H_EN_POS) #define REG_ANALOG_IO_TIE_CC1_1_H_EN_SET(num) (((num) << REG_ANALOG_IO_TIE_CC1_1_H_EN_POS ) & REG_ANALOG_IO_TIE_CC1_1_H_EN_MSK) #define REG_ANALOG_IO_TIE_CC2_1_H_EN_POS 1 #define REG_ANALOG_IO_TIE_CC2_1_H_EN_MSK (0x1ul << REG_ANALOG_IO_TIE_CC2_1_H_EN_POS) #define REG_ANALOG_IO_TIE_CC2_1_H_EN_SET(num) (((num) << REG_ANALOG_IO_TIE_CC2_1_H_EN_POS ) & REG_ANALOG_IO_TIE_CC2_1_H_EN_MSK) #define REG_ANALOG_IO_TIE_CC1_2_H_EN_POS 2 #define REG_ANALOG_IO_TIE_CC1_2_H_EN_MSK (0x1ul << REG_ANALOG_IO_TIE_CC1_2_H_EN_POS) #define REG_ANALOG_IO_TIE_CC1_2_H_EN_SET(num) (((num) << REG_ANALOG_IO_TIE_CC1_2_H_EN_POS ) & REG_ANALOG_IO_TIE_CC1_2_H_EN_MSK) #define REG_ANALOG_IO_TIE_CC2_2_H_EN_POS 3 #define REG_ANALOG_IO_TIE_CC2_2_H_EN_MSK (0x1ul << REG_ANALOG_IO_TIE_CC2_2_H_EN_POS) #define REG_ANALOG_IO_TIE_CC2_2_H_EN_SET(num) (((num) << REG_ANALOG_IO_TIE_CC2_2_H_EN_POS ) & REG_ANALOG_IO_TIE_CC2_2_H_EN_MSK) #define REG_ANALOG_IO_TIE_COMP1_H_EN_POS 4 #define REG_ANALOG_IO_TIE_COMP1_H_EN_MSK (0x1ul << REG_ANALOG_IO_TIE_COMP1_H_EN_POS) #define REG_ANALOG_IO_TIE_COMP1_H_EN_SET(num) (((num) << REG_ANALOG_IO_TIE_COMP1_H_EN_POS ) & REG_ANALOG_IO_TIE_COMP1_H_EN_MSK) #define REG_ANALOG_IO_TIE_FB2_H_EN_POS 5 #define REG_ANALOG_IO_TIE_FB2_H_EN_MSK (0x1ul << REG_ANALOG_IO_TIE_FB2_H_EN_POS) #define REG_ANALOG_IO_TIE_FB2_H_EN_SET(num) (((num) << REG_ANALOG_IO_TIE_FB2_H_EN_POS ) & REG_ANALOG_IO_TIE_FB2_H_EN_MSK) #define REG_ANALOG_IO_TIE_COMP2_H_EN_POS 6 #define REG_ANALOG_IO_TIE_COMP2_H_EN_MSK (0x1ul << REG_ANALOG_IO_TIE_COMP2_H_EN_POS) #define REG_ANALOG_IO_TIE_COMP2_H_EN_SET(num) (((num) << REG_ANALOG_IO_TIE_COMP2_H_EN_POS ) & REG_ANALOG_IO_TIE_COMP2_H_EN_MSK) #define REG_ANALOG_IO_TIE_VFB_H_EN_POS 7 #define REG_ANALOG_IO_TIE_VFB_H_EN_MSK (0x1ul << REG_ANALOG_IO_TIE_VFB_H_EN_POS) #define REG_ANALOG_IO_TIE_VFB_H_EN_SET(num) (((num) << REG_ANALOG_IO_TIE_VFB_H_EN_POS ) & REG_ANALOG_IO_TIE_VFB_H_EN_MSK) #define REG_ANALOG_IO_TIE_CC1_1_L_EN_POS 16 #define REG_ANALOG_IO_TIE_CC1_1_L_EN_MSK (0x1ul << REG_ANALOG_IO_TIE_CC1_1_L_EN_POS) #define REG_ANALOG_IO_TIE_CC1_1_L_EN_SET(num) (((num) << REG_ANALOG_IO_TIE_CC1_1_L_EN_POS ) & REG_ANALOG_IO_TIE_CC1_1_L_EN_MSK) #define REG_ANALOG_IO_TIE_CC2_1_L_EN_POS 17 #define REG_ANALOG_IO_TIE_CC2_1_L_EN_MSK (0x1ul << REG_ANALOG_IO_TIE_CC2_1_L_EN_POS) #define REG_ANALOG_IO_TIE_CC2_1_L_EN_SET(num) (((num) << REG_ANALOG_IO_TIE_CC2_1_L_EN_POS ) & REG_ANALOG_IO_TIE_CC2_1_L_EN_MSK) #define REG_ANALOG_IO_TIE_CC1_2_L_EN_POS 18 #define REG_ANALOG_IO_TIE_CC1_2_L_EN_MSK (0x1ul << REG_ANALOG_IO_TIE_CC1_2_L_EN_POS) #define REG_ANALOG_IO_TIE_CC1_2_L_EN_SET(num) (((num) << REG_ANALOG_IO_TIE_CC1_2_L_EN_POS ) & REG_ANALOG_IO_TIE_CC1_2_L_EN_MSK) #define REG_ANALOG_IO_TIE_CC2_2_L_EN_POS 19 #define REG_ANALOG_IO_TIE_CC2_2_L_EN_MSK (0x1ul << REG_ANALOG_IO_TIE_CC2_2_L_EN_POS) #define REG_ANALOG_IO_TIE_CC2_2_L_EN_SET(num) (((num) << REG_ANALOG_IO_TIE_CC2_2_L_EN_POS ) & REG_ANALOG_IO_TIE_CC2_2_L_EN_MSK) #define REG_ANALOG_IO_TIE_COMP1_L_EN_POS 20 #define REG_ANALOG_IO_TIE_COMP1_L_EN_MSK (0x1ul << REG_ANALOG_IO_TIE_COMP1_L_EN_POS) #define REG_ANALOG_IO_TIE_COMP1_L_EN_SET(num) (((num) << REG_ANALOG_IO_TIE_COMP1_L_EN_POS ) & REG_ANALOG_IO_TIE_COMP1_L_EN_MSK) #define REG_ANALOG_IO_TIE_FB2_L_EN_POS 21 #define REG_ANALOG_IO_TIE_FB2_L_EN_MSK (0x1ul << REG_ANALOG_IO_TIE_FB2_L_EN_POS) #define REG_ANALOG_IO_TIE_FB2_L_EN_SET(num) (((num) << REG_ANALOG_IO_TIE_FB2_L_EN_POS ) & REG_ANALOG_IO_TIE_FB2_L_EN_MSK) #define REG_ANALOG_IO_TIE_COMP2_L_EN_POS 22 #define REG_ANALOG_IO_TIE_COMP2_L_EN_MSK (0x1ul << REG_ANALOG_IO_TIE_COMP2_L_EN_POS) #define REG_ANALOG_IO_TIE_COMP2_L_EN_SET(num) (((num) << REG_ANALOG_IO_TIE_COMP2_L_EN_POS ) & REG_ANALOG_IO_TIE_COMP2_L_EN_MSK) #define REG_ANALOG_IO_TIE_VFB_L_EN_POS 23 #define REG_ANALOG_IO_TIE_VFB_L_EN_MSK (0x1ul << REG_ANALOG_IO_TIE_VFB_L_EN_POS) #define REG_ANALOG_IO_TIE_VFB_L_EN_SET(num) (((num) << REG_ANALOG_IO_TIE_VFB_L_EN_POS ) & REG_ANALOG_IO_TIE_VFB_L_EN_MSK) #define REG_ANALOG_MTP_LDO5P7V_EN_POS 0 #define REG_ANALOG_MTP_LDO5P7V_EN_MSK (0x1ul << REG_ANALOG_MTP_LDO5P7V_EN_POS) #define REG_ANALOG_MTP_LDO5P7V_EN_SET(num) (((num) << REG_ANALOG_MTP_LDO5P7V_EN_POS ) & REG_ANALOG_MTP_LDO5P7V_EN_MSK) #define REG_ANALOG_VIN_SEL_POS 0 #define REG_ANALOG_VIN_SEL_MSK (0x1ul << REG_ANALOG_VIN_SEL_POS) #define REG_ANALOG_VIN_SEL_SET(num) (((num) << REG_ANALOG_VIN_SEL_POS ) & REG_ANALOG_VIN_SEL_MSK) #define REG_ANALOG_CSN1_LEAK_EN_POS 0 #define REG_ANALOG_CSN1_LEAK_EN_MSK (0x1ul << REG_ANALOG_CSN1_LEAK_EN_POS) #define REG_ANALOG_CSN1_LEAK_EN_SET(num) (((num) << REG_ANALOG_CSN1_LEAK_EN_POS ) & REG_ANALOG_CSN1_LEAK_EN_MSK) #define REG_ANALOG_CSN2_LEAK_EN_POS 0 #define REG_ANALOG_CSN2_LEAK_EN_MSK (0x1ul << REG_ANALOG_CSN2_LEAK_EN_POS) #define REG_ANALOG_CSN2_LEAK_EN_SET(num) (((num) << REG_ANALOG_CSN2_LEAK_EN_POS ) & REG_ANALOG_CSN2_LEAK_EN_MSK) #define REG_ANALOG_FB1_GMCOMP_EN_POS 0 #define REG_ANALOG_FB1_GMCOMP_EN_MSK (0x1ul << REG_ANALOG_FB1_GMCOMP_EN_POS) #define REG_ANALOG_FB1_GMCOMP_EN_SET(num) (((num) << REG_ANALOG_FB1_GMCOMP_EN_POS ) & REG_ANALOG_FB1_GMCOMP_EN_MSK) #define REG_ANALOG_FB1_COMP_GMSET_POS 1 #define REG_ANALOG_FB1_COMP_GMSET_MSK (0x1ul << REG_ANALOG_FB1_COMP_GMSET_POS) #define REG_ANALOG_FB1_COMP_GMSET_SET(num) (((num) << REG_ANALOG_FB1_COMP_GMSET_POS ) & REG_ANALOG_FB1_COMP_GMSET_MSK) #define REG_ANALOG_FB1_CC_GMSET_POS 2 #define REG_ANALOG_FB1_CC_GMSET_MSK (0x1ul << REG_ANALOG_FB1_CC_GMSET_POS) #define REG_ANALOG_FB1_CC_GMSET_SET(num) (((num) << REG_ANALOG_FB1_CC_GMSET_POS ) & REG_ANALOG_FB1_CC_GMSET_MSK) #define REG_ANALOG_FB1_CV_GMSET_POS 4 #define REG_ANALOG_FB1_CV_GMSET_MSK (0x1ul << REG_ANALOG_FB1_CV_GMSET_POS) #define REG_ANALOG_FB1_CV_GMSET_SET(num) (((num) << REG_ANALOG_FB1_CV_GMSET_POS ) & REG_ANALOG_FB1_CV_GMSET_MSK) #define REG_ANALOG_FB1_FBPATH_EN_POS 6 #define REG_ANALOG_FB1_FBPATH_EN_MSK (0x1ul << REG_ANALOG_FB1_FBPATH_EN_POS) #define REG_ANALOG_FB1_FBPATH_EN_SET(num) (((num) << REG_ANALOG_FB1_FBPATH_EN_POS ) & REG_ANALOG_FB1_FBPATH_EN_MSK) #define REG_ANALOG_FB1_RZ_POS 7 #define REG_ANALOG_FB1_RZ_MSK (0x3ul << REG_ANALOG_FB1_RZ_POS) #define REG_ANALOG_FB1_RZ_SET(num) (((num) << REG_ANALOG_FB1_RZ_POS ) & REG_ANALOG_FB1_RZ_MSK) #define REG_ANALOG_FB1_FBPULLHI_POS 9 #define REG_ANALOG_FB1_FBPULLHI_MSK (0x1ul << REG_ANALOG_FB1_FBPULLHI_POS) #define REG_ANALOG_FB1_FBPULLHI_SET(num) (((num) << REG_ANALOG_FB1_FBPULLHI_POS ) & REG_ANALOG_FB1_FBPULLHI_MSK) #define REG_ANALOG_FB1_FBCV_EN_POS 0 #define REG_ANALOG_FB1_FBCV_EN_MSK (0x1ul << REG_ANALOG_FB1_FBCV_EN_POS) #define REG_ANALOG_FB1_FBCV_EN_SET(num) (((num) << REG_ANALOG_FB1_FBCV_EN_POS ) & REG_ANALOG_FB1_FBCV_EN_MSK) #define REG_ANALOG_FB1_FB_MODE_POS 0 #define REG_ANALOG_FB1_FB_MODE_MSK (0x1ul << REG_ANALOG_FB1_FB_MODE_POS) #define REG_ANALOG_FB1_FB_MODE_SET(num) (((num) << REG_ANALOG_FB1_FB_MODE_POS ) & REG_ANALOG_FB1_FB_MODE_MSK) #define REG_ANALOG_FB2_GMCOMP_EN_POS 0 #define REG_ANALOG_FB2_GMCOMP_EN_MSK (0x1ul << REG_ANALOG_FB2_GMCOMP_EN_POS) #define REG_ANALOG_FB2_GMCOMP_EN_SET(num) (((num) << REG_ANALOG_FB2_GMCOMP_EN_POS ) & REG_ANALOG_FB2_GMCOMP_EN_MSK) #define REG_ANALOG_FB2_COMP_GMSET_POS 1 #define REG_ANALOG_FB2_COMP_GMSET_MSK (0x1ul << REG_ANALOG_FB2_COMP_GMSET_POS) #define REG_ANALOG_FB2_COMP_GMSET_SET(num) (((num) << REG_ANALOG_FB2_COMP_GMSET_POS ) & REG_ANALOG_FB2_COMP_GMSET_MSK) #define REG_ANALOG_FB2_CC_GMSET_POS 2 #define REG_ANALOG_FB2_CC_GMSET_MSK (0x1ul << REG_ANALOG_FB2_CC_GMSET_POS) #define REG_ANALOG_FB2_CC_GMSET_SET(num) (((num) << REG_ANALOG_FB2_CC_GMSET_POS ) & REG_ANALOG_FB2_CC_GMSET_MSK) #define REG_ANALOG_FB2_CV_GMSET_POS 4 #define REG_ANALOG_FB2_CV_GMSET_MSK (0x1ul << REG_ANALOG_FB2_CV_GMSET_POS) #define REG_ANALOG_FB2_CV_GMSET_SET(num) (((num) << REG_ANALOG_FB2_CV_GMSET_POS ) & REG_ANALOG_FB2_CV_GMSET_MSK) #define REG_ANALOG_FB2_FBPATH_EN_POS 6 #define REG_ANALOG_FB2_FBPATH_EN_MSK (0x1ul << REG_ANALOG_FB2_FBPATH_EN_POS) #define REG_ANALOG_FB2_FBPATH_EN_SET(num) (((num) << REG_ANALOG_FB2_FBPATH_EN_POS ) & REG_ANALOG_FB2_FBPATH_EN_MSK) #define REG_ANALOG_FB2_RZ_POS 7 #define REG_ANALOG_FB2_RZ_MSK (0x3ul << REG_ANALOG_FB2_RZ_POS) #define REG_ANALOG_FB2_RZ_SET(num) (((num) << REG_ANALOG_FB2_RZ_POS ) & REG_ANALOG_FB2_RZ_MSK) #define REG_ANALOG_FB2_FBPULLHI_POS 9 #define REG_ANALOG_FB2_FBPULLHI_MSK (0x1ul << REG_ANALOG_FB2_FBPULLHI_POS) #define REG_ANALOG_FB2_FBPULLHI_SET(num) (((num) << REG_ANALOG_FB2_FBPULLHI_POS ) & REG_ANALOG_FB2_FBPULLHI_MSK) #define REG_ANALOG_FB2_FBCV_EN_POS 0 #define REG_ANALOG_FB2_FBCV_EN_MSK (0x1ul << REG_ANALOG_FB2_FBCV_EN_POS) #define REG_ANALOG_FB2_FBCV_EN_SET(num) (((num) << REG_ANALOG_FB2_FBCV_EN_POS ) & REG_ANALOG_FB2_FBCV_EN_MSK) #define REG_ANALOG_FB2_FB_MODE_POS 0 #define REG_ANALOG_FB2_FB_MODE_MSK (0x1ul << REG_ANALOG_FB2_FB_MODE_POS) #define REG_ANALOG_FB2_FB_MODE_SET(num) (((num) << REG_ANALOG_FB2_FB_MODE_POS ) & REG_ANALOG_FB2_FB_MODE_MSK) #endif /*__ANALOG_DEFINE_H__*/