#ifndef __PD_DEFINE_H__ #define __PD_DEFINE_H__ //----------------------------------------------------------------------------- // pd registers definition //----------------------------------------------------------------------------- #pragma anon_unions //----------------------------------------------------------------------------- // registers structures typedef struct { //1: manually measure the voltage on cc1. uint32_t meas_cc1:1; //1: manually measure the voltage on cc2. uint32_t meas_cc2:1; //1: turn on the vconn current to cc1 pin uint32_t vconn_cc1:1; //1: turn on the vconn current to cc2 pin uint32_t vconn_cc2:1; //1: apply host pull up current to cc1 pin uint32_t pu_en1:1; //1: apply host pull up current to cc2 pin uint32_t pu_en2:1; uint32_t reserved_7_6:2; //1:enable cc1 comparator to measure the voltage on cc1 uint32_t comp_en_cc1:1; //1:enable cc2 comparator to measure the voltage on cc2 uint32_t comp_en_cc2:1; uint32_t reserved_31_10:22; } REG_pd_sw1_bitfiled_TypeDef; typedef struct { union { __IO REG_pd_sw1_bitfiled_TypeDef bf;//bitfiled __IO uint32_t word; }; } REG_pd_sw1_TypeDef; typedef struct { //select bmc transceiver on cc1 pin. uint32_t txcc1:1; //select bmc transceiver on cc2 pin. uint32_t txcc2:1; //sends a goodcrc acknowledge packet back to the relevant sop uint32_t auto_crc:1; uint32_t reserved_3_3:1; //used for goodcrc ack packet(port data role bit), for sop: 1:src, 0:snk uint32_t datarole:1; //00=revision 1.0 //01=revision 2.0 //10=revision 3.0 //11=do not use uint32_t specrev:2; //used for goodcrc ack packet(port power role bit), for sop: 1:src, 0:snk uint32_t powerrole:1; uint32_t reserved_31_8:24; } REG_pd_sw2_bitfiled_TypeDef; typedef struct { union { __IO REG_pd_sw2_bitfiled_TypeDef bf;//bitfiled __IO uint32_t word; }; } REG_pd_sw2_TypeDef; typedef struct { //tx_data uint32_t tx:8; //rx_data uint32_t rx:8; uint32_t reserved_31_16:16; } REG_pd_data_bitfiled_TypeDef; typedef struct { union { __IO REG_pd_data_bitfiled_TypeDef bf;//bitfiled __IO uint32_t word; }; } REG_pd_data_TypeDef; typedef struct { //1: enable tx uint32_t tx_start:1; //tx packet sop type //0: sop, 1: sop1, 2: sop2, 3: sop1_db, 4: sop2_db uint32_t tx_sop:3; //10=pd3.0 ,11=pd2.0 uint32_t n_retries:2; //controls the host pull up current enabled by pu_en[2:1] //0: no current //1: 80ua - default usb power（rp1) //2: 180ua - medium current mode: 1.5a(rp2) //3: 330ua - high current mode: 3a(rp3) uint32_t host_cur:2; //1:enable sop packets uint32_t en_sop:1; //1:enable sop' packets uint32_t en_sop1:1; //1:enable sop'' packets uint32_t en_sop2:1; //1:enable sop'_debug packets uint32_t en_sop1db:1; //1:enable sop''_debug packets uint32_t en_sop2db:1; uint32_t reserved_15_13:3; //1:enable sop packets auto crc independently uint32_t en_sop_auto_crc:1; //1:enable sop' packets auto crc independently uint32_t en_sop1_auto_crc:1; //1:enable sop'' packets auto crc independently uint32_t en_sop2_auto_crc:1; //1:enable sop'_db packets auto crc independently uint32_t en_sop1_db_auto_crc:1; //1:enable sop''_db packets auto crc independently uint32_t en_sop2_db_auto_crc:1; uint32_t reserved_23_21:3; //1:sent bist mode 01s pattern for testing. if bist_always_on=1, bist pattern will be kept sending out even if pattern timeout. uint32_t bist_mode2:1; //1=send a soft reset packet uint32_t send_softrst:1; //1=send a hard reset packet (highest priority) uint32_t send_hardrst:1; //1= open uint32_t auto_retry:1; //1: send out pattern length >= pattern time out (1351 pd bit time). after pattern time out , clear this bit would stop pattern , when clear this bit at pattern time < pattern time out, pattern would send at least 1351 pd bit time //0: only send out one pattern(1351 pd bit time). uint32_t bist_always_on:1; //1=ccx auto detect enable, 0=manual by register uint32_t wake_en:1; uint32_t reserved_31_30:2; } REG_pd_ctrl_bitfiled_TypeDef; typedef struct { union { __IO REG_pd_ctrl_bitfiled_TypeDef bf;//bitfiled __IO uint32_t word; }; } REG_pd_ctrl_TypeDef; typedef struct { //1: pd cc_comp_en // uint32_t cc_comp_en:1; uint32_t reserved_31_1:31; } REG_pd_power_bitfiled_TypeDef; typedef struct { union { __IO REG_pd_power_bitfiled_TypeDef bf;//bitfiled __IO uint32_t word; }; } REG_pd_power_TypeDef; typedef struct { //1=is reset including the i2c registers to their default values. uint32_t sw_reset:1; //1=reset just the pd logic for both the pd transmitter and receiver.. uint32_t pd_reset:1; uint32_t reserved_31_2:30; } REG_pd_reset_bitfiled_TypeDef; typedef struct { union { __IO REG_pd_reset_bitfiled_TypeDef bf;//bitfiled __IO uint32_t word; }; } REG_pd_reset_TypeDef; typedef struct { //1= hard reset pd ordered set has been received from rx uint32_t hardrst:1; //1=soft reset packet has been received from rx uint32_t softrst:1; //packets retries have failed to get a goodcrc acknowledge .this status is cleared when a start_tx, txon or send_softreset_reset ,send_hard_reset is execute uint32_t rertyfail:1; //1= indicates the last packet placed in the rxfifo is type sop. uint32_t rx_sop:1; //1= indicates the last packet placed is type sop`. uint32_t rx_sop1:1; //1= indicates the last packet placed is type sop``. uint32_t rx_sop2:1; //1= indicates the last packet placed is type sop`_db. uint32_t rx_sop1_db:1; //1= indicates the last packet placed is type sop``_db. uint32_t rx_sop2_db:1; //src: //00: open, 01: ra, 10: rd, 11: resv, uint32_t cc1:2; //src: //00: open, 01: ra, 10: rd, 11: resv uint32_t cc2:2; uint32_t reserved_14_12:3; //1= indicates the last received packet had the correct crc. this bit remains set until the sop of the next packet. //0= packet received for an enabled sop* and crc for the enabled packet received was incorrect. // uint32_t crc_chk:1; uint32_t reserved_16_16:1; //1=transitions are detected on the active cc* line. this bit goes high after a minimum of 3 cc transitions, and remains high for about 45us after last transition on cc uint32_t activity:1; uint32_t reserved_29_18:12; //receive mode, bmc end drive overtime uint32_t enddrviebmc_overtime:1; uint32_t reserved_31_31:1; } REG_pd_status_bitfiled_TypeDef; typedef struct { union { __IO REG_pd_status_bitfiled_TypeDef bf;//bitfiled __IO uint32_t word; }; } REG_pd_status_TypeDef; typedef struct { //pd interrupt mask, correspond int_flag uint32_t value:14; uint32_t reserved_31_14:18; } REG_pd_int_mask_bitfiled_TypeDef; typedef struct { union { __IO REG_pd_int_mask_bitfiled_TypeDef bf;//bitfiled __IO uint32_t word; }; } REG_pd_int_mask_TypeDef; typedef struct { //type c interrupt flag //bit0:tx_dma_sreq //bit1:rx_dma_sreq //bit2:rx_crc_chk //bit3:collision //bit4:retryfail //bit5:hardfail //bit6:hardrst //bit7:softrst //bit8:goodcrcsent //bit9:hardsent //bit10:txsent //bit11:pd_ccx_ovp bit12:pd_vcon_oc //bit13:pd_status_activity // uint32_t value:14; uint32_t reserved_31_14:18; } REG_pd_int_flag_bitfiled_TypeDef; typedef struct { union { __IO REG_pd_int_flag_bitfiled_TypeDef bf;//bitfiled __IO uint32_t word; }; } REG_pd_int_flag_TypeDef; typedef struct { uint32_t reserved_0_0:1; //1=rx fifo wr ptr rollback if crc error (default), 0=disable uint32_t en_rx_rollback:1; //1=check msg_id only when goodcrc feedback(default) 0:check msg_id+sop* uint32_t dis_fullcheck:1; //00=rxd_activity or txd_activity 01=rxd_activity 1x= txd_activity uint32_t activity_mode:2; uint32_t reserved_5_5:1; //1=force_txen uint32_t force_txen:1; //1=force_rxen uint32_t force_rxen:1; uint32_t reserved_11_8:4; //for dig_testsel uint32_t dig_testsel:4; uint32_t reserved_18_16:3; //reply goodcrc timer 0=80us 1=110us uint32_t transmit_timer:1; //wait time(us) for reply goodcrc uint32_t gap_gcf:12; } REG_pd_cfg_bitfiled_TypeDef; typedef struct { union { __IO REG_pd_cfg_bitfiled_TypeDef bf;//bitfiled __IO uint32_t word; }; } REG_pd_cfg_TypeDef; typedef struct { //good crc find fsm status uint32_t host_inf_gcf_cs:4; //send hardware reset fsm status uint32_t host_inf_hdr_cs:4; //tx fsm status uint32_t host_inf_txs_cs:2; //protocol layer tx retry fsm status uint32_t prltx_cur_state:5; uint32_t reserved_15_15:1; //tx channel fsm status uint32_t tx_cs:6; uint32_t reserved_23_22:2; //rx channel fsm status uint32_t rx_cs:6; uint32_t reserved_31_30:2; } REG_pd_fsm_mac_bitfiled_TypeDef; typedef struct { union { __IO REG_pd_fsm_mac_bitfiled_TypeDef bf;//bitfiled __IO uint32_t word; }; } REG_pd_fsm_mac_TypeDef; typedef struct { //pd phy tx bist fsm state uint32_t state_tx_bist:4; //pd phy tx fsm state uint32_t state_tx_phy:3; uint32_t reserved_31_7:25; } REG_pd_fsm_phy_bitfiled_TypeDef; typedef struct { union { __IO REG_pd_fsm_phy_bitfiled_TypeDef bf;//bitfiled __IO uint32_t word; }; } REG_pd_fsm_phy_TypeDef; //----------------------------------------------------------------------------- // memory map #define REG_PD_SW1_BASE 0x4000D800 #define REG_PD_SW2_BASE 0x4000D804 #define REG_PD_DATA_BASE 0x4000D810 #define REG_PD_CTRL_BASE 0x4000D814 #define REG_PD_POWER_BASE 0x4000D81C #define REG_PD_RESET_BASE 0x4000D820 #define REG_PD_STATUS_BASE 0x4000D824 #define REG_PD_INT_MASK_BASE 0x4000D828 #define REG_PD_INT_FLAG_BASE 0x4000D82C #define REG_PD_CFG_BASE 0x4000D830 #define REG_PD_FSM_MAC_BASE 0x4000D834 #define REG_PD_FSM_PHY_BASE 0x4000D838 //----------------------------------------------------------------------------- // declaration #define REG_PD_SW1 ((REG_pd_sw1_TypeDef *) REG_PD_SW1_BASE ) #define REG_PD_SW2 ((REG_pd_sw2_TypeDef *) REG_PD_SW2_BASE ) #define REG_PD_DATA ((REG_pd_data_TypeDef *) REG_PD_DATA_BASE ) #define REG_PD_CTRL ((REG_pd_ctrl_TypeDef *) REG_PD_CTRL_BASE ) #define REG_PD_POWER ((REG_pd_power_TypeDef *) REG_PD_POWER_BASE ) #define REG_PD_RESET ((REG_pd_reset_TypeDef *) REG_PD_RESET_BASE ) #define REG_PD_STATUS ((REG_pd_status_TypeDef *) REG_PD_STATUS_BASE ) #define REG_PD_INT_MASK ((REG_pd_int_mask_TypeDef *) REG_PD_INT_MASK_BASE ) #define REG_PD_INT_FLAG ((REG_pd_int_flag_TypeDef *) REG_PD_INT_FLAG_BASE ) #define REG_PD_CFG ((REG_pd_cfg_TypeDef *) REG_PD_CFG_BASE ) #define REG_PD_FSM_MAC ((REG_pd_fsm_mac_TypeDef *) REG_PD_FSM_MAC_BASE ) #define REG_PD_FSM_PHY ((REG_pd_fsm_phy_TypeDef *) REG_PD_FSM_PHY_BASE ) //----------------------------------------------------------------------------- // set #define REG_PD_SW1_MEAS_CC1_POS 0 #define REG_PD_SW1_MEAS_CC1_MSK (0x1ul << REG_PD_SW1_MEAS_CC1_POS) #define REG_PD_SW1_MEAS_CC1_SET(num) (((num) << REG_PD_SW1_MEAS_CC1_POS ) & REG_PD_SW1_MEAS_CC1_MSK) #define REG_PD_SW1_MEAS_CC2_POS 1 #define REG_PD_SW1_MEAS_CC2_MSK (0x1ul << REG_PD_SW1_MEAS_CC2_POS) #define REG_PD_SW1_MEAS_CC2_SET(num) (((num) << REG_PD_SW1_MEAS_CC2_POS ) & REG_PD_SW1_MEAS_CC2_MSK) #define REG_PD_SW1_VCONN_CC1_POS 2 #define REG_PD_SW1_VCONN_CC1_MSK (0x1ul << REG_PD_SW1_VCONN_CC1_POS) #define REG_PD_SW1_VCONN_CC1_SET(num) (((num) << REG_PD_SW1_VCONN_CC1_POS ) & REG_PD_SW1_VCONN_CC1_MSK) #define REG_PD_SW1_VCONN_CC2_POS 3 #define REG_PD_SW1_VCONN_CC2_MSK (0x1ul << REG_PD_SW1_VCONN_CC2_POS) #define REG_PD_SW1_VCONN_CC2_SET(num) (((num) << REG_PD_SW1_VCONN_CC2_POS ) & REG_PD_SW1_VCONN_CC2_MSK) #define REG_PD_SW1_PU_EN1_POS 4 #define REG_PD_SW1_PU_EN1_MSK (0x1ul << REG_PD_SW1_PU_EN1_POS) #define REG_PD_SW1_PU_EN1_SET(num) (((num) << REG_PD_SW1_PU_EN1_POS ) & REG_PD_SW1_PU_EN1_MSK) #define REG_PD_SW1_PU_EN2_POS 5 #define REG_PD_SW1_PU_EN2_MSK (0x1ul << REG_PD_SW1_PU_EN2_POS) #define REG_PD_SW1_PU_EN2_SET(num) (((num) << REG_PD_SW1_PU_EN2_POS ) & REG_PD_SW1_PU_EN2_MSK) #define REG_PD_SW1_COMP_EN_CC1_POS 8 #define REG_PD_SW1_COMP_EN_CC1_MSK (0x1ul << REG_PD_SW1_COMP_EN_CC1_POS) #define REG_PD_SW1_COMP_EN_CC1_SET(num) (((num) << REG_PD_SW1_COMP_EN_CC1_POS ) & REG_PD_SW1_COMP_EN_CC1_MSK) #define REG_PD_SW1_COMP_EN_CC2_POS 9 #define REG_PD_SW1_COMP_EN_CC2_MSK (0x1ul << REG_PD_SW1_COMP_EN_CC2_POS) #define REG_PD_SW1_COMP_EN_CC2_SET(num) (((num) << REG_PD_SW1_COMP_EN_CC2_POS ) & REG_PD_SW1_COMP_EN_CC2_MSK) #define REG_PD_SW2_TXCC1_POS 0 #define REG_PD_SW2_TXCC1_MSK (0x1ul << REG_PD_SW2_TXCC1_POS) #define REG_PD_SW2_TXCC1_SET(num) (((num) << REG_PD_SW2_TXCC1_POS ) & REG_PD_SW2_TXCC1_MSK) #define REG_PD_SW2_TXCC2_POS 1 #define REG_PD_SW2_TXCC2_MSK (0x1ul << REG_PD_SW2_TXCC2_POS) #define REG_PD_SW2_TXCC2_SET(num) (((num) << REG_PD_SW2_TXCC2_POS ) & REG_PD_SW2_TXCC2_MSK) #define REG_PD_SW2_AUTO_CRC_POS 2 #define REG_PD_SW2_AUTO_CRC_MSK (0x1ul << REG_PD_SW2_AUTO_CRC_POS) #define REG_PD_SW2_AUTO_CRC_SET(num) (((num) << REG_PD_SW2_AUTO_CRC_POS ) & REG_PD_SW2_AUTO_CRC_MSK) #define REG_PD_SW2_DATAROLE_POS 4 #define REG_PD_SW2_DATAROLE_MSK (0x1ul << REG_PD_SW2_DATAROLE_POS) #define REG_PD_SW2_DATAROLE_SET(num) (((num) << REG_PD_SW2_DATAROLE_POS ) & REG_PD_SW2_DATAROLE_MSK) #define REG_PD_SW2_SPECREV_POS 5 #define REG_PD_SW2_SPECREV_MSK (0x3ul << REG_PD_SW2_SPECREV_POS) #define REG_PD_SW2_SPECREV_SET(num) (((num) << REG_PD_SW2_SPECREV_POS ) & REG_PD_SW2_SPECREV_MSK) #define REG_PD_SW2_POWERROLE_POS 7 #define REG_PD_SW2_POWERROLE_MSK (0x1ul << REG_PD_SW2_POWERROLE_POS) #define REG_PD_SW2_POWERROLE_SET(num) (((num) << REG_PD_SW2_POWERROLE_POS ) & REG_PD_SW2_POWERROLE_MSK) #define REG_PD_DATA_TX_POS 0 #define REG_PD_DATA_TX_MSK (0xFFul << REG_PD_DATA_TX_POS) #define REG_PD_DATA_TX_SET(num) (((num) << REG_PD_DATA_TX_POS ) & REG_PD_DATA_TX_MSK) #define REG_PD_CTRL_TX_START_POS 0 #define REG_PD_CTRL_TX_START_MSK (0x1ul << REG_PD_CTRL_TX_START_POS) #define REG_PD_CTRL_TX_START_SET(num) (((num) << REG_PD_CTRL_TX_START_POS ) & REG_PD_CTRL_TX_START_MSK) #define REG_PD_CTRL_TX_SOP_POS 1 #define REG_PD_CTRL_TX_SOP_MSK (0x7ul << REG_PD_CTRL_TX_SOP_POS) #define REG_PD_CTRL_TX_SOP_SET(num) (((num) << REG_PD_CTRL_TX_SOP_POS ) & REG_PD_CTRL_TX_SOP_MSK) #define REG_PD_CTRL_N_RETRIES_POS 4 #define REG_PD_CTRL_N_RETRIES_MSK (0x3ul << REG_PD_CTRL_N_RETRIES_POS) #define REG_PD_CTRL_N_RETRIES_SET(num) (((num) << REG_PD_CTRL_N_RETRIES_POS ) & REG_PD_CTRL_N_RETRIES_MSK) #define REG_PD_CTRL_HOST_CUR_POS 6 #define REG_PD_CTRL_HOST_CUR_MSK (0x3ul << REG_PD_CTRL_HOST_CUR_POS) #define REG_PD_CTRL_HOST_CUR_SET(num) (((num) << REG_PD_CTRL_HOST_CUR_POS ) & REG_PD_CTRL_HOST_CUR_MSK) #define REG_PD_CTRL_EN_SOP_POS 8 #define REG_PD_CTRL_EN_SOP_MSK (0x1ul << REG_PD_CTRL_EN_SOP_POS) #define REG_PD_CTRL_EN_SOP_SET(num) (((num) << REG_PD_CTRL_EN_SOP_POS ) & REG_PD_CTRL_EN_SOP_MSK) #define REG_PD_CTRL_EN_SOP1_POS 9 #define REG_PD_CTRL_EN_SOP1_MSK (0x1ul << REG_PD_CTRL_EN_SOP1_POS) #define REG_PD_CTRL_EN_SOP1_SET(num) (((num) << REG_PD_CTRL_EN_SOP1_POS ) & REG_PD_CTRL_EN_SOP1_MSK) #define REG_PD_CTRL_EN_SOP2_POS 10 #define REG_PD_CTRL_EN_SOP2_MSK (0x1ul << REG_PD_CTRL_EN_SOP2_POS) #define REG_PD_CTRL_EN_SOP2_SET(num) (((num) << REG_PD_CTRL_EN_SOP2_POS ) & REG_PD_CTRL_EN_SOP2_MSK) #define REG_PD_CTRL_EN_SOP1DB_POS 11 #define REG_PD_CTRL_EN_SOP1DB_MSK (0x1ul << REG_PD_CTRL_EN_SOP1DB_POS) #define REG_PD_CTRL_EN_SOP1DB_SET(num) (((num) << REG_PD_CTRL_EN_SOP1DB_POS ) & REG_PD_CTRL_EN_SOP1DB_MSK) #define REG_PD_CTRL_EN_SOP2DB_POS 12 #define REG_PD_CTRL_EN_SOP2DB_MSK (0x1ul << REG_PD_CTRL_EN_SOP2DB_POS) #define REG_PD_CTRL_EN_SOP2DB_SET(num) (((num) << REG_PD_CTRL_EN_SOP2DB_POS ) & REG_PD_CTRL_EN_SOP2DB_MSK) #define REG_PD_CTRL_EN_SOP_AUTO_CRC_POS 16 #define REG_PD_CTRL_EN_SOP_AUTO_CRC_MSK (0x1ul << REG_PD_CTRL_EN_SOP_AUTO_CRC_POS) #define REG_PD_CTRL_EN_SOP_AUTO_CRC_SET(num) (((num) << REG_PD_CTRL_EN_SOP_AUTO_CRC_POS ) & REG_PD_CTRL_EN_SOP_AUTO_CRC_MSK) #define REG_PD_CTRL_EN_SOP1_AUTO_CRC_POS 17 #define REG_PD_CTRL_EN_SOP1_AUTO_CRC_MSK (0x1ul << REG_PD_CTRL_EN_SOP1_AUTO_CRC_POS) #define REG_PD_CTRL_EN_SOP1_AUTO_CRC_SET(num) (((num) << REG_PD_CTRL_EN_SOP1_AUTO_CRC_POS ) & REG_PD_CTRL_EN_SOP1_AUTO_CRC_MSK) #define REG_PD_CTRL_EN_SOP2_AUTO_CRC_POS 18 #define REG_PD_CTRL_EN_SOP2_AUTO_CRC_MSK (0x1ul << REG_PD_CTRL_EN_SOP2_AUTO_CRC_POS) #define REG_PD_CTRL_EN_SOP2_AUTO_CRC_SET(num) (((num) << REG_PD_CTRL_EN_SOP2_AUTO_CRC_POS ) & REG_PD_CTRL_EN_SOP2_AUTO_CRC_MSK) #define REG_PD_CTRL_EN_SOP1_DB_AUTO_CRC_POS 19 #define REG_PD_CTRL_EN_SOP1_DB_AUTO_CRC_MSK (0x1ul << REG_PD_CTRL_EN_SOP1_DB_AUTO_CRC_POS) #define REG_PD_CTRL_EN_SOP1_DB_AUTO_CRC_SET(num) (((num) << REG_PD_CTRL_EN_SOP1_DB_AUTO_CRC_POS ) & REG_PD_CTRL_EN_SOP1_DB_AUTO_CRC_MSK) #define REG_PD_CTRL_EN_SOP2_DB_AUTO_CRC_POS 20 #define REG_PD_CTRL_EN_SOP2_DB_AUTO_CRC_MSK (0x1ul << REG_PD_CTRL_EN_SOP2_DB_AUTO_CRC_POS) #define REG_PD_CTRL_EN_SOP2_DB_AUTO_CRC_SET(num) (((num) << REG_PD_CTRL_EN_SOP2_DB_AUTO_CRC_POS ) & REG_PD_CTRL_EN_SOP2_DB_AUTO_CRC_MSK) #define REG_PD_CTRL_BIST_MODE2_POS 24 #define REG_PD_CTRL_BIST_MODE2_MSK (0x1ul << REG_PD_CTRL_BIST_MODE2_POS) #define REG_PD_CTRL_BIST_MODE2_SET(num) (((num) << REG_PD_CTRL_BIST_MODE2_POS ) & REG_PD_CTRL_BIST_MODE2_MSK) #define REG_PD_CTRL_SEND_SOFTRST_POS 25 #define REG_PD_CTRL_SEND_SOFTRST_MSK (0x1ul << REG_PD_CTRL_SEND_SOFTRST_POS) #define REG_PD_CTRL_SEND_SOFTRST_SET(num) (((num) << REG_PD_CTRL_SEND_SOFTRST_POS ) & REG_PD_CTRL_SEND_SOFTRST_MSK) #define REG_PD_CTRL_SEND_HARDRST_POS 26 #define REG_PD_CTRL_SEND_HARDRST_MSK (0x1ul << REG_PD_CTRL_SEND_HARDRST_POS) #define REG_PD_CTRL_SEND_HARDRST_SET(num) (((num) << REG_PD_CTRL_SEND_HARDRST_POS ) & REG_PD_CTRL_SEND_HARDRST_MSK) #define REG_PD_CTRL_AUTO_RETRY_POS 27 #define REG_PD_CTRL_AUTO_RETRY_MSK (0x1ul << REG_PD_CTRL_AUTO_RETRY_POS) #define REG_PD_CTRL_AUTO_RETRY_SET(num) (((num) << REG_PD_CTRL_AUTO_RETRY_POS ) & REG_PD_CTRL_AUTO_RETRY_MSK) #define REG_PD_CTRL_BIST_ALWAYS_ON_POS 28 #define REG_PD_CTRL_BIST_ALWAYS_ON_MSK (0x1ul << REG_PD_CTRL_BIST_ALWAYS_ON_POS) #define REG_PD_CTRL_BIST_ALWAYS_ON_SET(num) (((num) << REG_PD_CTRL_BIST_ALWAYS_ON_POS ) & REG_PD_CTRL_BIST_ALWAYS_ON_MSK) #define REG_PD_CTRL_WAKE_EN_POS 29 #define REG_PD_CTRL_WAKE_EN_MSK (0x1ul << REG_PD_CTRL_WAKE_EN_POS) #define REG_PD_CTRL_WAKE_EN_SET(num) (((num) << REG_PD_CTRL_WAKE_EN_POS ) & REG_PD_CTRL_WAKE_EN_MSK) #define REG_PD_POWER_CC_COMP_EN_POS 0 #define REG_PD_POWER_CC_COMP_EN_MSK (0x1ul << REG_PD_POWER_CC_COMP_EN_POS) #define REG_PD_POWER_CC_COMP_EN_SET(num) (((num) << REG_PD_POWER_CC_COMP_EN_POS ) & REG_PD_POWER_CC_COMP_EN_MSK) #define REG_PD_RESET_SW_RESET_POS 0 #define REG_PD_RESET_SW_RESET_MSK (0x1ul << REG_PD_RESET_SW_RESET_POS) #define REG_PD_RESET_SW_RESET_SET(num) (((num) << REG_PD_RESET_SW_RESET_POS ) & REG_PD_RESET_SW_RESET_MSK) #define REG_PD_RESET_PD_RESET_POS 1 #define REG_PD_RESET_PD_RESET_MSK (0x1ul << REG_PD_RESET_PD_RESET_POS) #define REG_PD_RESET_PD_RESET_SET(num) (((num) << REG_PD_RESET_PD_RESET_POS ) & REG_PD_RESET_PD_RESET_MSK) #define REG_PD_INT_MASK_POS 0 #define REG_PD_INT_MASK_MSK (0x3FFFul << REG_PD_INT_MASK_POS) #define REG_PD_INT_MASK_SET(num) (((num) << REG_PD_INT_MASK_POS ) & REG_PD_INT_MASK_MSK) #define REG_PD_CFG_EN_RX_ROLLBACK_POS 1 #define REG_PD_CFG_EN_RX_ROLLBACK_MSK (0x1ul << REG_PD_CFG_EN_RX_ROLLBACK_POS) #define REG_PD_CFG_EN_RX_ROLLBACK_SET(num) (((num) << REG_PD_CFG_EN_RX_ROLLBACK_POS ) & REG_PD_CFG_EN_RX_ROLLBACK_MSK) #define REG_PD_CFG_DIS_FULLCHECK_POS 2 #define REG_PD_CFG_DIS_FULLCHECK_MSK (0x1ul << REG_PD_CFG_DIS_FULLCHECK_POS) #define REG_PD_CFG_DIS_FULLCHECK_SET(num) (((num) << REG_PD_CFG_DIS_FULLCHECK_POS ) & REG_PD_CFG_DIS_FULLCHECK_MSK) #define REG_PD_CFG_ACTIVITY_MODE_POS 3 #define REG_PD_CFG_ACTIVITY_MODE_MSK (0x3ul << REG_PD_CFG_ACTIVITY_MODE_POS) #define REG_PD_CFG_ACTIVITY_MODE_SET(num) (((num) << REG_PD_CFG_ACTIVITY_MODE_POS ) & REG_PD_CFG_ACTIVITY_MODE_MSK) #define REG_PD_CFG_FORCE_TXEN_POS 6 #define REG_PD_CFG_FORCE_TXEN_MSK (0x1ul << REG_PD_CFG_FORCE_TXEN_POS) #define REG_PD_CFG_FORCE_TXEN_SET(num) (((num) << REG_PD_CFG_FORCE_TXEN_POS ) & REG_PD_CFG_FORCE_TXEN_MSK) #define REG_PD_CFG_FORCE_RXEN_POS 7 #define REG_PD_CFG_FORCE_RXEN_MSK (0x1ul << REG_PD_CFG_FORCE_RXEN_POS) #define REG_PD_CFG_FORCE_RXEN_SET(num) (((num) << REG_PD_CFG_FORCE_RXEN_POS ) & REG_PD_CFG_FORCE_RXEN_MSK) #define REG_PD_CFG_DIG_TESTSEL_POS 12 #define REG_PD_CFG_DIG_TESTSEL_MSK (0xFul << REG_PD_CFG_DIG_TESTSEL_POS) #define REG_PD_CFG_DIG_TESTSEL_SET(num) (((num) << REG_PD_CFG_DIG_TESTSEL_POS ) & REG_PD_CFG_DIG_TESTSEL_MSK) #define REG_PD_CFG_TRANSMIT_TIMER_POS 19 #define REG_PD_CFG_TRANSMIT_TIMER_MSK (0x1ul << REG_PD_CFG_TRANSMIT_TIMER_POS) #define REG_PD_CFG_TRANSMIT_TIMER_SET(num) (((num) << REG_PD_CFG_TRANSMIT_TIMER_POS ) & REG_PD_CFG_TRANSMIT_TIMER_MSK) #define REG_PD_CFG_GAP_GCF_POS 20 #define REG_PD_CFG_GAP_GCF_MSK (0xFFFul << REG_PD_CFG_GAP_GCF_POS) #define REG_PD_CFG_GAP_GCF_SET(num) (((num) << REG_PD_CFG_GAP_GCF_POS ) & REG_PD_CFG_GAP_GCF_MSK) #endif /*__PD_DEFINE_H__*/