/**
 ******************************************************************************
 * @copyright Copyright (C), 2016-2022, ConvenientPower. Co., Ltd.
 * @file    drv_dma.h
 * @version 1.0
 * @author  qing.cheng
 * @date    2022-10-31
 * @brief   Header file of DRV_DMA_H module.
 ******************************************************************************
 */
#ifndef _DRV_DMA_H_
#define _DRV_DMA_H_

#include "core_comm.h"
#include "dma_define.h"
#include "dma1_define.h"
#include "adc_define.h"

#include "pd0_define.h"
#include "scp_define.h"
#include "ufcs_define.h"

#include "pd_define.h"
#include "scp1_define.h"
#include "ufcs1_define.h"



#define DMA_ADDR_WORD_SET(cfg_buf, addr)\
    do{\
        cfg_buf[0] = (uint32_t)(addr) & 0xFF;\
        cfg_buf[1] = ((uint32_t)(addr) >> 8) & 0xFF;\
        cfg_buf[2] = ((uint32_t)(addr) >> 16) & 0xFF;\
        cfg_buf[3] = ((uint32_t)(addr) >> 24) & 0xFF;\
    }while(0)

#define DMA_CFG_WORD_SET(cfg_buf, dma_buf_len, ctrl_byte)\
    do{\
        cfg_buf[0] = 0x00;\
        cfg_buf[1] = 0x00;\
        cfg_buf[2] = dma_buf_len;\
        cfg_buf[3] = ctrl_byte;\
    }while(0)

/**
 * @brief  disable dma0 chn
 * @note
 * @retval None
 */
#define drv_dma0_done_clr(chn_index)\
    do{\
         REG_DMA_DMA_DONE_CLR->bf.value = chn_index;\
        }while(0)

/*
  * @brief  drv_dma0_chn_enable
  * @param  chn_index
  * @note
  * @retval
*/
#define drv_dma0_chn_enable(chn_index)\
        do{\
            REG_DMA_CHL_ENABLE->bf.value = chn_index;\
        }while(0)


/*
  * @brief  drv_dma0_ctrl_base_ptr
  * @param  base_ptr
  * @note
  * @retval
*/
#define drv_dma0_ctrl_base_ptr(base_ptr)\
        do{\
             REG_DMA_CTRL_BASE_PTR->bf.value = base_ptr;\
        }while(0)



/*
  * @brief  drv_dma0_done_int_mask
  * @param  base_ptr
  * @note
  * @retval
*/
#define drv_dma0_done_int_mask(chn_index)\
    do{\
             REG_DMA_DMADONE_INT_MASK->bf.value = chn_index;\
        }while(0)


/*
  * @brief  drv_dma0_done_int_mask
  * @param  base_ptr
  * @note
  * @retval
*/
#define drv_dma0_done_int(chn_index)\
    do{\
             REG_DMA_DMADONE_INT->bf.value = chn_index;\
        }while(0)


/***************DMA1******************************/
/**
 * @brief  disable dma0 chn
 * @note
 * @retval None
 */
#define drv_dma1_done_clr(chn_index)\
    do{\
         REG_DMA1_DMA_DONE_CLR->bf.value = chn_index;\
        }while(0)
/*
  * @brief  drv_dma1_chn_enable
  * @param  chn_index
  * @note
  * @retval
*/
#define drv_dma1_chn_enable(chn_index)\
        do{\
            REG_DMA1_CHL_ENABLE->bf.value = chn_index;\
        }while(0)


/*
  * @brief  drv_dma1_ctrl_base_ptr
  * @param  base_ptr
  * @note
  * @retval
*/
#define drv_dma1_ctrl_base_ptr(base_ptr)\
        do{\
             REG_DMA1_CTRL_BASE_PTR->bf.value = base_ptr;\
        }while(0)



/*
  * @brief  drv_dma1_done_int_mask
  * @param  base_ptr
  * @note
  * @retval
*/
#define drv_dma1_done_int_mask(chn_index)\
    do{\
             REG_DMA1_DMADONE_INT_MASK->bf.value = chn_index;\
        }while(0)


/*
  * @brief  drv_dma1_done_int_mask
  * @param  base_ptr
  * @note
  * @retval
*/
#define drv_dma1_done_int(chn_index)\
    do{\
             REG_DMA1_DMADONE_INT->bf.value = chn_index;\
        }while(0)

#endif