/**
 ******************************************************************************
 * @copyright Copyright (C), 2016-2022, ConvenientPower. Co., Ltd.
 * @file    drv_vfcp_phy.h
 * @version 1.0
 * @author  qing.cheng
 * @date    2022-11-04
 * @brief   Header file of DRV_VFCP_PHY_H module.
 ******************************************************************************
 */
#ifndef _DRV_VFCP_PHY_H_
#define _DRV_VFCP_PHY_H_

#include "core_comm.h"
#include "vfcp_define.h"
/*
  * @brief  drv_vfcp_configure_rx_word
  * @param  word----cfg rx baud rate, valid when rx_train_en=0;     UART bdrate= clock frequncy / bdrate_div.
  *         eg: clock is 12Mhz, to get 115200 bps baudrate, bdrate_div= 12000000/115200= 104
  * @note
  * @retval null
*/
#define drv_vfcp_configure_rx_word(word)\
	do{\
			REG_VFCP_CONFIGURE_RX->word = word;\
	}while(0)

/*
  * @brief  drv_vfcp_config_rx_mask_clr
  * @param  clr
  * @note
  * @retval null
*/
#define drv_vfcp_config_rx_mask_clr( clr)\
	do{\
			REG_VFCP_CONFIGURE_RX->word &= ~(clr);\
	}while(0)
/*
  * @brief  drv_vfcp_config_rx_mask_set
  * @param  value
  * @note
  * @retval null
*/
#define drv_vfcp_config_rx_mask_set( value)\
	do{\
			REG_VFCP_CONFIGURE_RX->word |= value;\
	}while(0)

/*
  * @brief  drv_vfcp_configure_tx_word
  * @param  cfg tx baud rate, valid when bdr_sel=1;     UART bdrate= clock frequncy / bdrate_div
  *       eg: clock is 12Mhz, to get 115200 bps baudrate, bdrate_div= 12000000/115200= 104
  *       this configure can only be check at the time of TX enable or the reset time.
  * @note
  * @retval null
*/
#define drv_vfcp_configure_tx_word(word)\
do{\
    REG_VFCP_CONFIGURE_TX->word = word;\
}while(0)

/*
  * @brief  void drv_vfcp_config_tx_mask_clr(uint32_t clr)
  * @param  clr
  * @note
  * @retval null
*/
#define drv_vfcp_config_tx_mask_clr( clr)\
do{\
    REG_VFCP_CONFIGURE_TX->word &= ~(clr);\
}while(0)
/*
  * @brief  drv_vfcp_config_tx_mask_set
  * @param  value
  * @note
  * @retval null
*/
#define drv_vfcp_config_tx_mask_set( value)\
do{\
    REG_VFCP_CONFIGURE_TX->word |= value;\
}while(0)

/*
  * @brief  drv_vfcp_rxto_word
  * @param  word
  * Receiver timeout value, in terms of number of bits. accuracy error is half a bit.
    RTOR can be written on-the-fly. If the new value is lower than or equal to the counter, the
    RTOF flag is set
    This register is reserved and forced by hardware to ¡°0x00000000¡± when the Receiver
    timeout feature is not supported
  * @note
  * @retval null
*/
#define drv_vfcp_rxto_word( word)\
do{\
    REG_VFCP_RXTO->word = word;\
}while(0)

/*
  * @brief  drv_vfcp_ctrl_mask_clr
  * @param  value
  * @note
  * @retval null
*/
#define drv_vfcp_ctrl_mask_clr( clr)\
do{\
    REG_VFCP_CTRL->word &= ~(clr);\
}while(0)
/*
  * @brief  drv_vfcp_ctrl_mask_set
  * @param  value
  * @note
  * @retval null
*/
#define drv_vfcp_ctrl_mask_set( value)\
do{\
    REG_VFCP_CTRL->word |= value;\
}while(0)

/*
  * @brief  drv_vfcp_reset_word
  * @param  word (1=Reset just the VFCS phy logic for both the VFCS phy transmitter and receiver.)
  * @note
  * @retval null
*/
#define drv_vfcp_reset_word( word)\
do{\
    REG_VFCP_RESET->word = word;\
}while(0)
/*
  * @brief  drv_vfcp_tx_data_write
  * @param  data
  * @note
  * @retval null
*/
#define drv_vfcp_tx_data_write( data)\
do{\
    (REG_VFCP_TX_DAT->word = data);\
}while(0)
/*
  * @brief  drv_vfcp_tx_data_read
  * @param  null
  * @note
  * @retval tx dada
*/
#define drv_vfcp_tx_data_read() (REG_VFCP_TX_DAT->word & 0xff)

/*
  * @brief  drv_vfcp_rx_data_read
  * @param  null
  * @note
  * @retval rx dada
*/
#define drv_vfcp_rx_data_read() (REG_VFCP_RX_DAT->word & 0xff)

/*
  * @brief  drv_vfcp_status_read
  * @param  null
  * @note
  * @retval vfcp_status
*/
#define drv_vfcp_status_read()  (REG_VFCP_STATUS->word)

/*
  * @brief  drv_vfcp_int_tx_read
  * @param  null
  * @note
  * @retval fcp_int_tx
*/
#define drv_vfcp_int_tx_read() (REG_VFCP_INT_TX->word & 0xff)

/*
  * @brief  drv_vfcp_int_tx_mask_set
  * @param  value
  * @note
  * @retval null
*/
#define drv_vfcp_int_tx_mask_set( value)\
	do{\
			REG_VFCP_INT_TX_MASK->word |= value;\
	}while(0)

/*
  * @brief  drv_vfcp_int_tx_mask_clr
  * @param  clr
  * @note
  * @retval null
*/
#define drv_vfcp_int_tx_mask_clr( clr)\
	do{\
			REG_VFCP_INT_TX_MASK->word &= ~(clr);\
	}while(0)

/*
  * @brief  drv_vfcp_int_rx_read
  * @param  null
  * @note
  * @retval fcp_int_rx data
*/
#define drv_vfcp_int_rx_read() (REG_VFCP_INT_RX->word & 0xff)

/*
  * @brief  drv_vfcp_int_rx_mask_set
  * @param  value
  * @note
  * @retval null
*/
#define drv_vfcp_int_rx_mask_set( value)\
do{\
    REG_VFCP_INT_RX_MASK->word |= value;\
}while(0)

/*
  * @brief  drv_vfcp_int_rx_mask_clr
  * @param  clr
  * @note
  * @retval null
*/
#define drv_vfcp_int_rx_mask_clr( clr)\
do{\
    REG_VFCP_INT_RX_MASK->word &= ~(clr);\
}while(0)

/*
  * @brief  drv_vfdp_fsm_dbg_read
  * @param  null
  * @note
  * @retval vfdp_fsm_dbg data
*/
#define drv_vfdp_fsm_dbg_read() (REG_VFCP_FSM_DBG->word)
/*
  * @brief  drv_vfcp_test_mode_word
  * @param  word
  * @note
  * @retval null
*/
#define drv_vfcp_test_mode_word( word)\
do{\
    REG_VFCP_TST_MODE->word = word;\
}while(0)



#endif