/**
 ******************************************************************************
 * @copyright Copyright (C), 2016-2022, ConvenientPower. Co., Ltd.
 * @file    ufcs_phy.h
 * @version 1.0
 * @author  qing.cheng
 * @date    2022-12-02
 * @brief   Header file of UFCS_PHY_H module.
 ******************************************************************************
 */

#ifndef __UFCS_PHY_H__
#define __UFCS_PHY_H__
#include "drv_comm.h"
#include "comp_dma.h"
#include "comp_config.h"
#include "ufcs_app.h"
//#define UFCS_FIFO_MAXLEN 16

#define UFCS_DPDN_FUNC 1
#define UFCS_GPIO_FUNC 3

#define DP1_PIN  2
#define DN1_PIN  3
#define DP2_PIN  4
#define DN2_PIN  5

typedef enum
{
    UFCS_BAUD_RATE_115200 = 0,
    UFCS_BAUD_RATE_57600,
    UFCS_BAUD_RATE_38400,
    UFCS_BAUD_RATE_MAX
} ufcs_baud_rate_e;
/*
  * @brief  ufcs_dn_level_low
  * @param  port
  * @note  null
  * @retval 1: dn <0.6V
*/

#define ufcs_dn_level_low(port) \
        drv_dpdn_dn_comp_0p6v_get(port)

/*
  * @brief  ufcs_phy_ctrl_tx_enable
  * @param  port
  * @param   en
  * @note  null
  * @retval null
*/
__forceinline void ufcs_phy_ctrl_tx_enable(uint8_t port, bool en)
{
    if(port == 0)
    {
        drv_ufcs0_ctrl_tx_enable(en);
    }
    else
    {
        drv_ufcs1_ctrl_tx_enable(en);
    }
}

/*
  * @brief  ufcs_phy_ctrl_rx_enable
  * @param  port
  * @param   en
  * @note  null
  * @retval null
*/
__forceinline void ufcs_phy_ctrl_rx_enable(uint8_t port, bool en)
{
    if(port == 0)
    {
        drv_ufcs0_ctrl_rx_enable(en);
    }
    else
    {
        drv_ufcs1_ctrl_rx_enable(en);
    }
}

/*
  * @brief  ufcs_phy_ctrl_rx_stop_en
  * @param  port
  * @param   en 1: hw clear rx_enable at the time of rxpkt_end, software set rx_enable; 0: sw control rx_enable directly
  * @note  null
  * @retval null
*/
__forceinline void ufcs_phy_ctrl_rx_stop_en(uint8_t port, bool en)
{
    if(port == 0)
    {
        drv_ufcs0_ctrl_rx_stop_en(en);
    }
    else
    {
        drv_ufcs1_ctrl_rx_stop_en(en);
    }
}

/*
  * @brief  ufcs_phy_ctrl_hw_reset_cable
  * @param  port
  * @param   en 1:  send cable hardware reset command, only valid when the &quot;txpkt_end&quot; is high level, set by software, clear by hw;
  * @note  null
  * @retval null
*/
__forceinline void ufcs_phy_ctrl_hw_reset_cable(uint8_t port, bool en)
{
    if(port == 0)
    {
        drv_ufcs0_ctrl_hw_reset_cable(en);
    }
    else
    {
        drv_ufcs1_ctrl_hw_reset_cable(en);
    }
}

/*
  * @brief  ufcs_phy_ctrl_hw_reset_snk
  * @param  port
  * @param   en 1:  send sink hardware reset command, only valid when the &quot;txpkt_end&quot; is high level, if tx packet not end status, miss this command
  * @note  null
  * @retval null
*/
__forceinline void ufcs_phy_ctrl_hw_reset_tx(uint8_t port, bool en)
{
    if(port == 0)
    {
        drv_ufcs0_ctrl_hw_reset_tx(en);
    }
    else
    {
        drv_ufcs1_ctrl_hw_reset_tx(en);
    }
}

/*
  * @brief  ufcs_phy_reset_logic
  * @param  port
  * @note  null
  * @retval null
*/
__forceinline void ufcs_phy_reset_logic(uint8_t port)
{
    if(port == 0)
    {
        drv_ufcs0_reset_logic();
    }
    else
    {
        drv_ufcs1_reset_logic();
    }
}

/*
  * @brief  ufcs_phy_reset_all
  * @param  port
  * @note  null
  * @retval null
*/
__forceinline void ufcs_phy_reset_all(uint8_t port)
{
    if(port == 0)
    {
        drv_ufcs0_reset_all();
    }
    else
    {
        drv_ufcs1_reset_all();
    }
}

/*
  * @brief  ufcs_phy_reset_all
  * @param  port
  * borate_num://0:115200 1:57600 2:38400 3:19200
  * @note  null
  * @retval null
*/
__forceinline void ufcs_phy_bdrate_tx_set(uint8_t port, uint16_t borate_num)
{
    if(port == 0)
    {
        drv_ufcs0_bdrate_tx(borate_num);
    }
    else
    {
        drv_ufcs1_bdrate_tx(borate_num);
    }
}

/*
  * @brief  ufcs_phy_reset_all
  * @param  port
  * @note  null
  * @retval borate_num
*/
__forceinline uint16_t  ufcs_phy_bdrate_rx_get(uint8_t port)
{
    if(port == 0)
    {
        return  drv_ufcs0_bdrate_rx();
    }
    else
    {
        return  drv_ufcs1_bdrate_rx();
    }
}

/*
  * @brief  ufcs_phy_reset_all
  * @param  port
  * borate_num:0: 115200; 1:57600; 2:38400; 3: 19200bps
  * @note  null
  * @retval null
*/
__forceinline void ufcs_phy_txpkt_len(uint8_t port, uint16_t len)
{
    if(port == 0)
    {
        drv_ufcs0_txpkt_len(len);
    }
    else
    {
        drv_ufcs1_txpkt_len(len);
    }
}

//usb_dn pulse counter enable

/*
  * @brief  ufcs_dn_val_get
  * @param  port
  * @note  null
  * @retval data32 val
*/
__forceinline uint32_t ufcs_dn_val_get(uint8_t port)
{
    if(port == 0)
    {
        return drv_ufcs0_get_pwd1_val();
    }
    else
    {
        return drv_ufcs1_get_pwd3_val();
    }
}


/*
  * @brief  ufcs_dn_val_get
  * @param  port
  * @note  null
  * @retval null
*/
__forceinline uint8_t ufcs_dpdn_short_staus_ge_ok(uint8_t port)
{
    return drv_dpdn_short_staus_get(port);
}

/*
  * @brief  ufcs_phy_get_rx_int
  * @param  port
  * @note  null
  * @retval rx int flag state
*/
__forceinline uint32_t ufcs_phy_get_rx_int(uint8_t port)
{
    if(port == 0)
    {
        return drv_ufcs0_get_rx_int();
    }
    else
    {
        return drv_ufcs1_get_rx_int();
    }
}

/*
  * @brief  ufcs_phy_get_tx_int
  * @param  port
  * @note  null
  * @retval tx int flag state
*/
__forceinline uint32_t ufcs_phy_get_tx_int(uint8_t port)
{
    if(port == 0)
    {
        return drv_ufcs0_get_tx_int();
    }
    else
    {
        return drv_ufcs1_get_tx_int();
    }
}
/*
  * @brief  ufcs_phy_rx_int_mask
  * @param  port
  * @param  val
  * @note  null
  * @retval null
*/
__forceinline void ufcs_phy_rx_int_mask(uint8_t port, uint32_t val)
{
    if(port == 0)
    {
        drv_ufcs0_rx_int_mask(val);
    }
    else
    {
        drv_ufcs1_rx_int_mask(val);
    }
}
/*
  * @brief  ufcs_phy_rx_int_clr
  * @param  port
  * @param  val
  * @note  null
  * @retval null
*/
__forceinline void ufcs_phy_rx_int_clr(uint8_t port, uint32_t val)
{
    if(port == 0)
    {
        drv_ufcs0_rx_int_clr(val);
    }
    else
    {
        drv_ufcs1_rx_int_clr(val);
    }
}

/*
  * @brief  ufcs_phy_tx_int_mask
  * @param  port
  * @param  val
  * @note  null
  * @retval null
*/
__forceinline void ufcs_phy_tx_int_mask(uint8_t port, uint32_t val)
{
    if(port == 0)
    {
        drv_ufcs0_tx_int_mask(val);
    }
    else
    {
        drv_ufcs1_tx_int_mask(val);
    }
}

/*
  * @brief  ufcs_phy_tx_int_clr
  * @param  port
  * @param  val
  * @note  null
  * @retval null
*/
__forceinline void ufcs_phy_tx_int_clr(uint8_t port, uint32_t val)
{
    if(port == 0)
    {
        drv_ufcs0_tx_int_clr(val);
    }
    else
    {
        drv_ufcs1_tx_int_clr(val);
    }
}

/*
  * @brief  ufcs_dma_done_clr
  * @param  port
  * @param  chn_index
  * @note  null
  * @retval null
*/
__forceinline void ufcs_dma_done_clr(uint8_t port, uint8_t chn_index)
{
    if(port == 0)
    {
        drv_dma0_done_clr(chn_index);
    }
    else
    {
        drv_dma1_done_clr(chn_index);
    }
}

/*
  * @brief  ufcs_rx_hard_reset_val_set
  * @param  port
  * @param  chn_index
  * @note  null
  * @retval null
*/
__forceinline void ufcs_rx_hard_reset_val_set(uint8_t port, uint8_t chn_index)
{
    if(port == 0)
    {
        drv_ufcs0_rx_hard_reset_val_set(chn_index);
    }
    else
    {
        drv_ufcs1_rx_hard_reset_val_set(chn_index);
    }
}

/*
  * @brief ufcs_phy_callback_init
  * @param  ufcs_param
  * @note
  * @retval NULL
*/
void ufcs_phy_callback_init(uint8_t port, ufcs_param_s *ufcs_param);

/*
  * @brief  ufcs_phy_ctrl_stop_src_tx
  * @param  port
  * @param
  *
  * //all the following condition is met, then the stop command is not effect
    //1 tx packet is processing
    //2. hwrst is processing
  * @retval null
*/
void ufcs_phy_ctrl_stop_src_tx(uint8_t port, uint8_t en);

/*
  * @brief ufcs_handshake_init
  * @param  uint8_t port
  * @param  NULL
  * @note
  * @retval NULL
*/
void ufcs_handshake_init(uint8_t port);

/*
  * @brief ufcs_handshake_disable
  * @param  uint8_t port
  * @param  NULL
  * @note
  * @retval NULL
*/
void ufcs_handshake_disable(uint8_t port);

/*
  * @brief ufcs_phy_reg_config
  * @param  uint8_t port
  * @param  ufcs_param
  * @note
  * @retval NULL
*/
void ufcs_phy_reg_config(uint8_t port, ufcs_param_s *ufcs_param);

/*
  * @brief ufcs_phy_reg_config
  * @param  uint8_t port
  * @note
  * @retval NULL
*/
void config_ufcs_port(uint8_t port);

/*
  * @brief send_ufcs_pkt
  * @param  uint8_t port
  * @param  dma_addr
  * @param  ufcs_assist
  * @note
  * @retval NULL
*/
void send_ufcs_pkt(uint8_t port, uint32_t dma_addr, ufcs_assist_s *ufcs_assist);

/*
  * @brief ufcs_phy_send_cable_reset
  * @param  NULL
  * @note
  * @retval NULL
*/
void ufcs_phy_send_cable_reset(uint8_t port);


/*
  * @brief ufcs_phy_send_hard_reset
  * @param  NULL
  * @note
  * @retval NULL
*/
void ufcs_phy_send_hard_reset(uint8_t port);


/*
  * @brief  ufcs_phy_exit_ufcs_mode
  * @param  NULL
  * @note
  * @retval NULL
*/
void ufcs_phy_exit_ufcs_mode(uint8_t port);

/*
  * @brief  ufcs_ping_follow_baudrate
  * @param  ufcs_param
  * @note
  * @retval NULL
*/
void ufcs_ping_follow_baudrate(uint8_t port, ufcs_param_s *ufcs_param);
#endif