#ifndef __DAC_CTRL_DEFINE_H__ #define __DAC_CTRL_DEFINE_H__ //----------------------------------------------------------------------------- // dac_ctrl registers definition //----------------------------------------------------------------------------- #pragma anon_unions //----------------------------------------------------------------------------- // registers structures typedef struct { //dac output target vaule //2.3v/4096=1lsb uint32_t target:12; uint32_t reserved_15_12:4; //ramp up slewrate selection, time unit is micro seconde. step is 1us. //0: 0us; 1: 1us; …..255: 255us; uint32_t slewrate:8; //dac output enable uint32_t enable:1; uint32_t reserved_31_25:7; } REG_dac_ctrl_cv0_cfg_bitfiled_TypeDef; typedef struct { union { __IO REG_dac_ctrl_cv0_cfg_bitfiled_TypeDef bf;//bitfiled __IO uint32_t word; }; } REG_dac_ctrl_cv0_cfg_TypeDef; typedef struct { //current dac value uint32_t out:12; uint32_t reserved_31_12:20; } REG_dac_ctrl_cv0_val_bitfiled_TypeDef; typedef struct { union { __IO REG_dac_ctrl_cv0_val_bitfiled_TypeDef bf;//bitfiled __IO uint32_t word; }; } REG_dac_ctrl_cv0_val_TypeDef; typedef struct { //dac output target vaule //2.3v/4096=1lsb uint32_t target:12; uint32_t reserved_15_12:4; //ramp up slewrate selection, time unit is micro seconde. step is 1us. //0: 0us; 1: 1us; …..255: 255us; uint32_t slewrate:8; //dac output enable uint32_t enable:1; uint32_t reserved_31_25:7; } REG_dac_ctrl_cv1_cfg_bitfiled_TypeDef; typedef struct { union { __IO REG_dac_ctrl_cv1_cfg_bitfiled_TypeDef bf;//bitfiled __IO uint32_t word; }; } REG_dac_ctrl_cv1_cfg_TypeDef; typedef struct { //current dac value uint32_t out:12; uint32_t reserved_31_12:20; } REG_dac_ctrl_cv1_val_bitfiled_TypeDef; typedef struct { union { __IO REG_dac_ctrl_cv1_val_bitfiled_TypeDef bf;//bitfiled __IO uint32_t word; }; } REG_dac_ctrl_cv1_val_TypeDef; typedef struct { //dac output target vaule //2.3v/63=1lsb uint32_t target:6; uint32_t reserved_15_6:10; //ramp up slewrate selection, time unit is micro seconde. step is 1us. //0: 0us; 1: 1us; …..255: 255us; uint32_t slewrate:8; //dac output enable uint32_t enable:1; uint32_t reserved_31_25:7; } REG_dac_ctrl_cv2_cfg_bitfiled_TypeDef; typedef struct { union { __IO REG_dac_ctrl_cv2_cfg_bitfiled_TypeDef bf;//bitfiled __IO uint32_t word; }; } REG_dac_ctrl_cv2_cfg_TypeDef; typedef struct { //current dac value uint32_t out:6; uint32_t reserved_31_6:26; } REG_dac_ctrl_cv2_val_bitfiled_TypeDef; typedef struct { union { __IO REG_dac_ctrl_cv2_val_bitfiled_TypeDef bf;//bitfiled __IO uint32_t word; }; } REG_dac_ctrl_cv2_val_TypeDef; typedef struct { //dac output target vaule //2.3v/2048=1lsb uint32_t target:11; uint32_t reserved_15_11:5; //ramp up slewrate selection, time unit is micro seconde. //0: 0us; 1: 1us; …..255: 255us; uint32_t slewrate:8; //dac output enable uint32_t enable:1; uint32_t reserved_31_25:7; } REG_dac_ctrl_cc0_cfg_bitfiled_TypeDef; typedef struct { union { __IO REG_dac_ctrl_cc0_cfg_bitfiled_TypeDef bf;//bitfiled __IO uint32_t word; }; } REG_dac_ctrl_cc0_cfg_TypeDef; typedef struct { //current dac value uint32_t out:11; uint32_t reserved_31_11:21; } REG_dac_ctrl_cc0_val_bitfiled_TypeDef; typedef struct { union { __IO REG_dac_ctrl_cc0_val_bitfiled_TypeDef bf;//bitfiled __IO uint32_t word; }; } REG_dac_ctrl_cc0_val_TypeDef; typedef struct { //dac output target vaule //2.3v/2048=1lsb uint32_t target:11; uint32_t reserved_15_11:5; //ramp up slewrate selection, time unit is micro seconde. //0: 0us; 1: 1us; …..255: 255us; uint32_t slewrate:8; //dac output enable uint32_t enable:1; uint32_t reserved_31_25:7; } REG_dac_ctrl_cc1_cfg_bitfiled_TypeDef; typedef struct { union { __IO REG_dac_ctrl_cc1_cfg_bitfiled_TypeDef bf;//bitfiled __IO uint32_t word; }; } REG_dac_ctrl_cc1_cfg_TypeDef; typedef struct { //current dac value uint32_t out:11; uint32_t reserved_31_11:21; } REG_dac_ctrl_cc1_val_bitfiled_TypeDef; typedef struct { union { __IO REG_dac_ctrl_cc1_val_bitfiled_TypeDef bf;//bitfiled __IO uint32_t word; }; } REG_dac_ctrl_cc1_val_TypeDef; //----------------------------------------------------------------------------- // memory map #define REG_DAC_CTRL_CV0_CFG_BASE 0x40009000 #define REG_DAC_CTRL_CV0_VAL_BASE 0x40009004 #define REG_DAC_CTRL_CV1_CFG_BASE 0x40009008 #define REG_DAC_CTRL_CV1_VAL_BASE 0x4000900C #define REG_DAC_CTRL_CV2_CFG_BASE 0x40009010 #define REG_DAC_CTRL_CV2_VAL_BASE 0x40009014 #define REG_DAC_CTRL_CC0_CFG_BASE 0x40009100 #define REG_DAC_CTRL_CC0_VAL_BASE 0x40009104 #define REG_DAC_CTRL_CC1_CFG_BASE 0x40009108 #define REG_DAC_CTRL_CC1_VAL_BASE 0x4000910C //----------------------------------------------------------------------------- // declaration #define REG_DAC_CTRL_CV0_CFG ((REG_dac_ctrl_cv0_cfg_TypeDef *) REG_DAC_CTRL_CV0_CFG_BASE ) #define REG_DAC_CTRL_CV0_VAL ((REG_dac_ctrl_cv0_val_TypeDef *) REG_DAC_CTRL_CV0_VAL_BASE ) #define REG_DAC_CTRL_CV1_CFG ((REG_dac_ctrl_cv1_cfg_TypeDef *) REG_DAC_CTRL_CV1_CFG_BASE ) #define REG_DAC_CTRL_CV1_VAL ((REG_dac_ctrl_cv1_val_TypeDef *) REG_DAC_CTRL_CV1_VAL_BASE ) #define REG_DAC_CTRL_CV2_CFG ((REG_dac_ctrl_cv2_cfg_TypeDef *) REG_DAC_CTRL_CV2_CFG_BASE ) #define REG_DAC_CTRL_CV2_VAL ((REG_dac_ctrl_cv2_val_TypeDef *) REG_DAC_CTRL_CV2_VAL_BASE ) #define REG_DAC_CTRL_CC0_CFG ((REG_dac_ctrl_cc0_cfg_TypeDef *) REG_DAC_CTRL_CC0_CFG_BASE ) #define REG_DAC_CTRL_CC0_VAL ((REG_dac_ctrl_cc0_val_TypeDef *) REG_DAC_CTRL_CC0_VAL_BASE ) #define REG_DAC_CTRL_CC1_CFG ((REG_dac_ctrl_cc1_cfg_TypeDef *) REG_DAC_CTRL_CC1_CFG_BASE ) #define REG_DAC_CTRL_CC1_VAL ((REG_dac_ctrl_cc1_val_TypeDef *) REG_DAC_CTRL_CC1_VAL_BASE ) //----------------------------------------------------------------------------- // set #define REG_DAC_CTRL_CV0_CFG_TARGET_POS 0 #define REG_DAC_CTRL_CV0_CFG_TARGET_MSK (0xFFFul << REG_DAC_CTRL_CV0_CFG_TARGET_POS) #define REG_DAC_CTRL_CV0_CFG_TARGET_SET(num) (((num) << REG_DAC_CTRL_CV0_CFG_TARGET_POS ) & REG_DAC_CTRL_CV0_CFG_TARGET_MSK) #define REG_DAC_CTRL_CV0_CFG_SLEWRATE_POS 16 #define REG_DAC_CTRL_CV0_CFG_SLEWRATE_MSK (0xFFul << REG_DAC_CTRL_CV0_CFG_SLEWRATE_POS) #define REG_DAC_CTRL_CV0_CFG_SLEWRATE_SET(num) (((num) << REG_DAC_CTRL_CV0_CFG_SLEWRATE_POS ) & REG_DAC_CTRL_CV0_CFG_SLEWRATE_MSK) #define REG_DAC_CTRL_CV0_CFG_ENABLE_POS 24 #define REG_DAC_CTRL_CV0_CFG_ENABLE_MSK (0x1ul << REG_DAC_CTRL_CV0_CFG_ENABLE_POS) #define REG_DAC_CTRL_CV0_CFG_ENABLE_SET(num) (((num) << REG_DAC_CTRL_CV0_CFG_ENABLE_POS ) & REG_DAC_CTRL_CV0_CFG_ENABLE_MSK) #define REG_DAC_CTRL_CV1_CFG_TARGET_POS 0 #define REG_DAC_CTRL_CV1_CFG_TARGET_MSK (0xFFFul << REG_DAC_CTRL_CV1_CFG_TARGET_POS) #define REG_DAC_CTRL_CV1_CFG_TARGET_SET(num) (((num) << REG_DAC_CTRL_CV1_CFG_TARGET_POS ) & REG_DAC_CTRL_CV1_CFG_TARGET_MSK) #define REG_DAC_CTRL_CV1_CFG_SLEWRATE_POS 16 #define REG_DAC_CTRL_CV1_CFG_SLEWRATE_MSK (0xFFul << REG_DAC_CTRL_CV1_CFG_SLEWRATE_POS) #define REG_DAC_CTRL_CV1_CFG_SLEWRATE_SET(num) (((num) << REG_DAC_CTRL_CV1_CFG_SLEWRATE_POS ) & REG_DAC_CTRL_CV1_CFG_SLEWRATE_MSK) #define REG_DAC_CTRL_CV1_CFG_ENABLE_POS 24 #define REG_DAC_CTRL_CV1_CFG_ENABLE_MSK (0x1ul << REG_DAC_CTRL_CV1_CFG_ENABLE_POS) #define REG_DAC_CTRL_CV1_CFG_ENABLE_SET(num) (((num) << REG_DAC_CTRL_CV1_CFG_ENABLE_POS ) & REG_DAC_CTRL_CV1_CFG_ENABLE_MSK) #define REG_DAC_CTRL_CV2_CFG_TARGET_POS 0 #define REG_DAC_CTRL_CV2_CFG_TARGET_MSK (0x3Ful << REG_DAC_CTRL_CV2_CFG_TARGET_POS) #define REG_DAC_CTRL_CV2_CFG_TARGET_SET(num) (((num) << REG_DAC_CTRL_CV2_CFG_TARGET_POS ) & REG_DAC_CTRL_CV2_CFG_TARGET_MSK) #define REG_DAC_CTRL_CV2_CFG_SLEWRATE_POS 16 #define REG_DAC_CTRL_CV2_CFG_SLEWRATE_MSK (0xFFul << REG_DAC_CTRL_CV2_CFG_SLEWRATE_POS) #define REG_DAC_CTRL_CV2_CFG_SLEWRATE_SET(num) (((num) << REG_DAC_CTRL_CV2_CFG_SLEWRATE_POS ) & REG_DAC_CTRL_CV2_CFG_SLEWRATE_MSK) #define REG_DAC_CTRL_CV2_CFG_ENABLE_POS 24 #define REG_DAC_CTRL_CV2_CFG_ENABLE_MSK (0x1ul << REG_DAC_CTRL_CV2_CFG_ENABLE_POS) #define REG_DAC_CTRL_CV2_CFG_ENABLE_SET(num) (((num) << REG_DAC_CTRL_CV2_CFG_ENABLE_POS ) & REG_DAC_CTRL_CV2_CFG_ENABLE_MSK) #define REG_DAC_CTRL_CC0_CFG_TARGET_POS 0 #define REG_DAC_CTRL_CC0_CFG_TARGET_MSK (0x7FFul << REG_DAC_CTRL_CC0_CFG_TARGET_POS) #define REG_DAC_CTRL_CC0_CFG_TARGET_SET(num) (((num) << REG_DAC_CTRL_CC0_CFG_TARGET_POS ) & REG_DAC_CTRL_CC0_CFG_TARGET_MSK) #define REG_DAC_CTRL_CC0_CFG_SLEWRATE_POS 16 #define REG_DAC_CTRL_CC0_CFG_SLEWRATE_MSK (0xFFul << REG_DAC_CTRL_CC0_CFG_SLEWRATE_POS) #define REG_DAC_CTRL_CC0_CFG_SLEWRATE_SET(num) (((num) << REG_DAC_CTRL_CC0_CFG_SLEWRATE_POS ) & REG_DAC_CTRL_CC0_CFG_SLEWRATE_MSK) #define REG_DAC_CTRL_CC0_CFG_ENABLE_POS 24 #define REG_DAC_CTRL_CC0_CFG_ENABLE_MSK (0x1ul << REG_DAC_CTRL_CC0_CFG_ENABLE_POS) #define REG_DAC_CTRL_CC0_CFG_ENABLE_SET(num) (((num) << REG_DAC_CTRL_CC0_CFG_ENABLE_POS ) & REG_DAC_CTRL_CC0_CFG_ENABLE_MSK) #define REG_DAC_CTRL_CC1_CFG_TARGET_POS 0 #define REG_DAC_CTRL_CC1_CFG_TARGET_MSK (0x7FFul << REG_DAC_CTRL_CC1_CFG_TARGET_POS) #define REG_DAC_CTRL_CC1_CFG_TARGET_SET(num) (((num) << REG_DAC_CTRL_CC1_CFG_TARGET_POS ) & REG_DAC_CTRL_CC1_CFG_TARGET_MSK) #define REG_DAC_CTRL_CC1_CFG_SLEWRATE_POS 16 #define REG_DAC_CTRL_CC1_CFG_SLEWRATE_MSK (0xFFul << REG_DAC_CTRL_CC1_CFG_SLEWRATE_POS) #define REG_DAC_CTRL_CC1_CFG_SLEWRATE_SET(num) (((num) << REG_DAC_CTRL_CC1_CFG_SLEWRATE_POS ) & REG_DAC_CTRL_CC1_CFG_SLEWRATE_MSK) #define REG_DAC_CTRL_CC1_CFG_ENABLE_POS 24 #define REG_DAC_CTRL_CC1_CFG_ENABLE_MSK (0x1ul << REG_DAC_CTRL_CC1_CFG_ENABLE_POS) #define REG_DAC_CTRL_CC1_CFG_ENABLE_SET(num) (((num) << REG_DAC_CTRL_CC1_CFG_ENABLE_POS ) & REG_DAC_CTRL_CC1_CFG_ENABLE_MSK) #endif /*__DAC_CTRL_DEFINE_H__*/