#ifndef __EXTINT_DEFINE_H__ #define __EXTINT_DEFINE_H__ //----------------------------------------------------------------------------- // extint registers definition //----------------------------------------------------------------------------- #pragma anon_unions //----------------------------------------------------------------------------- // registers structures typedef struct { //write 1 to clear interrupt uint32_t clr:1; uint32_t reserved_7_1:7; //0: disable interrupt uint32_t en:1; //1: mask interrupt uint32_t mask:1; uint32_t reserved_15_10:6; //interrupt value after latch uint32_t val:1; //interrupt source value uint32_t stat:1; uint32_t reserved_31_18:14; } REG_extint_pwd0_int_bitfiled_TypeDef; typedef struct { union { __IO REG_extint_pwd0_int_bitfiled_TypeDef bf;//bitfiled __IO uint32_t word; }; } REG_extint_pwd0_int_TypeDef; typedef struct { //write 1 to clear interrupt uint32_t clr:1; uint32_t reserved_7_1:7; //0: disable interrupt uint32_t en:1; //1: mask interrupt uint32_t mask:1; uint32_t reserved_15_10:6; //interrupt value after latch uint32_t val:1; //interrupt source value uint32_t stat:1; uint32_t reserved_31_18:14; } REG_extint_pwd1_int_bitfiled_TypeDef; typedef struct { union { __IO REG_extint_pwd1_int_bitfiled_TypeDef bf;//bitfiled __IO uint32_t word; }; } REG_extint_pwd1_int_TypeDef; typedef struct { //write 1 to clear interrupt uint32_t clr:1; uint32_t reserved_7_1:7; //0: disable interrupt uint32_t en:1; //1: mask interrupt uint32_t mask:1; uint32_t reserved_15_10:6; //interrupt value after latch uint32_t val:1; //interrupt source value uint32_t stat:1; uint32_t reserved_31_18:14; } REG_extint_pwd2_int_bitfiled_TypeDef; typedef struct { union { __IO REG_extint_pwd2_int_bitfiled_TypeDef bf;//bitfiled __IO uint32_t word; }; } REG_extint_pwd2_int_TypeDef; typedef struct { //write 1 to clear interrupt uint32_t clr:1; uint32_t reserved_7_1:7; //0: disable interrupt uint32_t en:1; //1: mask interrupt uint32_t mask:1; uint32_t reserved_15_10:6; //interrupt value after latch uint32_t val:1; //interrupt source value uint32_t stat:1; uint32_t reserved_31_18:14; } REG_extint_pwd3_int_bitfiled_TypeDef; typedef struct { union { __IO REG_extint_pwd3_int_bitfiled_TypeDef bf;//bitfiled __IO uint32_t word; }; } REG_extint_pwd3_int_TypeDef; typedef struct { //write 1 to clear interrupt uint32_t clr:1; uint32_t reserved_7_1:7; //0: disable interrupt uint32_t en:1; //1: mask interrupt uint32_t mask:1; uint32_t reserved_15_10:6; //interrupt value after latch uint32_t val:1; //interrupt source value uint32_t stat:1; uint32_t reserved_31_18:14; } REG_extint_i2c_func0_int_bitfiled_TypeDef; typedef struct { union { __IO REG_extint_i2c_func0_int_bitfiled_TypeDef bf;//bitfiled __IO uint32_t word; }; } REG_extint_i2c_func0_int_TypeDef; typedef struct { //write 1 to clear interrupt uint32_t clr:1; uint32_t reserved_7_1:7; //0: disable interrupt uint32_t en:1; //1: mask interrupt uint32_t mask:1; uint32_t reserved_15_10:6; //interrupt value after latch uint32_t val:1; //interrupt source value uint32_t stat:1; uint32_t reserved_31_18:14; } REG_extint_i2c_func1_int_bitfiled_TypeDef; typedef struct { union { __IO REG_extint_i2c_func1_int_bitfiled_TypeDef bf;//bitfiled __IO uint32_t word; }; } REG_extint_i2c_func1_int_TypeDef; typedef struct { //write 1 to clear interrupt uint32_t clr:1; uint32_t reserved_7_1:7; //0: disable interrupt uint32_t en:1; //1: mask interrupt uint32_t mask:1; uint32_t reserved_15_10:6; //interrupt value after latch uint32_t val:1; //interrupt source value uint32_t stat:1; uint32_t reserved_31_18:14; } REG_extint_vd_ls_comp_chg_int_bitfiled_TypeDef; typedef struct { union { __IO REG_extint_vd_ls_comp_chg_int_bitfiled_TypeDef bf;//bitfiled __IO uint32_t word; }; } REG_extint_vd_ls_comp_chg_int_TypeDef; typedef struct { //write 1 to clear interrupt uint32_t clr:1; uint32_t reserved_7_1:7; //0: disable interrupt uint32_t en:1; //1: mask interrupt uint32_t mask:1; uint32_t reserved_15_10:6; //interrupt value after latch uint32_t val:1; //interrupt source value uint32_t stat:1; uint32_t reserved_23_18:6; //interrupt trigger mode 0:rising 1:falling 2:low level 3:high level uint32_t mode:2; uint32_t reserved_31_26:6; } REG_extint_pd0_ccx_stat_int_bitfiled_TypeDef; typedef struct { union { __IO REG_extint_pd0_ccx_stat_int_bitfiled_TypeDef bf;//bitfiled __IO uint32_t word; }; } REG_extint_pd0_ccx_stat_int_TypeDef; typedef struct { //write 1 to clear interrupt uint32_t clr:1; uint32_t reserved_7_1:7; //0: disable interrupt uint32_t en:1; //1: mask interrupt uint32_t mask:1; uint32_t reserved_15_10:6; //interrupt value after latch uint32_t val:1; //interrupt source value uint32_t stat:1; uint32_t reserved_23_18:6; //interrupt trigger mode 0:rising 1:falling 2:low level 3:high level uint32_t mode:2; uint32_t reserved_31_26:6; } REG_extint_pd1_ccx_stat_int_bitfiled_TypeDef; typedef struct { union { __IO REG_extint_pd1_ccx_stat_int_bitfiled_TypeDef bf;//bitfiled __IO uint32_t word; }; } REG_extint_pd1_ccx_stat_int_TypeDef; typedef struct { //write 1 to clear interrupt uint32_t clr:1; uint32_t reserved_7_1:7; //0: disable interrupt uint32_t en:1; //1: mask interrupt uint32_t mask:1; uint32_t reserved_15_10:6; //interrupt value after latch uint32_t val:1; //interrupt source value uint32_t stat:1; uint32_t reserved_23_18:6; //interrupt trigger mode 0:rising 1:falling 2:low level 3:high level uint32_t mode:2; uint32_t reserved_31_26:6; } REG_extint_pd0_vwake_int_bitfiled_TypeDef; typedef struct { union { __IO REG_extint_pd0_vwake_int_bitfiled_TypeDef bf;//bitfiled __IO uint32_t word; }; } REG_extint_pd0_vwake_int_TypeDef; typedef struct { //write 1 to clear interrupt uint32_t clr:1; uint32_t reserved_7_1:7; //0: disable interrupt uint32_t en:1; //1: mask interrupt uint32_t mask:1; uint32_t reserved_15_10:6; //interrupt value after latch uint32_t val:1; //interrupt source value uint32_t stat:1; uint32_t reserved_23_18:6; //interrupt trigger mode 0:rising 1:falling 2:low level 3:high level uint32_t mode:2; uint32_t reserved_31_26:6; } REG_extint_pd1_vwake_int_bitfiled_TypeDef; typedef struct { union { __IO REG_extint_pd1_vwake_int_bitfiled_TypeDef bf;//bitfiled __IO uint32_t word; }; } REG_extint_pd1_vwake_int_TypeDef; typedef struct { //write 1 to clear interrupt uint32_t clr:1; uint32_t reserved_7_1:7; //0: disable interrupt uint32_t en:1; //1: mask interrupt uint32_t mask:1; uint32_t reserved_15_10:6; //interrupt value after latch uint32_t val:1; //interrupt source value uint32_t stat:1; uint32_t reserved_23_18:6; //interrupt trigger mode 0:rising 1:falling 2:low level 3:high level uint32_t mode:2; uint32_t reserved_31_26:6; } REG_extint_pd0_dac_comp_chng_int_bitfiled_TypeDef; typedef struct { union { __IO REG_extint_pd0_dac_comp_chng_int_bitfiled_TypeDef bf;//bitfiled __IO uint32_t word; }; } REG_extint_pd0_dac_comp_chng_int_TypeDef; typedef struct { //write 1 to clear interrupt uint32_t clr:1; uint32_t reserved_7_1:7; //0: disable interrupt uint32_t en:1; //1: mask interrupt uint32_t mask:1; uint32_t reserved_15_10:6; //interrupt value after latch uint32_t val:1; //interrupt source value uint32_t stat:1; uint32_t reserved_23_18:6; //interrupt trigger mode 0:rising 1:falling 2:low level 3:high level uint32_t mode:2; uint32_t reserved_31_26:6; } REG_extint_pd1_dac_comp_chng_int_bitfiled_TypeDef; typedef struct { union { __IO REG_extint_pd1_dac_comp_chng_int_bitfiled_TypeDef bf;//bitfiled __IO uint32_t word; }; } REG_extint_pd1_dac_comp_chng_int_TypeDef; typedef struct { //write 1 to clear interrupt uint32_t clr:1; uint32_t reserved_7_1:7; //0: disable interrupt uint32_t en:1; //1: mask interrupt uint32_t mask:1; uint32_t reserved_15_10:6; //interrupt value after latch uint32_t val:1; //interrupt source value uint32_t stat:1; uint32_t reserved_31_18:14; } REG_extint_pd0_vconn_oc_int_bitfiled_TypeDef; typedef struct { union { __IO REG_extint_pd0_vconn_oc_int_bitfiled_TypeDef bf;//bitfiled __IO uint32_t word; }; } REG_extint_pd0_vconn_oc_int_TypeDef; typedef struct { //write 1 to clear interrupt uint32_t clr:1; uint32_t reserved_7_1:7; //0: disable interrupt uint32_t en:1; //1: mask interrupt uint32_t mask:1; uint32_t reserved_15_10:6; //interrupt value after latch uint32_t val:1; //interrupt source value uint32_t stat:1; uint32_t reserved_31_18:14; } REG_extint_pd1_vconn_oc_int_bitfiled_TypeDef; typedef struct { union { __IO REG_extint_pd1_vconn_oc_int_bitfiled_TypeDef bf;//bitfiled __IO uint32_t word; }; } REG_extint_pd1_vconn_oc_int_TypeDef; typedef struct { //write 1 to clear interrupt uint32_t clr:1; uint32_t reserved_7_1:7; //0: disable interrupt uint32_t en:1; //1: mask interrupt uint32_t mask:1; uint32_t reserved_15_10:6; //interrupt value after latch uint32_t val:1; //interrupt source value uint32_t stat:1; uint32_t reserved_31_18:14; } REG_extint_dpdn0_comp_int_bitfiled_TypeDef; typedef struct { union { __IO REG_extint_dpdn0_comp_int_bitfiled_TypeDef bf;//bitfiled __IO uint32_t word; }; } REG_extint_dpdn0_comp_int_TypeDef; typedef struct { //write 1 to clear interrupt uint32_t clr:1; uint32_t reserved_7_1:7; //0: disable interrupt uint32_t en:1; //1: mask interrupt uint32_t mask:1; uint32_t reserved_15_10:6; //interrupt value after latch uint32_t val:1; //interrupt source value uint32_t stat:1; uint32_t reserved_31_18:14; } REG_extint_dpdn1_comp_int_bitfiled_TypeDef; typedef struct { union { __IO REG_extint_dpdn1_comp_int_bitfiled_TypeDef bf;//bitfiled __IO uint32_t word; }; } REG_extint_dpdn1_comp_int_TypeDef; typedef struct { //write 1 to clear interrupt uint32_t clr:1; uint32_t reserved_7_1:7; //0: disable interrupt uint32_t en:1; //1: mask interrupt uint32_t mask:1; uint32_t reserved_15_10:6; //interrupt value after latch uint32_t val:1; //interrupt source value uint32_t stat:1; uint32_t reserved_31_18:14; } REG_extint_dpdn0_ovp_int_bitfiled_TypeDef; typedef struct { union { __IO REG_extint_dpdn0_ovp_int_bitfiled_TypeDef bf;//bitfiled __IO uint32_t word; }; } REG_extint_dpdn0_ovp_int_TypeDef; typedef struct { //write 1 to clear interrupt uint32_t clr:1; uint32_t reserved_7_1:7; //0: disable interrupt uint32_t en:1; //1: mask interrupt uint32_t mask:1; uint32_t reserved_15_10:6; //interrupt value after latch uint32_t val:1; //interrupt source value uint32_t stat:1; uint32_t reserved_31_18:14; } REG_extint_dpdn1_ovp_int_bitfiled_TypeDef; typedef struct { union { __IO REG_extint_dpdn1_ovp_int_bitfiled_TypeDef bf;//bitfiled __IO uint32_t word; }; } REG_extint_dpdn1_ovp_int_TypeDef; typedef struct { //write 1 to clear interrupt uint32_t clr:1; uint32_t reserved_7_1:7; //0: disable interrupt uint32_t en:1; //1: mask interrupt uint32_t mask:1; uint32_t reserved_15_10:6; //interrupt value after latch uint32_t val:1; //interrupt source value uint32_t stat:1; uint32_t reserved_23_18:6; //interrupt trigger mode 0:rising 1:falling 2:low level 3:high level uint32_t mode:2; uint32_t reserved_31_26:6; } REG_extint_chip_ot_int_bitfiled_TypeDef; typedef struct { union { __IO REG_extint_chip_ot_int_bitfiled_TypeDef bf;//bitfiled __IO uint32_t word; }; } REG_extint_chip_ot_int_TypeDef; typedef struct { //write 1 to clear interrupt uint32_t clr:1; uint32_t reserved_7_1:7; //0: disable interrupt uint32_t en:1; //1: mask interrupt uint32_t mask:1; uint32_t reserved_15_10:6; //interrupt value after latch uint32_t val:1; //interrupt source value uint32_t stat:1; uint32_t reserved_23_18:6; //interrupt trigger mode 0:rising 1:falling 2:low level 3:high level uint32_t mode:2; uint32_t reserved_31_26:6; } REG_extint_vin_ratiop_ov_int_bitfiled_TypeDef; typedef struct { union { __IO REG_extint_vin_ratiop_ov_int_bitfiled_TypeDef bf;//bitfiled __IO uint32_t word; }; } REG_extint_vin_ratiop_ov_int_TypeDef; typedef struct { //write 1 to clear interrupt uint32_t clr:1; uint32_t reserved_7_1:7; //0: disable interrupt uint32_t en:1; //1: mask interrupt uint32_t mask:1; uint32_t reserved_15_10:6; //interrupt value after latch uint32_t val:1; //interrupt source value uint32_t stat:1; uint32_t reserved_23_18:6; //interrupt trigger mode 0:rising 1:falling 2:low level 3:high level uint32_t mode:2; uint32_t reserved_31_26:6; } REG_extint_vin_ov_int_bitfiled_TypeDef; typedef struct { union { __IO REG_extint_vin_ov_int_bitfiled_TypeDef bf;//bitfiled __IO uint32_t word; }; } REG_extint_vin_ov_int_TypeDef; typedef struct { //write 1 to clear interrupt uint32_t clr:1; uint32_t reserved_7_1:7; //0: disable interrupt uint32_t en:1; //1: mask interrupt uint32_t mask:1; uint32_t reserved_15_10:6; //interrupt value after latch uint32_t val:1; //interrupt source value uint32_t stat:1; uint32_t reserved_23_18:6; //interrupt trigger mode 0:rising 1:falling 2:low level 3:high level uint32_t mode:2; uint32_t reserved_31_26:6; } REG_extint_vin_ratiop_uv_int_bitfiled_TypeDef; typedef struct { union { __IO REG_extint_vin_ratiop_uv_int_bitfiled_TypeDef bf;//bitfiled __IO uint32_t word; }; } REG_extint_vin_ratiop_uv_int_TypeDef; typedef struct { //write 1 to clear interrupt uint32_t clr:1; uint32_t reserved_7_1:7; //0: disable interrupt uint32_t en:1; //1: mask interrupt uint32_t mask:1; uint32_t reserved_15_10:6; //interrupt value after latch uint32_t val:1; //interrupt source value uint32_t stat:1; uint32_t reserved_23_18:6; //interrupt trigger mode 0:rising 1:falling 2:low level 3:high level uint32_t mode:2; uint32_t reserved_31_26:6; } REG_extint_vin1_ratiop_ov_int_bitfiled_TypeDef; typedef struct { union { __IO REG_extint_vin1_ratiop_ov_int_bitfiled_TypeDef bf;//bitfiled __IO uint32_t word; }; } REG_extint_vin1_ratiop_ov_int_TypeDef; typedef struct { //write 1 to clear interrupt uint32_t clr:1; uint32_t reserved_7_1:7; //0: disable interrupt uint32_t en:1; //1: mask interrupt uint32_t mask:1; uint32_t reserved_15_10:6; //interrupt value after latch uint32_t val:1; //interrupt source value uint32_t stat:1; uint32_t reserved_23_18:6; //interrupt trigger mode 0:rising 1:falling 2:low level 3:high level uint32_t mode:2; uint32_t reserved_31_26:6; } REG_extint_vin1_ov_int_bitfiled_TypeDef; typedef struct { union { __IO REG_extint_vin1_ov_int_bitfiled_TypeDef bf;//bitfiled __IO uint32_t word; }; } REG_extint_vin1_ov_int_TypeDef; typedef struct { //write 1 to clear interrupt uint32_t clr:1; uint32_t reserved_7_1:7; //0: disable interrupt uint32_t en:1; //1: mask interrupt uint32_t mask:1; uint32_t reserved_15_10:6; //interrupt value after latch uint32_t val:1; //interrupt source value uint32_t stat:1; uint32_t reserved_23_18:6; //interrupt trigger mode 0:rising 1:falling 2:low level 3:high level uint32_t mode:2; uint32_t reserved_31_26:6; } REG_extint_vin1_ratiop_uv_int_bitfiled_TypeDef; typedef struct { union { __IO REG_extint_vin1_ratiop_uv_int_bitfiled_TypeDef bf;//bitfiled __IO uint32_t word; }; } REG_extint_vin1_ratiop_uv_int_TypeDef; typedef struct { //write 1 to clear interrupt uint32_t clr:1; uint32_t reserved_7_1:7; //0: disable interrupt uint32_t en:1; //1: mask interrupt uint32_t mask:1; uint32_t reserved_15_10:6; //interrupt value after latch uint32_t val:1; //interrupt source value uint32_t stat:1; uint32_t reserved_23_18:6; //interrupt trigger mode 0:rising 1:falling 2:low level 3:high level uint32_t mode:2; uint32_t reserved_31_26:6; } REG_extint_vin2_ratiop_ov_int_bitfiled_TypeDef; typedef struct { union { __IO REG_extint_vin2_ratiop_ov_int_bitfiled_TypeDef bf;//bitfiled __IO uint32_t word; }; } REG_extint_vin2_ratiop_ov_int_TypeDef; typedef struct { //write 1 to clear interrupt uint32_t clr:1; uint32_t reserved_7_1:7; //0: disable interrupt uint32_t en:1; //1: mask interrupt uint32_t mask:1; uint32_t reserved_15_10:6; //interrupt value after latch uint32_t val:1; //interrupt source value uint32_t stat:1; uint32_t reserved_23_18:6; //interrupt trigger mode 0:rising 1:falling 2:low level 3:high level uint32_t mode:2; uint32_t reserved_31_26:6; } REG_extint_vin2_ov_int_bitfiled_TypeDef; typedef struct { union { __IO REG_extint_vin2_ov_int_bitfiled_TypeDef bf;//bitfiled __IO uint32_t word; }; } REG_extint_vin2_ov_int_TypeDef; typedef struct { //write 1 to clear interrupt uint32_t clr:1; uint32_t reserved_7_1:7; //0: disable interrupt uint32_t en:1; //1: mask interrupt uint32_t mask:1; uint32_t reserved_15_10:6; //interrupt value after latch uint32_t val:1; //interrupt source value uint32_t stat:1; uint32_t reserved_23_18:6; //interrupt trigger mode 0:rising 1:falling 2:low level 3:high level uint32_t mode:2; uint32_t reserved_31_26:6; } REG_extint_vin2_ratiop_uv_int_bitfiled_TypeDef; typedef struct { union { __IO REG_extint_vin2_ratiop_uv_int_bitfiled_TypeDef bf;//bitfiled __IO uint32_t word; }; } REG_extint_vin2_ratiop_uv_int_TypeDef; typedef struct { //write 1 to clear interrupt uint32_t clr:1; uint32_t reserved_7_1:7; //0: disable interrupt uint32_t en:1; //1: mask interrupt uint32_t mask:1; uint32_t reserved_15_10:6; //interrupt value after latch uint32_t val:1; //interrupt source value uint32_t stat:1; uint32_t reserved_31_18:14; } REG_extint_exit_green_int_bitfiled_TypeDef; typedef struct { union { __IO REG_extint_exit_green_int_bitfiled_TypeDef bf;//bitfiled __IO uint32_t word; }; } REG_extint_exit_green_int_TypeDef; typedef struct { //write 1 to clear interrupt uint32_t clr:1; uint32_t reserved_7_1:7; //0: disable interrupt uint32_t en:1; //1: mask interrupt uint32_t mask:1; uint32_t reserved_15_10:6; //interrupt value after latch uint32_t val:1; //interrupt source value:low level int uint32_t stat:1; uint32_t reserved_23_18:6; //interrupt trigger mode 0:rising 1:falling 2:low level 3:high level uint32_t mode:2; uint32_t reserved_31_26:6; } REG_extint_sda1_neg_det_int_bitfiled_TypeDef; typedef struct { union { __IO REG_extint_sda1_neg_det_int_bitfiled_TypeDef bf;//bitfiled __IO uint32_t word; }; } REG_extint_sda1_neg_det_int_TypeDef; typedef struct { //write 1 to clear interrupt uint32_t clr:1; uint32_t reserved_7_1:7; //0: disable interrupt uint32_t en:1; //1: mask interrupt uint32_t mask:1; uint32_t reserved_15_10:6; //interrupt value after latch uint32_t val:1; //interrupt source value:low level int uint32_t stat:1; uint32_t reserved_23_18:6; //interrupt trigger mode 0:rising 1:falling 2:low level 3:high level uint32_t mode:2; uint32_t reserved_31_26:6; } REG_extint_sda2_neg_det_int_bitfiled_TypeDef; typedef struct { union { __IO REG_extint_sda2_neg_det_int_bitfiled_TypeDef bf;//bitfiled __IO uint32_t word; }; } REG_extint_sda2_neg_det_int_TypeDef; typedef struct { //write 1 to clear interrupt uint32_t clr:1; uint32_t reserved_7_1:7; //0: disable interrupt uint32_t en:1; //1: mask interrupt uint32_t mask:1; uint32_t reserved_15_10:6; //interrupt value after latch:low level int uint32_t val:1; //interrupt source value uint32_t stat:1; uint32_t reserved_23_18:6; //interrupt trigger mode 0:rising 1:falling 2:low level 3:high level uint32_t mode:2; uint32_t reserved_31_26:6; } REG_extint_scl1_neg_det_int_bitfiled_TypeDef; typedef struct { union { __IO REG_extint_scl1_neg_det_int_bitfiled_TypeDef bf;//bitfiled __IO uint32_t word; }; } REG_extint_scl1_neg_det_int_TypeDef; typedef struct { //write 1 to clear interrupt uint32_t clr:1; uint32_t reserved_7_1:7; //0: disable interrupt uint32_t en:1; //1: mask interrupt uint32_t mask:1; uint32_t reserved_15_10:6; //interrupt value after latch:low level int uint32_t val:1; //interrupt source value uint32_t stat:1; uint32_t reserved_23_18:6; //interrupt trigger mode 0:rising 1:falling 2:low level 3:high level uint32_t mode:2; uint32_t reserved_31_26:6; } REG_extint_scl2_neg_det_int_bitfiled_TypeDef; typedef struct { union { __IO REG_extint_scl2_neg_det_int_bitfiled_TypeDef bf;//bitfiled __IO uint32_t word; }; } REG_extint_scl2_neg_det_int_TypeDef; typedef struct { //write 1 to clear interrupt uint32_t clr:1; uint32_t reserved_7_1:7; //0: disable interrupt uint32_t en:1; //1: mask interrupt uint32_t mask:1; uint32_t reserved_15_10:6; //interrupt value after latch uint32_t val:1; //interrupt source value uint32_t stat:1; uint32_t reserved_31_18:14; } REG_extint_pd0_ccx_ovp_int_bitfiled_TypeDef; typedef struct { union { __IO REG_extint_pd0_ccx_ovp_int_bitfiled_TypeDef bf;//bitfiled __IO uint32_t word; }; } REG_extint_pd0_ccx_ovp_int_TypeDef; typedef struct { //write 1 to clear interrupt uint32_t clr:1; uint32_t reserved_7_1:7; //0: disable interrupt uint32_t en:1; //1: mask interrupt uint32_t mask:1; uint32_t reserved_15_10:6; //interrupt value after latch uint32_t val:1; //interrupt source value uint32_t stat:1; uint32_t reserved_31_18:14; } REG_extint_pd1_ccx_ovp_int_bitfiled_TypeDef; typedef struct { union { __IO REG_extint_pd1_ccx_ovp_int_bitfiled_TypeDef bf;//bitfiled __IO uint32_t word; }; } REG_extint_pd1_ccx_ovp_int_TypeDef; typedef struct { //write 1 to clear interrupt uint32_t clr:1; uint32_t reserved_7_1:7; //0: disable interrupt uint32_t en:1; //1: mask interrupt uint32_t mask:1; uint32_t reserved_15_10:6; //interrupt value after latch uint32_t val:1; //interrupt source value uint32_t stat:1; uint32_t reserved_31_18:14; } REG_extint_v2_ocp_int_bitfiled_TypeDef; typedef struct { union { __IO REG_extint_v2_ocp_int_bitfiled_TypeDef bf;//bitfiled __IO uint32_t word; }; } REG_extint_v2_ocp_int_TypeDef; typedef struct { //write 1 to clear interrupt uint32_t clr:1; uint32_t reserved_7_1:7; //0: disable interrupt uint32_t en:1; //1: mask interrupt uint32_t mask:1; uint32_t reserved_15_10:6; //interrupt value after latch uint32_t val:1; //interrupt source value uint32_t stat:1; uint32_t reserved_31_18:14; } REG_extint_vbusoc1_int_bitfiled_TypeDef; typedef struct { union { __IO REG_extint_vbusoc1_int_bitfiled_TypeDef bf;//bitfiled __IO uint32_t word; }; } REG_extint_vbusoc1_int_TypeDef; typedef struct { //write 1 to clear interrupt uint32_t clr:1; uint32_t reserved_7_1:7; //0: disable interrupt uint32_t en:1; //1: mask interrupt uint32_t mask:1; uint32_t reserved_15_10:6; //interrupt value after latch uint32_t val:1; //interrupt source value uint32_t stat:1; uint32_t reserved_31_18:14; } REG_extint_vbusoc2_int_bitfiled_TypeDef; typedef struct { union { __IO REG_extint_vbusoc2_int_bitfiled_TypeDef bf;//bitfiled __IO uint32_t word; }; } REG_extint_vbusoc2_int_TypeDef; typedef struct { //write 1 to clear interrupt uint32_t clr:1; uint32_t reserved_7_1:7; //0: disable interrupt uint32_t en:1; //1: mask interrupt uint32_t mask:1; uint32_t reserved_15_10:6; //interrupt value after latch uint32_t val:1; //interrupt source value uint32_t stat:1; uint32_t reserved_31_18:14; } REG_extint_vin1_uvlo_int_bitfiled_TypeDef; typedef struct { union { __IO REG_extint_vin1_uvlo_int_bitfiled_TypeDef bf;//bitfiled __IO uint32_t word; }; } REG_extint_vin1_uvlo_int_TypeDef; typedef struct { //write 1 to clear interrupt uint32_t clr:1; uint32_t reserved_7_1:7; //0: disable interrupt uint32_t en:1; //1: mask interrupt uint32_t mask:1; uint32_t reserved_15_10:6; //interrupt value after latch uint32_t val:1; //interrupt source value uint32_t stat:1; uint32_t reserved_31_18:14; } REG_extint_vin2_uvlo_int_bitfiled_TypeDef; typedef struct { union { __IO REG_extint_vin2_uvlo_int_bitfiled_TypeDef bf;//bitfiled __IO uint32_t word; }; } REG_extint_vin2_uvlo_int_TypeDef; //----------------------------------------------------------------------------- // memory map #define REG_EXTINT_PWD0_INT_BASE 0x40013000 #define REG_EXTINT_PWD1_INT_BASE 0x40013004 #define REG_EXTINT_PWD2_INT_BASE 0x40013008 #define REG_EXTINT_PWD3_INT_BASE 0x4001300C #define REG_EXTINT_I2C_FUNC0_INT_BASE 0x40013010 #define REG_EXTINT_I2C_FUNC1_INT_BASE 0x40013014 #define REG_EXTINT_VD_LS_COMP_CHG_INT_BASE 0x40013018 #define REG_EXTINT_PD0_CCX_STAT_INT_BASE 0x4001301C #define REG_EXTINT_PD1_CCX_STAT_INT_BASE 0x40013020 #define REG_EXTINT_PD0_VWAKE_INT_BASE 0x40013024 #define REG_EXTINT_PD1_VWAKE_INT_BASE 0x40013028 #define REG_EXTINT_PD0_DAC_COMP_CHNG_INT_BASE 0x4001302C #define REG_EXTINT_PD1_DAC_COMP_CHNG_INT_BASE 0x40013030 #define REG_EXTINT_PD0_VCONN_OC_INT_BASE 0x40013034 #define REG_EXTINT_PD1_VCONN_OC_INT_BASE 0x40013038 #define REG_EXTINT_DPDN0_COMP_INT_BASE 0x4001303C #define REG_EXTINT_DPDN1_COMP_INT_BASE 0x40013040 #define REG_EXTINT_DPDN0_OVP_INT_BASE 0x40013044 #define REG_EXTINT_DPDN1_OVP_INT_BASE 0x40013048 #define REG_EXTINT_CHIP_OT_INT_BASE 0x4001304C #define REG_EXTINT_VIN_RATIOP_OV_INT_BASE 0x40013050 #define REG_EXTINT_VIN_OV_INT_BASE 0x40013054 #define REG_EXTINT_VIN_RATIOP_UV_INT_BASE 0x40013058 #define REG_EXTINT_VIN1_RATIOP_OV_INT_BASE 0x4001305C #define REG_EXTINT_VIN1_OV_INT_BASE 0x40013060 #define REG_EXTINT_VIN1_RATIOP_UV_INT_BASE 0x40013064 #define REG_EXTINT_VIN2_RATIOP_OV_INT_BASE 0x40013068 #define REG_EXTINT_VIN2_OV_INT_BASE 0x4001306C #define REG_EXTINT_VIN2_RATIOP_UV_INT_BASE 0x40013070 #define REG_EXTINT_EXIT_GREEN_INT_BASE 0x40013074 #define REG_EXTINT_SDA1_NEG_DET_INT_BASE 0x40013078 #define REG_EXTINT_SDA2_NEG_DET_INT_BASE 0x4001307C #define REG_EXTINT_SCL1_NEG_DET_INT_BASE 0x40013080 #define REG_EXTINT_SCL2_NEG_DET_INT_BASE 0x40013084 #define REG_EXTINT_PD0_CCX_OVP_INT_BASE 0x40013088 #define REG_EXTINT_PD1_CCX_OVP_INT_BASE 0x40013090 #define REG_EXTINT_V2_OCP_INT_BASE 0x40013094 #define REG_EXTINT_VBUSOC1_INT_BASE 0x40013098 #define REG_EXTINT_VBUSOC2_INT_BASE 0x400130A0 #define REG_EXTINT_VIN1_UVLO_INT_BASE 0x400130A4 #define REG_EXTINT_VIN2_UVLO_INT_BASE 0x400130A8 //----------------------------------------------------------------------------- // declaration #define REG_EXTINT_PWD0_INT ((REG_extint_pwd0_int_TypeDef *) REG_EXTINT_PWD0_INT_BASE ) #define REG_EXTINT_PWD1_INT ((REG_extint_pwd1_int_TypeDef *) REG_EXTINT_PWD1_INT_BASE ) #define REG_EXTINT_PWD2_INT ((REG_extint_pwd2_int_TypeDef *) REG_EXTINT_PWD2_INT_BASE ) #define REG_EXTINT_PWD3_INT ((REG_extint_pwd3_int_TypeDef *) REG_EXTINT_PWD3_INT_BASE ) #define REG_EXTINT_I2C_FUNC0_INT ((REG_extint_i2c_func0_int_TypeDef *) REG_EXTINT_I2C_FUNC0_INT_BASE ) #define REG_EXTINT_I2C_FUNC1_INT ((REG_extint_i2c_func1_int_TypeDef *) REG_EXTINT_I2C_FUNC1_INT_BASE ) #define REG_EXTINT_VD_LS_COMP_CHG_INT ((REG_extint_vd_ls_comp_chg_int_TypeDef *) REG_EXTINT_VD_LS_COMP_CHG_INT_BASE ) #define REG_EXTINT_PD0_CCX_STAT_INT ((REG_extint_pd0_ccx_stat_int_TypeDef *) REG_EXTINT_PD0_CCX_STAT_INT_BASE ) #define REG_EXTINT_PD1_CCX_STAT_INT ((REG_extint_pd1_ccx_stat_int_TypeDef *) REG_EXTINT_PD1_CCX_STAT_INT_BASE ) #define REG_EXTINT_PD0_VWAKE_INT ((REG_extint_pd0_vwake_int_TypeDef *) REG_EXTINT_PD0_VWAKE_INT_BASE ) #define REG_EXTINT_PD1_VWAKE_INT ((REG_extint_pd1_vwake_int_TypeDef *) REG_EXTINT_PD1_VWAKE_INT_BASE ) #define REG_EXTINT_PD0_DAC_COMP_CHNG_INT ((REG_extint_pd0_dac_comp_chng_int_TypeDef *) REG_EXTINT_PD0_DAC_COMP_CHNG_INT_BASE ) #define REG_EXTINT_PD1_DAC_COMP_CHNG_INT ((REG_extint_pd1_dac_comp_chng_int_TypeDef *) REG_EXTINT_PD1_DAC_COMP_CHNG_INT_BASE ) #define REG_EXTINT_PD0_VCONN_OC_INT ((REG_extint_pd0_vconn_oc_int_TypeDef *) REG_EXTINT_PD0_VCONN_OC_INT_BASE ) #define REG_EXTINT_PD1_VCONN_OC_INT ((REG_extint_pd1_vconn_oc_int_TypeDef *) REG_EXTINT_PD1_VCONN_OC_INT_BASE ) #define REG_EXTINT_DPDN0_COMP_INT ((REG_extint_dpdn0_comp_int_TypeDef *) REG_EXTINT_DPDN0_COMP_INT_BASE ) #define REG_EXTINT_DPDN1_COMP_INT ((REG_extint_dpdn1_comp_int_TypeDef *) REG_EXTINT_DPDN1_COMP_INT_BASE ) #define REG_EXTINT_DPDN0_OVP_INT ((REG_extint_dpdn0_ovp_int_TypeDef *) REG_EXTINT_DPDN0_OVP_INT_BASE ) #define REG_EXTINT_DPDN1_OVP_INT ((REG_extint_dpdn1_ovp_int_TypeDef *) REG_EXTINT_DPDN1_OVP_INT_BASE ) #define REG_EXTINT_CHIP_OT_INT ((REG_extint_chip_ot_int_TypeDef *) REG_EXTINT_CHIP_OT_INT_BASE ) #define REG_EXTINT_VIN_RATIOP_OV_INT ((REG_extint_vin_ratiop_ov_int_TypeDef *) REG_EXTINT_VIN_RATIOP_OV_INT_BASE ) #define REG_EXTINT_VIN_OV_INT ((REG_extint_vin_ov_int_TypeDef *) REG_EXTINT_VIN_OV_INT_BASE ) #define REG_EXTINT_VIN_RATIOP_UV_INT ((REG_extint_vin_ratiop_uv_int_TypeDef *) REG_EXTINT_VIN_RATIOP_UV_INT_BASE ) #define REG_EXTINT_VIN1_RATIOP_OV_INT ((REG_extint_vin1_ratiop_ov_int_TypeDef *) REG_EXTINT_VIN1_RATIOP_OV_INT_BASE ) #define REG_EXTINT_VIN1_OV_INT ((REG_extint_vin1_ov_int_TypeDef *) REG_EXTINT_VIN1_OV_INT_BASE ) #define REG_EXTINT_VIN1_RATIOP_UV_INT ((REG_extint_vin1_ratiop_uv_int_TypeDef *) REG_EXTINT_VIN1_RATIOP_UV_INT_BASE ) #define REG_EXTINT_VIN2_RATIOP_OV_INT ((REG_extint_vin2_ratiop_ov_int_TypeDef *) REG_EXTINT_VIN2_RATIOP_OV_INT_BASE ) #define REG_EXTINT_VIN2_OV_INT ((REG_extint_vin2_ov_int_TypeDef *) REG_EXTINT_VIN2_OV_INT_BASE ) #define REG_EXTINT_VIN2_RATIOP_UV_INT ((REG_extint_vin2_ratiop_uv_int_TypeDef *) REG_EXTINT_VIN2_RATIOP_UV_INT_BASE ) #define REG_EXTINT_EXIT_GREEN_INT ((REG_extint_exit_green_int_TypeDef *) REG_EXTINT_EXIT_GREEN_INT_BASE ) #define REG_EXTINT_SDA1_NEG_DET_INT ((REG_extint_sda1_neg_det_int_TypeDef *) REG_EXTINT_SDA1_NEG_DET_INT_BASE ) #define REG_EXTINT_SDA2_NEG_DET_INT ((REG_extint_sda2_neg_det_int_TypeDef *) REG_EXTINT_SDA2_NEG_DET_INT_BASE ) #define REG_EXTINT_SCL1_NEG_DET_INT ((REG_extint_scl1_neg_det_int_TypeDef *) REG_EXTINT_SCL1_NEG_DET_INT_BASE ) #define REG_EXTINT_SCL2_NEG_DET_INT ((REG_extint_scl2_neg_det_int_TypeDef *) REG_EXTINT_SCL2_NEG_DET_INT_BASE ) #define REG_EXTINT_PD0_CCX_OVP_INT ((REG_extint_pd0_ccx_ovp_int_TypeDef *) REG_EXTINT_PD0_CCX_OVP_INT_BASE ) #define REG_EXTINT_PD1_CCX_OVP_INT ((REG_extint_pd1_ccx_ovp_int_TypeDef *) REG_EXTINT_PD1_CCX_OVP_INT_BASE ) #define REG_EXTINT_V2_OCP_INT ((REG_extint_v2_ocp_int_TypeDef *) REG_EXTINT_V2_OCP_INT_BASE ) #define REG_EXTINT_VBUSOC1_INT ((REG_extint_vbusoc1_int_TypeDef *) REG_EXTINT_VBUSOC1_INT_BASE ) #define REG_EXTINT_VBUSOC2_INT ((REG_extint_vbusoc2_int_TypeDef *) REG_EXTINT_VBUSOC2_INT_BASE ) #define REG_EXTINT_VIN1_UVLO_INT ((REG_extint_vin1_uvlo_int_TypeDef *) REG_EXTINT_VIN1_UVLO_INT_BASE ) #define REG_EXTINT_VIN2_UVLO_INT ((REG_extint_vin2_uvlo_int_TypeDef *) REG_EXTINT_VIN2_UVLO_INT_BASE ) //----------------------------------------------------------------------------- // set #define REG_EXTINT_PWD0_INT_CLR_POS 0 #define REG_EXTINT_PWD0_INT_CLR_MSK (0x1ul << REG_EXTINT_PWD0_INT_CLR_POS) #define REG_EXTINT_PWD0_INT_CLR_SET(num) (((num) << REG_EXTINT_PWD0_INT_CLR_POS ) & REG_EXTINT_PWD0_INT_CLR_MSK) #define REG_EXTINT_PWD0_INT_EN_POS 8 #define REG_EXTINT_PWD0_INT_EN_MSK (0x1ul << REG_EXTINT_PWD0_INT_EN_POS) #define REG_EXTINT_PWD0_INT_EN_SET(num) (((num) << REG_EXTINT_PWD0_INT_EN_POS ) & REG_EXTINT_PWD0_INT_EN_MSK) #define REG_EXTINT_PWD0_INT_MASK_POS 9 #define REG_EXTINT_PWD0_INT_MASK_MSK (0x1ul << REG_EXTINT_PWD0_INT_MASK_POS) #define REG_EXTINT_PWD0_INT_MASK_SET(num) (((num) << REG_EXTINT_PWD0_INT_MASK_POS ) & REG_EXTINT_PWD0_INT_MASK_MSK) #define REG_EXTINT_PWD1_INT_CLR_POS 0 #define REG_EXTINT_PWD1_INT_CLR_MSK (0x1ul << REG_EXTINT_PWD1_INT_CLR_POS) #define REG_EXTINT_PWD1_INT_CLR_SET(num) (((num) << REG_EXTINT_PWD1_INT_CLR_POS ) & REG_EXTINT_PWD1_INT_CLR_MSK) #define REG_EXTINT_PWD1_INT_EN_POS 8 #define REG_EXTINT_PWD1_INT_EN_MSK (0x1ul << REG_EXTINT_PWD1_INT_EN_POS) #define REG_EXTINT_PWD1_INT_EN_SET(num) (((num) << REG_EXTINT_PWD1_INT_EN_POS ) & REG_EXTINT_PWD1_INT_EN_MSK) #define REG_EXTINT_PWD1_INT_MASK_POS 9 #define REG_EXTINT_PWD1_INT_MASK_MSK (0x1ul << REG_EXTINT_PWD1_INT_MASK_POS) #define REG_EXTINT_PWD1_INT_MASK_SET(num) (((num) << REG_EXTINT_PWD1_INT_MASK_POS ) & REG_EXTINT_PWD1_INT_MASK_MSK) #define REG_EXTINT_PWD2_INT_CLR_POS 0 #define REG_EXTINT_PWD2_INT_CLR_MSK (0x1ul << REG_EXTINT_PWD2_INT_CLR_POS) #define REG_EXTINT_PWD2_INT_CLR_SET(num) (((num) << REG_EXTINT_PWD2_INT_CLR_POS ) & REG_EXTINT_PWD2_INT_CLR_MSK) #define REG_EXTINT_PWD2_INT_EN_POS 8 #define REG_EXTINT_PWD2_INT_EN_MSK (0x1ul << REG_EXTINT_PWD2_INT_EN_POS) #define REG_EXTINT_PWD2_INT_EN_SET(num) (((num) << REG_EXTINT_PWD2_INT_EN_POS ) & REG_EXTINT_PWD2_INT_EN_MSK) #define REG_EXTINT_PWD2_INT_MASK_POS 9 #define REG_EXTINT_PWD2_INT_MASK_MSK (0x1ul << REG_EXTINT_PWD2_INT_MASK_POS) #define REG_EXTINT_PWD2_INT_MASK_SET(num) (((num) << REG_EXTINT_PWD2_INT_MASK_POS ) & REG_EXTINT_PWD2_INT_MASK_MSK) #define REG_EXTINT_PWD3_INT_CLR_POS 0 #define REG_EXTINT_PWD3_INT_CLR_MSK (0x1ul << REG_EXTINT_PWD3_INT_CLR_POS) #define REG_EXTINT_PWD3_INT_CLR_SET(num) (((num) << REG_EXTINT_PWD3_INT_CLR_POS ) & REG_EXTINT_PWD3_INT_CLR_MSK) #define REG_EXTINT_PWD3_INT_EN_POS 8 #define REG_EXTINT_PWD3_INT_EN_MSK (0x1ul << REG_EXTINT_PWD3_INT_EN_POS) #define REG_EXTINT_PWD3_INT_EN_SET(num) (((num) << REG_EXTINT_PWD3_INT_EN_POS ) & REG_EXTINT_PWD3_INT_EN_MSK) #define REG_EXTINT_PWD3_INT_MASK_POS 9 #define REG_EXTINT_PWD3_INT_MASK_MSK (0x1ul << REG_EXTINT_PWD3_INT_MASK_POS) #define REG_EXTINT_PWD3_INT_MASK_SET(num) (((num) << REG_EXTINT_PWD3_INT_MASK_POS ) & REG_EXTINT_PWD3_INT_MASK_MSK) #define REG_EXTINT_I2C_FUNC0_INT_CLR_POS 0 #define REG_EXTINT_I2C_FUNC0_INT_CLR_MSK (0x1ul << REG_EXTINT_I2C_FUNC0_INT_CLR_POS) #define REG_EXTINT_I2C_FUNC0_INT_CLR_SET(num) (((num) << REG_EXTINT_I2C_FUNC0_INT_CLR_POS ) & REG_EXTINT_I2C_FUNC0_INT_CLR_MSK) #define REG_EXTINT_I2C_FUNC0_INT_EN_POS 8 #define REG_EXTINT_I2C_FUNC0_INT_EN_MSK (0x1ul << REG_EXTINT_I2C_FUNC0_INT_EN_POS) #define REG_EXTINT_I2C_FUNC0_INT_EN_SET(num) (((num) << REG_EXTINT_I2C_FUNC0_INT_EN_POS ) & REG_EXTINT_I2C_FUNC0_INT_EN_MSK) #define REG_EXTINT_I2C_FUNC0_INT_MASK_POS 9 #define REG_EXTINT_I2C_FUNC0_INT_MASK_MSK (0x1ul << REG_EXTINT_I2C_FUNC0_INT_MASK_POS) #define REG_EXTINT_I2C_FUNC0_INT_MASK_SET(num) (((num) << REG_EXTINT_I2C_FUNC0_INT_MASK_POS ) & REG_EXTINT_I2C_FUNC0_INT_MASK_MSK) #define REG_EXTINT_I2C_FUNC1_INT_CLR_POS 0 #define REG_EXTINT_I2C_FUNC1_INT_CLR_MSK (0x1ul << REG_EXTINT_I2C_FUNC1_INT_CLR_POS) #define REG_EXTINT_I2C_FUNC1_INT_CLR_SET(num) (((num) << REG_EXTINT_I2C_FUNC1_INT_CLR_POS ) & REG_EXTINT_I2C_FUNC1_INT_CLR_MSK) #define REG_EXTINT_I2C_FUNC1_INT_EN_POS 8 #define REG_EXTINT_I2C_FUNC1_INT_EN_MSK (0x1ul << REG_EXTINT_I2C_FUNC1_INT_EN_POS) #define REG_EXTINT_I2C_FUNC1_INT_EN_SET(num) (((num) << REG_EXTINT_I2C_FUNC1_INT_EN_POS ) & REG_EXTINT_I2C_FUNC1_INT_EN_MSK) #define REG_EXTINT_I2C_FUNC1_INT_MASK_POS 9 #define REG_EXTINT_I2C_FUNC1_INT_MASK_MSK (0x1ul << REG_EXTINT_I2C_FUNC1_INT_MASK_POS) #define REG_EXTINT_I2C_FUNC1_INT_MASK_SET(num) (((num) << REG_EXTINT_I2C_FUNC1_INT_MASK_POS ) & REG_EXTINT_I2C_FUNC1_INT_MASK_MSK) #define REG_EXTINT_VD_LS_COMP_CHG_INT_CLR_POS 0 #define REG_EXTINT_VD_LS_COMP_CHG_INT_CLR_MSK (0x1ul << REG_EXTINT_VD_LS_COMP_CHG_INT_CLR_POS) #define REG_EXTINT_VD_LS_COMP_CHG_INT_CLR_SET(num) (((num) << REG_EXTINT_VD_LS_COMP_CHG_INT_CLR_POS ) & REG_EXTINT_VD_LS_COMP_CHG_INT_CLR_MSK) #define REG_EXTINT_VD_LS_COMP_CHG_INT_EN_POS 8 #define REG_EXTINT_VD_LS_COMP_CHG_INT_EN_MSK (0x1ul << REG_EXTINT_VD_LS_COMP_CHG_INT_EN_POS) #define REG_EXTINT_VD_LS_COMP_CHG_INT_EN_SET(num) (((num) << REG_EXTINT_VD_LS_COMP_CHG_INT_EN_POS ) & REG_EXTINT_VD_LS_COMP_CHG_INT_EN_MSK) #define REG_EXTINT_VD_LS_COMP_CHG_INT_MASK_POS 9 #define REG_EXTINT_VD_LS_COMP_CHG_INT_MASK_MSK (0x1ul << REG_EXTINT_VD_LS_COMP_CHG_INT_MASK_POS) #define REG_EXTINT_VD_LS_COMP_CHG_INT_MASK_SET(num) (((num) << REG_EXTINT_VD_LS_COMP_CHG_INT_MASK_POS ) & REG_EXTINT_VD_LS_COMP_CHG_INT_MASK_MSK) #define REG_EXTINT_PD0_CCX_STAT_INT_CLR_POS 0 #define REG_EXTINT_PD0_CCX_STAT_INT_CLR_MSK (0x1ul << REG_EXTINT_PD0_CCX_STAT_INT_CLR_POS) #define REG_EXTINT_PD0_CCX_STAT_INT_CLR_SET(num) (((num) << REG_EXTINT_PD0_CCX_STAT_INT_CLR_POS ) & REG_EXTINT_PD0_CCX_STAT_INT_CLR_MSK) #define REG_EXTINT_PD0_CCX_STAT_INT_EN_POS 8 #define REG_EXTINT_PD0_CCX_STAT_INT_EN_MSK (0x1ul << REG_EXTINT_PD0_CCX_STAT_INT_EN_POS) #define REG_EXTINT_PD0_CCX_STAT_INT_EN_SET(num) (((num) << REG_EXTINT_PD0_CCX_STAT_INT_EN_POS ) & REG_EXTINT_PD0_CCX_STAT_INT_EN_MSK) #define REG_EXTINT_PD0_CCX_STAT_INT_MASK_POS 9 #define REG_EXTINT_PD0_CCX_STAT_INT_MASK_MSK (0x1ul << REG_EXTINT_PD0_CCX_STAT_INT_MASK_POS) #define REG_EXTINT_PD0_CCX_STAT_INT_MASK_SET(num) (((num) << REG_EXTINT_PD0_CCX_STAT_INT_MASK_POS ) & REG_EXTINT_PD0_CCX_STAT_INT_MASK_MSK) #define REG_EXTINT_PD0_CCX_STAT_INT_MODE_POS 24 #define REG_EXTINT_PD0_CCX_STAT_INT_MODE_MSK (0x3ul << REG_EXTINT_PD0_CCX_STAT_INT_MODE_POS) #define REG_EXTINT_PD0_CCX_STAT_INT_MODE_SET(num) (((num) << REG_EXTINT_PD0_CCX_STAT_INT_MODE_POS ) & REG_EXTINT_PD0_CCX_STAT_INT_MODE_MSK) #define REG_EXTINT_PD1_CCX_STAT_INT_CLR_POS 0 #define REG_EXTINT_PD1_CCX_STAT_INT_CLR_MSK (0x1ul << REG_EXTINT_PD1_CCX_STAT_INT_CLR_POS) #define REG_EXTINT_PD1_CCX_STAT_INT_CLR_SET(num) (((num) << REG_EXTINT_PD1_CCX_STAT_INT_CLR_POS ) & REG_EXTINT_PD1_CCX_STAT_INT_CLR_MSK) #define REG_EXTINT_PD1_CCX_STAT_INT_EN_POS 8 #define REG_EXTINT_PD1_CCX_STAT_INT_EN_MSK (0x1ul << REG_EXTINT_PD1_CCX_STAT_INT_EN_POS) #define REG_EXTINT_PD1_CCX_STAT_INT_EN_SET(num) (((num) << REG_EXTINT_PD1_CCX_STAT_INT_EN_POS ) & REG_EXTINT_PD1_CCX_STAT_INT_EN_MSK) #define REG_EXTINT_PD1_CCX_STAT_INT_MASK_POS 9 #define REG_EXTINT_PD1_CCX_STAT_INT_MASK_MSK (0x1ul << REG_EXTINT_PD1_CCX_STAT_INT_MASK_POS) #define REG_EXTINT_PD1_CCX_STAT_INT_MASK_SET(num) (((num) << REG_EXTINT_PD1_CCX_STAT_INT_MASK_POS ) & REG_EXTINT_PD1_CCX_STAT_INT_MASK_MSK) #define REG_EXTINT_PD1_CCX_STAT_INT_MODE_POS 24 #define REG_EXTINT_PD1_CCX_STAT_INT_MODE_MSK (0x3ul << REG_EXTINT_PD1_CCX_STAT_INT_MODE_POS) #define REG_EXTINT_PD1_CCX_STAT_INT_MODE_SET(num) (((num) << REG_EXTINT_PD1_CCX_STAT_INT_MODE_POS ) & REG_EXTINT_PD1_CCX_STAT_INT_MODE_MSK) #define REG_EXTINT_PD0_VWAKE_INT_CLR_POS 0 #define REG_EXTINT_PD0_VWAKE_INT_CLR_MSK (0x1ul << REG_EXTINT_PD0_VWAKE_INT_CLR_POS) #define REG_EXTINT_PD0_VWAKE_INT_CLR_SET(num) (((num) << REG_EXTINT_PD0_VWAKE_INT_CLR_POS ) & REG_EXTINT_PD0_VWAKE_INT_CLR_MSK) #define REG_EXTINT_PD0_VWAKE_INT_EN_POS 8 #define REG_EXTINT_PD0_VWAKE_INT_EN_MSK (0x1ul << REG_EXTINT_PD0_VWAKE_INT_EN_POS) #define REG_EXTINT_PD0_VWAKE_INT_EN_SET(num) (((num) << REG_EXTINT_PD0_VWAKE_INT_EN_POS ) & REG_EXTINT_PD0_VWAKE_INT_EN_MSK) #define REG_EXTINT_PD0_VWAKE_INT_MASK_POS 9 #define REG_EXTINT_PD0_VWAKE_INT_MASK_MSK (0x1ul << REG_EXTINT_PD0_VWAKE_INT_MASK_POS) #define REG_EXTINT_PD0_VWAKE_INT_MASK_SET(num) (((num) << REG_EXTINT_PD0_VWAKE_INT_MASK_POS ) & REG_EXTINT_PD0_VWAKE_INT_MASK_MSK) #define REG_EXTINT_PD0_VWAKE_INT_MODE_POS 24 #define REG_EXTINT_PD0_VWAKE_INT_MODE_MSK (0x3ul << REG_EXTINT_PD0_VWAKE_INT_MODE_POS) #define REG_EXTINT_PD0_VWAKE_INT_MODE_SET(num) (((num) << REG_EXTINT_PD0_VWAKE_INT_MODE_POS ) & REG_EXTINT_PD0_VWAKE_INT_MODE_MSK) #define REG_EXTINT_PD1_VWAKE_INT_CLR_POS 0 #define REG_EXTINT_PD1_VWAKE_INT_CLR_MSK (0x1ul << REG_EXTINT_PD1_VWAKE_INT_CLR_POS) #define REG_EXTINT_PD1_VWAKE_INT_CLR_SET(num) (((num) << REG_EXTINT_PD1_VWAKE_INT_CLR_POS ) & REG_EXTINT_PD1_VWAKE_INT_CLR_MSK) #define REG_EXTINT_PD1_VWAKE_INT_EN_POS 8 #define REG_EXTINT_PD1_VWAKE_INT_EN_MSK (0x1ul << REG_EXTINT_PD1_VWAKE_INT_EN_POS) #define REG_EXTINT_PD1_VWAKE_INT_EN_SET(num) (((num) << REG_EXTINT_PD1_VWAKE_INT_EN_POS ) & REG_EXTINT_PD1_VWAKE_INT_EN_MSK) #define REG_EXTINT_PD1_VWAKE_INT_MASK_POS 9 #define REG_EXTINT_PD1_VWAKE_INT_MASK_MSK (0x1ul << REG_EXTINT_PD1_VWAKE_INT_MASK_POS) #define REG_EXTINT_PD1_VWAKE_INT_MASK_SET(num) (((num) << REG_EXTINT_PD1_VWAKE_INT_MASK_POS ) & REG_EXTINT_PD1_VWAKE_INT_MASK_MSK) #define REG_EXTINT_PD1_VWAKE_INT_MODE_POS 24 #define REG_EXTINT_PD1_VWAKE_INT_MODE_MSK (0x3ul << REG_EXTINT_PD1_VWAKE_INT_MODE_POS) #define REG_EXTINT_PD1_VWAKE_INT_MODE_SET(num) (((num) << REG_EXTINT_PD1_VWAKE_INT_MODE_POS ) & REG_EXTINT_PD1_VWAKE_INT_MODE_MSK) #define REG_EXTINT_PD0_DAC_COMP_CHNG_INT_CLR_POS 0 #define REG_EXTINT_PD0_DAC_COMP_CHNG_INT_CLR_MSK (0x1ul << REG_EXTINT_PD0_DAC_COMP_CHNG_INT_CLR_POS) #define REG_EXTINT_PD0_DAC_COMP_CHNG_INT_CLR_SET(num) (((num) << REG_EXTINT_PD0_DAC_COMP_CHNG_INT_CLR_POS ) & REG_EXTINT_PD0_DAC_COMP_CHNG_INT_CLR_MSK) #define REG_EXTINT_PD0_DAC_COMP_CHNG_INT_EN_POS 8 #define REG_EXTINT_PD0_DAC_COMP_CHNG_INT_EN_MSK (0x1ul << REG_EXTINT_PD0_DAC_COMP_CHNG_INT_EN_POS) #define REG_EXTINT_PD0_DAC_COMP_CHNG_INT_EN_SET(num) (((num) << REG_EXTINT_PD0_DAC_COMP_CHNG_INT_EN_POS ) & REG_EXTINT_PD0_DAC_COMP_CHNG_INT_EN_MSK) #define REG_EXTINT_PD0_DAC_COMP_CHNG_INT_MASK_POS 9 #define REG_EXTINT_PD0_DAC_COMP_CHNG_INT_MASK_MSK (0x1ul << REG_EXTINT_PD0_DAC_COMP_CHNG_INT_MASK_POS) #define REG_EXTINT_PD0_DAC_COMP_CHNG_INT_MASK_SET(num) (((num) << REG_EXTINT_PD0_DAC_COMP_CHNG_INT_MASK_POS ) & REG_EXTINT_PD0_DAC_COMP_CHNG_INT_MASK_MSK) #define REG_EXTINT_PD0_DAC_COMP_CHNG_INT_MODE_POS 24 #define REG_EXTINT_PD0_DAC_COMP_CHNG_INT_MODE_MSK (0x3ul << REG_EXTINT_PD0_DAC_COMP_CHNG_INT_MODE_POS) #define REG_EXTINT_PD0_DAC_COMP_CHNG_INT_MODE_SET(num) (((num) << REG_EXTINT_PD0_DAC_COMP_CHNG_INT_MODE_POS ) & REG_EXTINT_PD0_DAC_COMP_CHNG_INT_MODE_MSK) #define REG_EXTINT_PD1_DAC_COMP_CHNG_INT_CLR_POS 0 #define REG_EXTINT_PD1_DAC_COMP_CHNG_INT_CLR_MSK (0x1ul << REG_EXTINT_PD1_DAC_COMP_CHNG_INT_CLR_POS) #define REG_EXTINT_PD1_DAC_COMP_CHNG_INT_CLR_SET(num) (((num) << REG_EXTINT_PD1_DAC_COMP_CHNG_INT_CLR_POS ) & REG_EXTINT_PD1_DAC_COMP_CHNG_INT_CLR_MSK) #define REG_EXTINT_PD1_DAC_COMP_CHNG_INT_EN_POS 8 #define REG_EXTINT_PD1_DAC_COMP_CHNG_INT_EN_MSK (0x1ul << REG_EXTINT_PD1_DAC_COMP_CHNG_INT_EN_POS) #define REG_EXTINT_PD1_DAC_COMP_CHNG_INT_EN_SET(num) (((num) << REG_EXTINT_PD1_DAC_COMP_CHNG_INT_EN_POS ) & REG_EXTINT_PD1_DAC_COMP_CHNG_INT_EN_MSK) #define REG_EXTINT_PD1_DAC_COMP_CHNG_INT_MASK_POS 9 #define REG_EXTINT_PD1_DAC_COMP_CHNG_INT_MASK_MSK (0x1ul << REG_EXTINT_PD1_DAC_COMP_CHNG_INT_MASK_POS) #define REG_EXTINT_PD1_DAC_COMP_CHNG_INT_MASK_SET(num) (((num) << REG_EXTINT_PD1_DAC_COMP_CHNG_INT_MASK_POS ) & REG_EXTINT_PD1_DAC_COMP_CHNG_INT_MASK_MSK) #define REG_EXTINT_PD1_DAC_COMP_CHNG_INT_MODE_POS 24 #define REG_EXTINT_PD1_DAC_COMP_CHNG_INT_MODE_MSK (0x3ul << REG_EXTINT_PD1_DAC_COMP_CHNG_INT_MODE_POS) #define REG_EXTINT_PD1_DAC_COMP_CHNG_INT_MODE_SET(num) (((num) << REG_EXTINT_PD1_DAC_COMP_CHNG_INT_MODE_POS ) & REG_EXTINT_PD1_DAC_COMP_CHNG_INT_MODE_MSK) #define REG_EXTINT_PD0_VCONN_OC_INT_CLR_POS 0 #define REG_EXTINT_PD0_VCONN_OC_INT_CLR_MSK (0x1ul << REG_EXTINT_PD0_VCONN_OC_INT_CLR_POS) #define REG_EXTINT_PD0_VCONN_OC_INT_CLR_SET(num) (((num) << REG_EXTINT_PD0_VCONN_OC_INT_CLR_POS ) & REG_EXTINT_PD0_VCONN_OC_INT_CLR_MSK) #define REG_EXTINT_PD0_VCONN_OC_INT_EN_POS 8 #define REG_EXTINT_PD0_VCONN_OC_INT_EN_MSK (0x1ul << REG_EXTINT_PD0_VCONN_OC_INT_EN_POS) #define REG_EXTINT_PD0_VCONN_OC_INT_EN_SET(num) (((num) << REG_EXTINT_PD0_VCONN_OC_INT_EN_POS ) & REG_EXTINT_PD0_VCONN_OC_INT_EN_MSK) #define REG_EXTINT_PD0_VCONN_OC_INT_MASK_POS 9 #define REG_EXTINT_PD0_VCONN_OC_INT_MASK_MSK (0x1ul << REG_EXTINT_PD0_VCONN_OC_INT_MASK_POS) #define REG_EXTINT_PD0_VCONN_OC_INT_MASK_SET(num) (((num) << REG_EXTINT_PD0_VCONN_OC_INT_MASK_POS ) & REG_EXTINT_PD0_VCONN_OC_INT_MASK_MSK) #define REG_EXTINT_PD1_VCONN_OC_INT_CLR_POS 0 #define REG_EXTINT_PD1_VCONN_OC_INT_CLR_MSK (0x1ul << REG_EXTINT_PD1_VCONN_OC_INT_CLR_POS) #define REG_EXTINT_PD1_VCONN_OC_INT_CLR_SET(num) (((num) << REG_EXTINT_PD1_VCONN_OC_INT_CLR_POS ) & REG_EXTINT_PD1_VCONN_OC_INT_CLR_MSK) #define REG_EXTINT_PD1_VCONN_OC_INT_EN_POS 8 #define REG_EXTINT_PD1_VCONN_OC_INT_EN_MSK (0x1ul << REG_EXTINT_PD1_VCONN_OC_INT_EN_POS) #define REG_EXTINT_PD1_VCONN_OC_INT_EN_SET(num) (((num) << REG_EXTINT_PD1_VCONN_OC_INT_EN_POS ) & REG_EXTINT_PD1_VCONN_OC_INT_EN_MSK) #define REG_EXTINT_PD1_VCONN_OC_INT_MASK_POS 9 #define REG_EXTINT_PD1_VCONN_OC_INT_MASK_MSK (0x1ul << REG_EXTINT_PD1_VCONN_OC_INT_MASK_POS) #define REG_EXTINT_PD1_VCONN_OC_INT_MASK_SET(num) (((num) << REG_EXTINT_PD1_VCONN_OC_INT_MASK_POS ) & REG_EXTINT_PD1_VCONN_OC_INT_MASK_MSK) #define REG_EXTINT_DPDN0_COMP_INT_CLR_POS 0 #define REG_EXTINT_DPDN0_COMP_INT_CLR_MSK (0x1ul << REG_EXTINT_DPDN0_COMP_INT_CLR_POS) #define REG_EXTINT_DPDN0_COMP_INT_CLR_SET(num) (((num) << REG_EXTINT_DPDN0_COMP_INT_CLR_POS ) & REG_EXTINT_DPDN0_COMP_INT_CLR_MSK) #define REG_EXTINT_DPDN0_COMP_INT_EN_POS 8 #define REG_EXTINT_DPDN0_COMP_INT_EN_MSK (0x1ul << REG_EXTINT_DPDN0_COMP_INT_EN_POS) #define REG_EXTINT_DPDN0_COMP_INT_EN_SET(num) (((num) << REG_EXTINT_DPDN0_COMP_INT_EN_POS ) & REG_EXTINT_DPDN0_COMP_INT_EN_MSK) #define REG_EXTINT_DPDN0_COMP_INT_MASK_POS 9 #define REG_EXTINT_DPDN0_COMP_INT_MASK_MSK (0x1ul << REG_EXTINT_DPDN0_COMP_INT_MASK_POS) #define REG_EXTINT_DPDN0_COMP_INT_MASK_SET(num) (((num) << REG_EXTINT_DPDN0_COMP_INT_MASK_POS ) & REG_EXTINT_DPDN0_COMP_INT_MASK_MSK) #define REG_EXTINT_DPDN1_COMP_INT_CLR_POS 0 #define REG_EXTINT_DPDN1_COMP_INT_CLR_MSK (0x1ul << REG_EXTINT_DPDN1_COMP_INT_CLR_POS) #define REG_EXTINT_DPDN1_COMP_INT_CLR_SET(num) (((num) << REG_EXTINT_DPDN1_COMP_INT_CLR_POS ) & REG_EXTINT_DPDN1_COMP_INT_CLR_MSK) #define REG_EXTINT_DPDN1_COMP_INT_EN_POS 8 #define REG_EXTINT_DPDN1_COMP_INT_EN_MSK (0x1ul << REG_EXTINT_DPDN1_COMP_INT_EN_POS) #define REG_EXTINT_DPDN1_COMP_INT_EN_SET(num) (((num) << REG_EXTINT_DPDN1_COMP_INT_EN_POS ) & REG_EXTINT_DPDN1_COMP_INT_EN_MSK) #define REG_EXTINT_DPDN1_COMP_INT_MASK_POS 9 #define REG_EXTINT_DPDN1_COMP_INT_MASK_MSK (0x1ul << REG_EXTINT_DPDN1_COMP_INT_MASK_POS) #define REG_EXTINT_DPDN1_COMP_INT_MASK_SET(num) (((num) << REG_EXTINT_DPDN1_COMP_INT_MASK_POS ) & REG_EXTINT_DPDN1_COMP_INT_MASK_MSK) #define REG_EXTINT_DPDN0_OVP_INT_CLR_POS 0 #define REG_EXTINT_DPDN0_OVP_INT_CLR_MSK (0x1ul << REG_EXTINT_DPDN0_OVP_INT_CLR_POS) #define REG_EXTINT_DPDN0_OVP_INT_CLR_SET(num) (((num) << REG_EXTINT_DPDN0_OVP_INT_CLR_POS ) & REG_EXTINT_DPDN0_OVP_INT_CLR_MSK) #define REG_EXTINT_DPDN0_OVP_INT_EN_POS 8 #define REG_EXTINT_DPDN0_OVP_INT_EN_MSK (0x1ul << REG_EXTINT_DPDN0_OVP_INT_EN_POS) #define REG_EXTINT_DPDN0_OVP_INT_EN_SET(num) (((num) << REG_EXTINT_DPDN0_OVP_INT_EN_POS ) & REG_EXTINT_DPDN0_OVP_INT_EN_MSK) #define REG_EXTINT_DPDN0_OVP_INT_MASK_POS 9 #define REG_EXTINT_DPDN0_OVP_INT_MASK_MSK (0x1ul << REG_EXTINT_DPDN0_OVP_INT_MASK_POS) #define REG_EXTINT_DPDN0_OVP_INT_MASK_SET(num) (((num) << REG_EXTINT_DPDN0_OVP_INT_MASK_POS ) & REG_EXTINT_DPDN0_OVP_INT_MASK_MSK) #define REG_EXTINT_DPDN1_OVP_INT_CLR_POS 0 #define REG_EXTINT_DPDN1_OVP_INT_CLR_MSK (0x1ul << REG_EXTINT_DPDN1_OVP_INT_CLR_POS) #define REG_EXTINT_DPDN1_OVP_INT_CLR_SET(num) (((num) << REG_EXTINT_DPDN1_OVP_INT_CLR_POS ) & REG_EXTINT_DPDN1_OVP_INT_CLR_MSK) #define REG_EXTINT_DPDN1_OVP_INT_EN_POS 8 #define REG_EXTINT_DPDN1_OVP_INT_EN_MSK (0x1ul << REG_EXTINT_DPDN1_OVP_INT_EN_POS) #define REG_EXTINT_DPDN1_OVP_INT_EN_SET(num) (((num) << REG_EXTINT_DPDN1_OVP_INT_EN_POS ) & REG_EXTINT_DPDN1_OVP_INT_EN_MSK) #define REG_EXTINT_DPDN1_OVP_INT_MASK_POS 9 #define REG_EXTINT_DPDN1_OVP_INT_MASK_MSK (0x1ul << REG_EXTINT_DPDN1_OVP_INT_MASK_POS) #define REG_EXTINT_DPDN1_OVP_INT_MASK_SET(num) (((num) << REG_EXTINT_DPDN1_OVP_INT_MASK_POS ) & REG_EXTINT_DPDN1_OVP_INT_MASK_MSK) #define REG_EXTINT_CHIP_OT_INT_CLR_POS 0 #define REG_EXTINT_CHIP_OT_INT_CLR_MSK (0x1ul << REG_EXTINT_CHIP_OT_INT_CLR_POS) #define REG_EXTINT_CHIP_OT_INT_CLR_SET(num) (((num) << REG_EXTINT_CHIP_OT_INT_CLR_POS ) & REG_EXTINT_CHIP_OT_INT_CLR_MSK) #define REG_EXTINT_CHIP_OT_INT_EN_POS 8 #define REG_EXTINT_CHIP_OT_INT_EN_MSK (0x1ul << REG_EXTINT_CHIP_OT_INT_EN_POS) #define REG_EXTINT_CHIP_OT_INT_EN_SET(num) (((num) << REG_EXTINT_CHIP_OT_INT_EN_POS ) & REG_EXTINT_CHIP_OT_INT_EN_MSK) #define REG_EXTINT_CHIP_OT_INT_MASK_POS 9 #define REG_EXTINT_CHIP_OT_INT_MASK_MSK (0x1ul << REG_EXTINT_CHIP_OT_INT_MASK_POS) #define REG_EXTINT_CHIP_OT_INT_MASK_SET(num) (((num) << REG_EXTINT_CHIP_OT_INT_MASK_POS ) & REG_EXTINT_CHIP_OT_INT_MASK_MSK) #define REG_EXTINT_CHIP_OT_INT_MODE_POS 24 #define REG_EXTINT_CHIP_OT_INT_MODE_MSK (0x3ul << REG_EXTINT_CHIP_OT_INT_MODE_POS) #define REG_EXTINT_CHIP_OT_INT_MODE_SET(num) (((num) << REG_EXTINT_CHIP_OT_INT_MODE_POS ) & REG_EXTINT_CHIP_OT_INT_MODE_MSK) #define REG_EXTINT_VIN_RATIOP_OV_INT_CLR_POS 0 #define REG_EXTINT_VIN_RATIOP_OV_INT_CLR_MSK (0x1ul << REG_EXTINT_VIN_RATIOP_OV_INT_CLR_POS) #define REG_EXTINT_VIN_RATIOP_OV_INT_CLR_SET(num) (((num) << REG_EXTINT_VIN_RATIOP_OV_INT_CLR_POS ) & REG_EXTINT_VIN_RATIOP_OV_INT_CLR_MSK) #define REG_EXTINT_VIN_RATIOP_OV_INT_EN_POS 8 #define REG_EXTINT_VIN_RATIOP_OV_INT_EN_MSK (0x1ul << REG_EXTINT_VIN_RATIOP_OV_INT_EN_POS) #define REG_EXTINT_VIN_RATIOP_OV_INT_EN_SET(num) (((num) << REG_EXTINT_VIN_RATIOP_OV_INT_EN_POS ) & REG_EXTINT_VIN_RATIOP_OV_INT_EN_MSK) #define REG_EXTINT_VIN_RATIOP_OV_INT_MASK_POS 9 #define REG_EXTINT_VIN_RATIOP_OV_INT_MASK_MSK (0x1ul << REG_EXTINT_VIN_RATIOP_OV_INT_MASK_POS) #define REG_EXTINT_VIN_RATIOP_OV_INT_MASK_SET(num) (((num) << REG_EXTINT_VIN_RATIOP_OV_INT_MASK_POS ) & REG_EXTINT_VIN_RATIOP_OV_INT_MASK_MSK) #define REG_EXTINT_VIN_RATIOP_OV_INT_MODE_POS 24 #define REG_EXTINT_VIN_RATIOP_OV_INT_MODE_MSK (0x3ul << REG_EXTINT_VIN_RATIOP_OV_INT_MODE_POS) #define REG_EXTINT_VIN_RATIOP_OV_INT_MODE_SET(num) (((num) << REG_EXTINT_VIN_RATIOP_OV_INT_MODE_POS ) & REG_EXTINT_VIN_RATIOP_OV_INT_MODE_MSK) #define REG_EXTINT_VIN_OV_INT_CLR_POS 0 #define REG_EXTINT_VIN_OV_INT_CLR_MSK (0x1ul << REG_EXTINT_VIN_OV_INT_CLR_POS) #define REG_EXTINT_VIN_OV_INT_CLR_SET(num) (((num) << REG_EXTINT_VIN_OV_INT_CLR_POS ) & REG_EXTINT_VIN_OV_INT_CLR_MSK) #define REG_EXTINT_VIN_OV_INT_EN_POS 8 #define REG_EXTINT_VIN_OV_INT_EN_MSK (0x1ul << REG_EXTINT_VIN_OV_INT_EN_POS) #define REG_EXTINT_VIN_OV_INT_EN_SET(num) (((num) << REG_EXTINT_VIN_OV_INT_EN_POS ) & REG_EXTINT_VIN_OV_INT_EN_MSK) #define REG_EXTINT_VIN_OV_INT_MASK_POS 9 #define REG_EXTINT_VIN_OV_INT_MASK_MSK (0x1ul << REG_EXTINT_VIN_OV_INT_MASK_POS) #define REG_EXTINT_VIN_OV_INT_MASK_SET(num) (((num) << REG_EXTINT_VIN_OV_INT_MASK_POS ) & REG_EXTINT_VIN_OV_INT_MASK_MSK) #define REG_EXTINT_VIN_OV_INT_MODE_POS 24 #define REG_EXTINT_VIN_OV_INT_MODE_MSK (0x3ul << REG_EXTINT_VIN_OV_INT_MODE_POS) #define REG_EXTINT_VIN_OV_INT_MODE_SET(num) (((num) << REG_EXTINT_VIN_OV_INT_MODE_POS ) & REG_EXTINT_VIN_OV_INT_MODE_MSK) #define REG_EXTINT_VIN_RATIOP_UV_INT_CLR_POS 0 #define REG_EXTINT_VIN_RATIOP_UV_INT_CLR_MSK (0x1ul << REG_EXTINT_VIN_RATIOP_UV_INT_CLR_POS) #define REG_EXTINT_VIN_RATIOP_UV_INT_CLR_SET(num) (((num) << REG_EXTINT_VIN_RATIOP_UV_INT_CLR_POS ) & REG_EXTINT_VIN_RATIOP_UV_INT_CLR_MSK) #define REG_EXTINT_VIN_RATIOP_UV_INT_EN_POS 8 #define REG_EXTINT_VIN_RATIOP_UV_INT_EN_MSK (0x1ul << REG_EXTINT_VIN_RATIOP_UV_INT_EN_POS) #define REG_EXTINT_VIN_RATIOP_UV_INT_EN_SET(num) (((num) << REG_EXTINT_VIN_RATIOP_UV_INT_EN_POS ) & REG_EXTINT_VIN_RATIOP_UV_INT_EN_MSK) #define REG_EXTINT_VIN_RATIOP_UV_INT_MASK_POS 9 #define REG_EXTINT_VIN_RATIOP_UV_INT_MASK_MSK (0x1ul << REG_EXTINT_VIN_RATIOP_UV_INT_MASK_POS) #define REG_EXTINT_VIN_RATIOP_UV_INT_MASK_SET(num) (((num) << REG_EXTINT_VIN_RATIOP_UV_INT_MASK_POS ) & REG_EXTINT_VIN_RATIOP_UV_INT_MASK_MSK) #define REG_EXTINT_VIN_RATIOP_UV_INT_MODE_POS 24 #define REG_EXTINT_VIN_RATIOP_UV_INT_MODE_MSK (0x3ul << REG_EXTINT_VIN_RATIOP_UV_INT_MODE_POS) #define REG_EXTINT_VIN_RATIOP_UV_INT_MODE_SET(num) (((num) << REG_EXTINT_VIN_RATIOP_UV_INT_MODE_POS ) & REG_EXTINT_VIN_RATIOP_UV_INT_MODE_MSK) #define REG_EXTINT_VIN1_RATIOP_OV_INT_CLR_POS 0 #define REG_EXTINT_VIN1_RATIOP_OV_INT_CLR_MSK (0x1ul << REG_EXTINT_VIN1_RATIOP_OV_INT_CLR_POS) #define REG_EXTINT_VIN1_RATIOP_OV_INT_CLR_SET(num) (((num) << REG_EXTINT_VIN1_RATIOP_OV_INT_CLR_POS ) & REG_EXTINT_VIN1_RATIOP_OV_INT_CLR_MSK) #define REG_EXTINT_VIN1_RATIOP_OV_INT_EN_POS 8 #define REG_EXTINT_VIN1_RATIOP_OV_INT_EN_MSK (0x1ul << REG_EXTINT_VIN1_RATIOP_OV_INT_EN_POS) #define REG_EXTINT_VIN1_RATIOP_OV_INT_EN_SET(num) (((num) << REG_EXTINT_VIN1_RATIOP_OV_INT_EN_POS ) & REG_EXTINT_VIN1_RATIOP_OV_INT_EN_MSK) #define REG_EXTINT_VIN1_RATIOP_OV_INT_MASK_POS 9 #define REG_EXTINT_VIN1_RATIOP_OV_INT_MASK_MSK (0x1ul << REG_EXTINT_VIN1_RATIOP_OV_INT_MASK_POS) #define REG_EXTINT_VIN1_RATIOP_OV_INT_MASK_SET(num) (((num) << REG_EXTINT_VIN1_RATIOP_OV_INT_MASK_POS ) & REG_EXTINT_VIN1_RATIOP_OV_INT_MASK_MSK) #define REG_EXTINT_VIN1_RATIOP_OV_INT_MODE_POS 24 #define REG_EXTINT_VIN1_RATIOP_OV_INT_MODE_MSK (0x3ul << REG_EXTINT_VIN1_RATIOP_OV_INT_MODE_POS) #define REG_EXTINT_VIN1_RATIOP_OV_INT_MODE_SET(num) (((num) << REG_EXTINT_VIN1_RATIOP_OV_INT_MODE_POS ) & REG_EXTINT_VIN1_RATIOP_OV_INT_MODE_MSK) #define REG_EXTINT_VIN1_OV_INT_CLR_POS 0 #define REG_EXTINT_VIN1_OV_INT_CLR_MSK (0x1ul << REG_EXTINT_VIN1_OV_INT_CLR_POS) #define REG_EXTINT_VIN1_OV_INT_CLR_SET(num) (((num) << REG_EXTINT_VIN1_OV_INT_CLR_POS ) & REG_EXTINT_VIN1_OV_INT_CLR_MSK) #define REG_EXTINT_VIN1_OV_INT_EN_POS 8 #define REG_EXTINT_VIN1_OV_INT_EN_MSK (0x1ul << REG_EXTINT_VIN1_OV_INT_EN_POS) #define REG_EXTINT_VIN1_OV_INT_EN_SET(num) (((num) << REG_EXTINT_VIN1_OV_INT_EN_POS ) & REG_EXTINT_VIN1_OV_INT_EN_MSK) #define REG_EXTINT_VIN1_OV_INT_MASK_POS 9 #define REG_EXTINT_VIN1_OV_INT_MASK_MSK (0x1ul << REG_EXTINT_VIN1_OV_INT_MASK_POS) #define REG_EXTINT_VIN1_OV_INT_MASK_SET(num) (((num) << REG_EXTINT_VIN1_OV_INT_MASK_POS ) & REG_EXTINT_VIN1_OV_INT_MASK_MSK) #define REG_EXTINT_VIN1_OV_INT_MODE_POS 24 #define REG_EXTINT_VIN1_OV_INT_MODE_MSK (0x3ul << REG_EXTINT_VIN1_OV_INT_MODE_POS) #define REG_EXTINT_VIN1_OV_INT_MODE_SET(num) (((num) << REG_EXTINT_VIN1_OV_INT_MODE_POS ) & REG_EXTINT_VIN1_OV_INT_MODE_MSK) #define REG_EXTINT_VIN1_RATIOP_UV_INT_CLR_POS 0 #define REG_EXTINT_VIN1_RATIOP_UV_INT_CLR_MSK (0x1ul << REG_EXTINT_VIN1_RATIOP_UV_INT_CLR_POS) #define REG_EXTINT_VIN1_RATIOP_UV_INT_CLR_SET(num) (((num) << REG_EXTINT_VIN1_RATIOP_UV_INT_CLR_POS ) & REG_EXTINT_VIN1_RATIOP_UV_INT_CLR_MSK) #define REG_EXTINT_VIN1_RATIOP_UV_INT_EN_POS 8 #define REG_EXTINT_VIN1_RATIOP_UV_INT_EN_MSK (0x1ul << REG_EXTINT_VIN1_RATIOP_UV_INT_EN_POS) #define REG_EXTINT_VIN1_RATIOP_UV_INT_EN_SET(num) (((num) << REG_EXTINT_VIN1_RATIOP_UV_INT_EN_POS ) & REG_EXTINT_VIN1_RATIOP_UV_INT_EN_MSK) #define REG_EXTINT_VIN1_RATIOP_UV_INT_MASK_POS 9 #define REG_EXTINT_VIN1_RATIOP_UV_INT_MASK_MSK (0x1ul << REG_EXTINT_VIN1_RATIOP_UV_INT_MASK_POS) #define REG_EXTINT_VIN1_RATIOP_UV_INT_MASK_SET(num) (((num) << REG_EXTINT_VIN1_RATIOP_UV_INT_MASK_POS ) & REG_EXTINT_VIN1_RATIOP_UV_INT_MASK_MSK) #define REG_EXTINT_VIN1_RATIOP_UV_INT_MODE_POS 24 #define REG_EXTINT_VIN1_RATIOP_UV_INT_MODE_MSK (0x3ul << REG_EXTINT_VIN1_RATIOP_UV_INT_MODE_POS) #define REG_EXTINT_VIN1_RATIOP_UV_INT_MODE_SET(num) (((num) << REG_EXTINT_VIN1_RATIOP_UV_INT_MODE_POS ) & REG_EXTINT_VIN1_RATIOP_UV_INT_MODE_MSK) #define REG_EXTINT_VIN2_RATIOP_OV_INT_CLR_POS 0 #define REG_EXTINT_VIN2_RATIOP_OV_INT_CLR_MSK (0x1ul << REG_EXTINT_VIN2_RATIOP_OV_INT_CLR_POS) #define REG_EXTINT_VIN2_RATIOP_OV_INT_CLR_SET(num) (((num) << REG_EXTINT_VIN2_RATIOP_OV_INT_CLR_POS ) & REG_EXTINT_VIN2_RATIOP_OV_INT_CLR_MSK) #define REG_EXTINT_VIN2_RATIOP_OV_INT_EN_POS 8 #define REG_EXTINT_VIN2_RATIOP_OV_INT_EN_MSK (0x1ul << REG_EXTINT_VIN2_RATIOP_OV_INT_EN_POS) #define REG_EXTINT_VIN2_RATIOP_OV_INT_EN_SET(num) (((num) << REG_EXTINT_VIN2_RATIOP_OV_INT_EN_POS ) & REG_EXTINT_VIN2_RATIOP_OV_INT_EN_MSK) #define REG_EXTINT_VIN2_RATIOP_OV_INT_MASK_POS 9 #define REG_EXTINT_VIN2_RATIOP_OV_INT_MASK_MSK (0x1ul << REG_EXTINT_VIN2_RATIOP_OV_INT_MASK_POS) #define REG_EXTINT_VIN2_RATIOP_OV_INT_MASK_SET(num) (((num) << REG_EXTINT_VIN2_RATIOP_OV_INT_MASK_POS ) & REG_EXTINT_VIN2_RATIOP_OV_INT_MASK_MSK) #define REG_EXTINT_VIN2_RATIOP_OV_INT_MODE_POS 24 #define REG_EXTINT_VIN2_RATIOP_OV_INT_MODE_MSK (0x3ul << REG_EXTINT_VIN2_RATIOP_OV_INT_MODE_POS) #define REG_EXTINT_VIN2_RATIOP_OV_INT_MODE_SET(num) (((num) << REG_EXTINT_VIN2_RATIOP_OV_INT_MODE_POS ) & REG_EXTINT_VIN2_RATIOP_OV_INT_MODE_MSK) #define REG_EXTINT_VIN2_OV_INT_CLR_POS 0 #define REG_EXTINT_VIN2_OV_INT_CLR_MSK (0x1ul << REG_EXTINT_VIN2_OV_INT_CLR_POS) #define REG_EXTINT_VIN2_OV_INT_CLR_SET(num) (((num) << REG_EXTINT_VIN2_OV_INT_CLR_POS ) & REG_EXTINT_VIN2_OV_INT_CLR_MSK) #define REG_EXTINT_VIN2_OV_INT_EN_POS 8 #define REG_EXTINT_VIN2_OV_INT_EN_MSK (0x1ul << REG_EXTINT_VIN2_OV_INT_EN_POS) #define REG_EXTINT_VIN2_OV_INT_EN_SET(num) (((num) << REG_EXTINT_VIN2_OV_INT_EN_POS ) & REG_EXTINT_VIN2_OV_INT_EN_MSK) #define REG_EXTINT_VIN2_OV_INT_MASK_POS 9 #define REG_EXTINT_VIN2_OV_INT_MASK_MSK (0x1ul << REG_EXTINT_VIN2_OV_INT_MASK_POS) #define REG_EXTINT_VIN2_OV_INT_MASK_SET(num) (((num) << REG_EXTINT_VIN2_OV_INT_MASK_POS ) & REG_EXTINT_VIN2_OV_INT_MASK_MSK) #define REG_EXTINT_VIN2_OV_INT_MODE_POS 24 #define REG_EXTINT_VIN2_OV_INT_MODE_MSK (0x3ul << REG_EXTINT_VIN2_OV_INT_MODE_POS) #define REG_EXTINT_VIN2_OV_INT_MODE_SET(num) (((num) << REG_EXTINT_VIN2_OV_INT_MODE_POS ) & REG_EXTINT_VIN2_OV_INT_MODE_MSK) #define REG_EXTINT_VIN2_RATIOP_UV_INT_CLR_POS 0 #define REG_EXTINT_VIN2_RATIOP_UV_INT_CLR_MSK (0x1ul << REG_EXTINT_VIN2_RATIOP_UV_INT_CLR_POS) #define REG_EXTINT_VIN2_RATIOP_UV_INT_CLR_SET(num) (((num) << REG_EXTINT_VIN2_RATIOP_UV_INT_CLR_POS ) & REG_EXTINT_VIN2_RATIOP_UV_INT_CLR_MSK) #define REG_EXTINT_VIN2_RATIOP_UV_INT_EN_POS 8 #define REG_EXTINT_VIN2_RATIOP_UV_INT_EN_MSK (0x1ul << REG_EXTINT_VIN2_RATIOP_UV_INT_EN_POS) #define REG_EXTINT_VIN2_RATIOP_UV_INT_EN_SET(num) (((num) << REG_EXTINT_VIN2_RATIOP_UV_INT_EN_POS ) & REG_EXTINT_VIN2_RATIOP_UV_INT_EN_MSK) #define REG_EXTINT_VIN2_RATIOP_UV_INT_MASK_POS 9 #define REG_EXTINT_VIN2_RATIOP_UV_INT_MASK_MSK (0x1ul << REG_EXTINT_VIN2_RATIOP_UV_INT_MASK_POS) #define REG_EXTINT_VIN2_RATIOP_UV_INT_MASK_SET(num) (((num) << REG_EXTINT_VIN2_RATIOP_UV_INT_MASK_POS ) & REG_EXTINT_VIN2_RATIOP_UV_INT_MASK_MSK) #define REG_EXTINT_VIN2_RATIOP_UV_INT_MODE_POS 24 #define REG_EXTINT_VIN2_RATIOP_UV_INT_MODE_MSK (0x3ul << REG_EXTINT_VIN2_RATIOP_UV_INT_MODE_POS) #define REG_EXTINT_VIN2_RATIOP_UV_INT_MODE_SET(num) (((num) << REG_EXTINT_VIN2_RATIOP_UV_INT_MODE_POS ) & REG_EXTINT_VIN2_RATIOP_UV_INT_MODE_MSK) #define REG_EXTINT_EXIT_GREEN_INT_CLR_POS 0 #define REG_EXTINT_EXIT_GREEN_INT_CLR_MSK (0x1ul << REG_EXTINT_EXIT_GREEN_INT_CLR_POS) #define REG_EXTINT_EXIT_GREEN_INT_CLR_SET(num) (((num) << REG_EXTINT_EXIT_GREEN_INT_CLR_POS ) & REG_EXTINT_EXIT_GREEN_INT_CLR_MSK) #define REG_EXTINT_EXIT_GREEN_INT_EN_POS 8 #define REG_EXTINT_EXIT_GREEN_INT_EN_MSK (0x1ul << REG_EXTINT_EXIT_GREEN_INT_EN_POS) #define REG_EXTINT_EXIT_GREEN_INT_EN_SET(num) (((num) << REG_EXTINT_EXIT_GREEN_INT_EN_POS ) & REG_EXTINT_EXIT_GREEN_INT_EN_MSK) #define REG_EXTINT_EXIT_GREEN_INT_MASK_POS 9 #define REG_EXTINT_EXIT_GREEN_INT_MASK_MSK (0x1ul << REG_EXTINT_EXIT_GREEN_INT_MASK_POS) #define REG_EXTINT_EXIT_GREEN_INT_MASK_SET(num) (((num) << REG_EXTINT_EXIT_GREEN_INT_MASK_POS ) & REG_EXTINT_EXIT_GREEN_INT_MASK_MSK) #define REG_EXTINT_SDA1_NEG_DET_INT_CLR_POS 0 #define REG_EXTINT_SDA1_NEG_DET_INT_CLR_MSK (0x1ul << REG_EXTINT_SDA1_NEG_DET_INT_CLR_POS) #define REG_EXTINT_SDA1_NEG_DET_INT_CLR_SET(num) (((num) << REG_EXTINT_SDA1_NEG_DET_INT_CLR_POS ) & REG_EXTINT_SDA1_NEG_DET_INT_CLR_MSK) #define REG_EXTINT_SDA1_NEG_DET_INT_EN_POS 8 #define REG_EXTINT_SDA1_NEG_DET_INT_EN_MSK (0x1ul << REG_EXTINT_SDA1_NEG_DET_INT_EN_POS) #define REG_EXTINT_SDA1_NEG_DET_INT_EN_SET(num) (((num) << REG_EXTINT_SDA1_NEG_DET_INT_EN_POS ) & REG_EXTINT_SDA1_NEG_DET_INT_EN_MSK) #define REG_EXTINT_SDA1_NEG_DET_INT_MASK_POS 9 #define REG_EXTINT_SDA1_NEG_DET_INT_MASK_MSK (0x1ul << REG_EXTINT_SDA1_NEG_DET_INT_MASK_POS) #define REG_EXTINT_SDA1_NEG_DET_INT_MASK_SET(num) (((num) << REG_EXTINT_SDA1_NEG_DET_INT_MASK_POS ) & REG_EXTINT_SDA1_NEG_DET_INT_MASK_MSK) #define REG_EXTINT_SDA1_NEG_DET_INT_MODE_POS 24 #define REG_EXTINT_SDA1_NEG_DET_INT_MODE_MSK (0x3ul << REG_EXTINT_SDA1_NEG_DET_INT_MODE_POS) #define REG_EXTINT_SDA1_NEG_DET_INT_MODE_SET(num) (((num) << REG_EXTINT_SDA1_NEG_DET_INT_MODE_POS ) & REG_EXTINT_SDA1_NEG_DET_INT_MODE_MSK) #define REG_EXTINT_SDA2_NEG_DET_INT_CLR_POS 0 #define REG_EXTINT_SDA2_NEG_DET_INT_CLR_MSK (0x1ul << REG_EXTINT_SDA2_NEG_DET_INT_CLR_POS) #define REG_EXTINT_SDA2_NEG_DET_INT_CLR_SET(num) (((num) << REG_EXTINT_SDA2_NEG_DET_INT_CLR_POS ) & REG_EXTINT_SDA2_NEG_DET_INT_CLR_MSK) #define REG_EXTINT_SDA2_NEG_DET_INT_EN_POS 8 #define REG_EXTINT_SDA2_NEG_DET_INT_EN_MSK (0x1ul << REG_EXTINT_SDA2_NEG_DET_INT_EN_POS) #define REG_EXTINT_SDA2_NEG_DET_INT_EN_SET(num) (((num) << REG_EXTINT_SDA2_NEG_DET_INT_EN_POS ) & REG_EXTINT_SDA2_NEG_DET_INT_EN_MSK) #define REG_EXTINT_SDA2_NEG_DET_INT_MASK_POS 9 #define REG_EXTINT_SDA2_NEG_DET_INT_MASK_MSK (0x1ul << REG_EXTINT_SDA2_NEG_DET_INT_MASK_POS) #define REG_EXTINT_SDA2_NEG_DET_INT_MASK_SET(num) (((num) << REG_EXTINT_SDA2_NEG_DET_INT_MASK_POS ) & REG_EXTINT_SDA2_NEG_DET_INT_MASK_MSK) #define REG_EXTINT_SDA2_NEG_DET_INT_MODE_POS 24 #define REG_EXTINT_SDA2_NEG_DET_INT_MODE_MSK (0x3ul << REG_EXTINT_SDA2_NEG_DET_INT_MODE_POS) #define REG_EXTINT_SDA2_NEG_DET_INT_MODE_SET(num) (((num) << REG_EXTINT_SDA2_NEG_DET_INT_MODE_POS ) & REG_EXTINT_SDA2_NEG_DET_INT_MODE_MSK) #define REG_EXTINT_SCL1_NEG_DET_INT_CLR_POS 0 #define REG_EXTINT_SCL1_NEG_DET_INT_CLR_MSK (0x1ul << REG_EXTINT_SCL1_NEG_DET_INT_CLR_POS) #define REG_EXTINT_SCL1_NEG_DET_INT_CLR_SET(num) (((num) << REG_EXTINT_SCL1_NEG_DET_INT_CLR_POS ) & REG_EXTINT_SCL1_NEG_DET_INT_CLR_MSK) #define REG_EXTINT_SCL1_NEG_DET_INT_EN_POS 8 #define REG_EXTINT_SCL1_NEG_DET_INT_EN_MSK (0x1ul << REG_EXTINT_SCL1_NEG_DET_INT_EN_POS) #define REG_EXTINT_SCL1_NEG_DET_INT_EN_SET(num) (((num) << REG_EXTINT_SCL1_NEG_DET_INT_EN_POS ) & REG_EXTINT_SCL1_NEG_DET_INT_EN_MSK) #define REG_EXTINT_SCL1_NEG_DET_INT_MASK_POS 9 #define REG_EXTINT_SCL1_NEG_DET_INT_MASK_MSK (0x1ul << REG_EXTINT_SCL1_NEG_DET_INT_MASK_POS) #define REG_EXTINT_SCL1_NEG_DET_INT_MASK_SET(num) (((num) << REG_EXTINT_SCL1_NEG_DET_INT_MASK_POS ) & REG_EXTINT_SCL1_NEG_DET_INT_MASK_MSK) #define REG_EXTINT_SCL1_NEG_DET_INT_MODE_POS 24 #define REG_EXTINT_SCL1_NEG_DET_INT_MODE_MSK (0x3ul << REG_EXTINT_SCL1_NEG_DET_INT_MODE_POS) #define REG_EXTINT_SCL1_NEG_DET_INT_MODE_SET(num) (((num) << REG_EXTINT_SCL1_NEG_DET_INT_MODE_POS ) & REG_EXTINT_SCL1_NEG_DET_INT_MODE_MSK) #define REG_EXTINT_SCL2_NEG_DET_INT_CLR_POS 0 #define REG_EXTINT_SCL2_NEG_DET_INT_CLR_MSK (0x1ul << REG_EXTINT_SCL2_NEG_DET_INT_CLR_POS) #define REG_EXTINT_SCL2_NEG_DET_INT_CLR_SET(num) (((num) << REG_EXTINT_SCL2_NEG_DET_INT_CLR_POS ) & REG_EXTINT_SCL2_NEG_DET_INT_CLR_MSK) #define REG_EXTINT_SCL2_NEG_DET_INT_EN_POS 8 #define REG_EXTINT_SCL2_NEG_DET_INT_EN_MSK (0x1ul << REG_EXTINT_SCL2_NEG_DET_INT_EN_POS) #define REG_EXTINT_SCL2_NEG_DET_INT_EN_SET(num) (((num) << REG_EXTINT_SCL2_NEG_DET_INT_EN_POS ) & REG_EXTINT_SCL2_NEG_DET_INT_EN_MSK) #define REG_EXTINT_SCL2_NEG_DET_INT_MASK_POS 9 #define REG_EXTINT_SCL2_NEG_DET_INT_MASK_MSK (0x1ul << REG_EXTINT_SCL2_NEG_DET_INT_MASK_POS) #define REG_EXTINT_SCL2_NEG_DET_INT_MASK_SET(num) (((num) << REG_EXTINT_SCL2_NEG_DET_INT_MASK_POS ) & REG_EXTINT_SCL2_NEG_DET_INT_MASK_MSK) #define REG_EXTINT_SCL2_NEG_DET_INT_MODE_POS 24 #define REG_EXTINT_SCL2_NEG_DET_INT_MODE_MSK (0x3ul << REG_EXTINT_SCL2_NEG_DET_INT_MODE_POS) #define REG_EXTINT_SCL2_NEG_DET_INT_MODE_SET(num) (((num) << REG_EXTINT_SCL2_NEG_DET_INT_MODE_POS ) & REG_EXTINT_SCL2_NEG_DET_INT_MODE_MSK) #define REG_EXTINT_PD0_CCX_OVP_INT_CLR_POS 0 #define REG_EXTINT_PD0_CCX_OVP_INT_CLR_MSK (0x1ul << REG_EXTINT_PD0_CCX_OVP_INT_CLR_POS) #define REG_EXTINT_PD0_CCX_OVP_INT_CLR_SET(num) (((num) << REG_EXTINT_PD0_CCX_OVP_INT_CLR_POS ) & REG_EXTINT_PD0_CCX_OVP_INT_CLR_MSK) #define REG_EXTINT_PD0_CCX_OVP_INT_EN_POS 8 #define REG_EXTINT_PD0_CCX_OVP_INT_EN_MSK (0x1ul << REG_EXTINT_PD0_CCX_OVP_INT_EN_POS) #define REG_EXTINT_PD0_CCX_OVP_INT_EN_SET(num) (((num) << REG_EXTINT_PD0_CCX_OVP_INT_EN_POS ) & REG_EXTINT_PD0_CCX_OVP_INT_EN_MSK) #define REG_EXTINT_PD0_CCX_OVP_INT_MASK_POS 9 #define REG_EXTINT_PD0_CCX_OVP_INT_MASK_MSK (0x1ul << REG_EXTINT_PD0_CCX_OVP_INT_MASK_POS) #define REG_EXTINT_PD0_CCX_OVP_INT_MASK_SET(num) (((num) << REG_EXTINT_PD0_CCX_OVP_INT_MASK_POS ) & REG_EXTINT_PD0_CCX_OVP_INT_MASK_MSK) #define REG_EXTINT_PD1_CCX_OVP_INT_CLR_POS 0 #define REG_EXTINT_PD1_CCX_OVP_INT_CLR_MSK (0x1ul << REG_EXTINT_PD1_CCX_OVP_INT_CLR_POS) #define REG_EXTINT_PD1_CCX_OVP_INT_CLR_SET(num) (((num) << REG_EXTINT_PD1_CCX_OVP_INT_CLR_POS ) & REG_EXTINT_PD1_CCX_OVP_INT_CLR_MSK) #define REG_EXTINT_PD1_CCX_OVP_INT_EN_POS 8 #define REG_EXTINT_PD1_CCX_OVP_INT_EN_MSK (0x1ul << REG_EXTINT_PD1_CCX_OVP_INT_EN_POS) #define REG_EXTINT_PD1_CCX_OVP_INT_EN_SET(num) (((num) << REG_EXTINT_PD1_CCX_OVP_INT_EN_POS ) & REG_EXTINT_PD1_CCX_OVP_INT_EN_MSK) #define REG_EXTINT_PD1_CCX_OVP_INT_MASK_POS 9 #define REG_EXTINT_PD1_CCX_OVP_INT_MASK_MSK (0x1ul << REG_EXTINT_PD1_CCX_OVP_INT_MASK_POS) #define REG_EXTINT_PD1_CCX_OVP_INT_MASK_SET(num) (((num) << REG_EXTINT_PD1_CCX_OVP_INT_MASK_POS ) & REG_EXTINT_PD1_CCX_OVP_INT_MASK_MSK) #define REG_EXTINT_V2_OCP_INT_CLR_POS 0 #define REG_EXTINT_V2_OCP_INT_CLR_MSK (0x1ul << REG_EXTINT_V2_OCP_INT_CLR_POS) #define REG_EXTINT_V2_OCP_INT_CLR_SET(num) (((num) << REG_EXTINT_V2_OCP_INT_CLR_POS ) & REG_EXTINT_V2_OCP_INT_CLR_MSK) #define REG_EXTINT_V2_OCP_INT_EN_POS 8 #define REG_EXTINT_V2_OCP_INT_EN_MSK (0x1ul << REG_EXTINT_V2_OCP_INT_EN_POS) #define REG_EXTINT_V2_OCP_INT_EN_SET(num) (((num) << REG_EXTINT_V2_OCP_INT_EN_POS ) & REG_EXTINT_V2_OCP_INT_EN_MSK) #define REG_EXTINT_V2_OCP_INT_MASK_POS 9 #define REG_EXTINT_V2_OCP_INT_MASK_MSK (0x1ul << REG_EXTINT_V2_OCP_INT_MASK_POS) #define REG_EXTINT_V2_OCP_INT_MASK_SET(num) (((num) << REG_EXTINT_V2_OCP_INT_MASK_POS ) & REG_EXTINT_V2_OCP_INT_MASK_MSK) #define REG_EXTINT_VBUSOC1_INT_CLR_POS 0 #define REG_EXTINT_VBUSOC1_INT_CLR_MSK (0x1ul << REG_EXTINT_VBUSOC1_INT_CLR_POS) #define REG_EXTINT_VBUSOC1_INT_CLR_SET(num) (((num) << REG_EXTINT_VBUSOC1_INT_CLR_POS ) & REG_EXTINT_VBUSOC1_INT_CLR_MSK) #define REG_EXTINT_VBUSOC1_INT_EN_POS 8 #define REG_EXTINT_VBUSOC1_INT_EN_MSK (0x1ul << REG_EXTINT_VBUSOC1_INT_EN_POS) #define REG_EXTINT_VBUSOC1_INT_EN_SET(num) (((num) << REG_EXTINT_VBUSOC1_INT_EN_POS ) & REG_EXTINT_VBUSOC1_INT_EN_MSK) #define REG_EXTINT_VBUSOC1_INT_MASK_POS 9 #define REG_EXTINT_VBUSOC1_INT_MASK_MSK (0x1ul << REG_EXTINT_VBUSOC1_INT_MASK_POS) #define REG_EXTINT_VBUSOC1_INT_MASK_SET(num) (((num) << REG_EXTINT_VBUSOC1_INT_MASK_POS ) & REG_EXTINT_VBUSOC1_INT_MASK_MSK) #define REG_EXTINT_VBUSOC2_INT_CLR_POS 0 #define REG_EXTINT_VBUSOC2_INT_CLR_MSK (0x1ul << REG_EXTINT_VBUSOC2_INT_CLR_POS) #define REG_EXTINT_VBUSOC2_INT_CLR_SET(num) (((num) << REG_EXTINT_VBUSOC2_INT_CLR_POS ) & REG_EXTINT_VBUSOC2_INT_CLR_MSK) #define REG_EXTINT_VBUSOC2_INT_EN_POS 8 #define REG_EXTINT_VBUSOC2_INT_EN_MSK (0x1ul << REG_EXTINT_VBUSOC2_INT_EN_POS) #define REG_EXTINT_VBUSOC2_INT_EN_SET(num) (((num) << REG_EXTINT_VBUSOC2_INT_EN_POS ) & REG_EXTINT_VBUSOC2_INT_EN_MSK) #define REG_EXTINT_VBUSOC2_INT_MASK_POS 9 #define REG_EXTINT_VBUSOC2_INT_MASK_MSK (0x1ul << REG_EXTINT_VBUSOC2_INT_MASK_POS) #define REG_EXTINT_VBUSOC2_INT_MASK_SET(num) (((num) << REG_EXTINT_VBUSOC2_INT_MASK_POS ) & REG_EXTINT_VBUSOC2_INT_MASK_MSK) #define REG_EXTINT_VIN1_UVLO_INT_CLR_POS 0 #define REG_EXTINT_VIN1_UVLO_INT_CLR_MSK (0x1ul << REG_EXTINT_VIN1_UVLO_INT_CLR_POS) #define REG_EXTINT_VIN1_UVLO_INT_CLR_SET(num) (((num) << REG_EXTINT_VIN1_UVLO_INT_CLR_POS ) & REG_EXTINT_VIN1_UVLO_INT_CLR_MSK) #define REG_EXTINT_VIN1_UVLO_INT_EN_POS 8 #define REG_EXTINT_VIN1_UVLO_INT_EN_MSK (0x1ul << REG_EXTINT_VIN1_UVLO_INT_EN_POS) #define REG_EXTINT_VIN1_UVLO_INT_EN_SET(num) (((num) << REG_EXTINT_VIN1_UVLO_INT_EN_POS ) & REG_EXTINT_VIN1_UVLO_INT_EN_MSK) #define REG_EXTINT_VIN1_UVLO_INT_MASK_POS 9 #define REG_EXTINT_VIN1_UVLO_INT_MASK_MSK (0x1ul << REG_EXTINT_VIN1_UVLO_INT_MASK_POS) #define REG_EXTINT_VIN1_UVLO_INT_MASK_SET(num) (((num) << REG_EXTINT_VIN1_UVLO_INT_MASK_POS ) & REG_EXTINT_VIN1_UVLO_INT_MASK_MSK) #define REG_EXTINT_VIN2_UVLO_INT_CLR_POS 0 #define REG_EXTINT_VIN2_UVLO_INT_CLR_MSK (0x1ul << REG_EXTINT_VIN2_UVLO_INT_CLR_POS) #define REG_EXTINT_VIN2_UVLO_INT_CLR_SET(num) (((num) << REG_EXTINT_VIN2_UVLO_INT_CLR_POS ) & REG_EXTINT_VIN2_UVLO_INT_CLR_MSK) #define REG_EXTINT_VIN2_UVLO_INT_EN_POS 8 #define REG_EXTINT_VIN2_UVLO_INT_EN_MSK (0x1ul << REG_EXTINT_VIN2_UVLO_INT_EN_POS) #define REG_EXTINT_VIN2_UVLO_INT_EN_SET(num) (((num) << REG_EXTINT_VIN2_UVLO_INT_EN_POS ) & REG_EXTINT_VIN2_UVLO_INT_EN_MSK) #define REG_EXTINT_VIN2_UVLO_INT_MASK_POS 9 #define REG_EXTINT_VIN2_UVLO_INT_MASK_MSK (0x1ul << REG_EXTINT_VIN2_UVLO_INT_MASK_POS) #define REG_EXTINT_VIN2_UVLO_INT_MASK_SET(num) (((num) << REG_EXTINT_VIN2_UVLO_INT_MASK_POS ) & REG_EXTINT_VIN2_UVLO_INT_MASK_MSK) #endif /*__EXTINT_DEFINE_H__*/