#ifndef __MISC_DEFINE_H__ #define __MISC_DEFINE_H__ //----------------------------------------------------------------------------- // misc registers definition //----------------------------------------------------------------------------- #pragma anon_unions //----------------------------------------------------------------------------- // registers structures typedef struct { uint32_t enable:1; uint32_t reserved_31_1:31; } REG_misc_pwd0_cfg_bitfiled_TypeDef; typedef struct { union { __IO REG_misc_pwd0_cfg_bitfiled_TypeDef bf;//bitfiled __IO uint32_t word; }; } REG_misc_pwd0_cfg_TypeDef; typedef struct { uint32_t width:14; uint32_t reserved_14_14:1; uint32_t level:1; uint32_t reserved_31_16:16; } REG_misc_pwd0_val_bitfiled_TypeDef; typedef struct { union { __IO REG_misc_pwd0_val_bitfiled_TypeDef bf;//bitfiled __IO uint32_t word; }; } REG_misc_pwd0_val_TypeDef; typedef struct { uint32_t enable:1; uint32_t reserved_31_1:31; } REG_misc_pwd1_cfg_bitfiled_TypeDef; typedef struct { union { __IO REG_misc_pwd1_cfg_bitfiled_TypeDef bf;//bitfiled __IO uint32_t word; }; } REG_misc_pwd1_cfg_TypeDef; typedef struct { uint32_t width:14; uint32_t reserved_14_14:1; uint32_t level:1; uint32_t reserved_31_16:16; } REG_misc_pwd1_val_bitfiled_TypeDef; typedef struct { union { __IO REG_misc_pwd1_val_bitfiled_TypeDef bf;//bitfiled __IO uint32_t word; }; } REG_misc_pwd1_val_TypeDef; typedef struct { uint32_t time:9; uint32_t start:1; uint32_t reserved_15_10:6; uint32_t cnt:16; } REG_misc_vd_freq_calc_bitfiled_TypeDef; typedef struct { union { __IO REG_misc_vd_freq_calc_bitfiled_TypeDef bf;//bitfiled __IO uint32_t word; }; } REG_misc_vd_freq_calc_TypeDef; typedef struct { uint32_t high_width:9; uint32_t reserved_15_9:7; uint32_t low_width:11; uint32_t reserved_31_27:5; } REG_misc_vd_ls_comp_bitfiled_TypeDef; typedef struct { union { __IO REG_misc_vd_ls_comp_bitfiled_TypeDef bf;//bitfiled __IO uint32_t word; }; } REG_misc_vd_ls_comp_TypeDef; typedef struct { uint32_t sample_on_high_en:1; uint32_t sample_on_low_en:1; uint32_t reserved_7_2:6; uint32_t blank_time:7; uint32_t reserved_15_15:1; uint32_t sample_time:3; uint32_t reserved_31_19:13; } REG_misc_vd_bitfiled_TypeDef; typedef struct { union { __IO REG_misc_vd_bitfiled_TypeDef bf;//bitfiled __IO uint32_t word; }; } REG_misc_vd_TypeDef; typedef struct { uint32_t sel:2; uint32_t reserved_2_2:1; uint32_t vdw_cst:3; uint32_t reserved_15_6:10; uint32_t vdw_cnt:16; } REG_misc_vd_dbg_bitfiled_TypeDef; typedef struct { union { __IO REG_misc_vd_dbg_bitfiled_TypeDef bf;//bitfiled __IO uint32_t word; }; } REG_misc_vd_dbg_TypeDef; typedef struct { uint32_t ac_off_flag:1; uint32_t ac_off_cnt_dis:1; uint32_t rst_cnt_sel:1; uint32_t vd_rst_flag:1; uint32_t reserved_31_4:28; } REG_misc_vd_cnt_bitfiled_TypeDef; typedef struct { union { __IO REG_misc_vd_cnt_bitfiled_TypeDef bf;//bitfiled __IO uint32_t word; }; } REG_misc_vd_cnt_TypeDef; typedef struct { uint32_t tdring_sel:2; uint32_t reserved_31_2:30; } REG_misc_vd_cfg_bitfiled_TypeDef; typedef struct { union { __IO REG_misc_vd_cfg_bitfiled_TypeDef bf;//bitfiled __IO uint32_t word; }; } REG_misc_vd_cfg_TypeDef; //----------------------------------------------------------------------------- //----------------------------------------------------------------------------- // memory map #define REG_MISC_PWD0_CFG_BASE 0X4000F800 #define REG_MISC_PWD0_VAL_BASE 0X4000F804 #define REG_MISC_PWD1_CFG_BASE 0X4000F808 #define REG_MISC_PWD1_VAL_BASE 0X4000F80C #define REG_MISC_VD_FREQ_CALC_BASE 0X4000F820 #define REG_MISC_VD_LS_COMP_BASE 0X4000F824 #define REG_MISC_VD_BASE 0X4000F828 #define REG_MISC_VD_DBG_BASE 0X4000F82C #define REG_MISC_VD_CNT_BASE 0X4000F830 #define REG_MISC_VD_CFG_BASE 0X4000F834 //----------------------------------------------------------------------------- //----------------------------------------------------------------------------- // declaration #define REG_MISC_PWD0_CFG ((REG_misc_pwd0_cfg_TypeDef *) REG_MISC_PWD0_CFG_BASE) #define REG_MISC_PWD0_VAL ((REG_misc_pwd0_val_TypeDef *) REG_MISC_PWD0_VAL_BASE) #define REG_MISC_PWD1_CFG ((REG_misc_pwd1_cfg_TypeDef *) REG_MISC_PWD1_CFG_BASE) #define REG_MISC_PWD1_VAL ((REG_misc_pwd1_val_TypeDef *) REG_MISC_PWD1_VAL_BASE) #define REG_MISC_VD_FREQ_CALC ((REG_misc_vd_freq_calc_TypeDef *) REG_MISC_VD_FREQ_CALC_BASE) #define REG_MISC_VD_LS_COMP ((REG_misc_vd_ls_comp_TypeDef *) REG_MISC_VD_LS_COMP_BASE) #define REG_MISC_VD ((REG_misc_vd_TypeDef *) REG_MISC_VD_BASE) #define REG_MISC_VD_DBG ((REG_misc_vd_dbg_TypeDef *) REG_MISC_VD_DBG_BASE) #define REG_MISC_VD_CNT ((REG_misc_vd_cnt_TypeDef *) REG_MISC_VD_CNT_BASE) #define REG_MISC_VD_CFG ((REG_misc_vd_cfg_TypeDef *) REG_MISC_VD_CFG_BASE) //----------------------------------------------------------------------------- //----------------------------------------------------------------------------- // set #define REG_MISC_PWD0_CFG_ENABLE_POS 0 #define REG_MISC_PWD0_CFG_ENABLE_MSK (0x1ul << REG_MISC_PWD0_CFG_ENABLE_POS) #define REG_MISC_PWD0_CFG_ENABLE_SET(num) (((num) << REG_MISC_PWD0_CFG_ENABLE_POS ) & REG_MISC_PWD0_CFG_ENABLE_MSK) #define REG_MISC_PWD1_CFG_ENABLE_POS 0 #define REG_MISC_PWD1_CFG_ENABLE_MSK (0x1ul << REG_MISC_PWD1_CFG_ENABLE_POS) #define REG_MISC_PWD1_CFG_ENABLE_SET(num) (((num) << REG_MISC_PWD1_CFG_ENABLE_POS ) & REG_MISC_PWD1_CFG_ENABLE_MSK) #define REG_MISC_VD_FREQ_CALC_TIME_POS 0 #define REG_MISC_VD_FREQ_CALC_TIME_MSK (0x9ul << REG_MISC_VD_FREQ_CALC_TIME_POS) #define REG_MISC_VD_FREQ_CALC_TIME_SET(num) (((num) << REG_MISC_VD_FREQ_CALC_TIME_POS ) & REG_MISC_VD_FREQ_CALC_TIME_MSK) #define REG_MISC_VD_FREQ_CALC_START_POS 9 #define REG_MISC_VD_FREQ_CALC_START_MSK (0x1ul << REG_MISC_VD_FREQ_CALC_START_POS) #define REG_MISC_VD_FREQ_CALC_START_SET(num) (((num) << REG_MISC_VD_FREQ_CALC_START_POS ) & REG_MISC_VD_FREQ_CALC_START_MSK) #define REG_MISC_VD_SAMPLE_ON_HIGH_EN_POS 0 #define REG_MISC_VD_SAMPLE_ON_HIGH_EN_MSK (0x1ul << REG_MISC_VD_SAMPLE_ON_HIGH_EN_POS) #define REG_MISC_VD_SAMPLE_ON_HIGH_EN_SET(num) (((num) << REG_MISC_VD_SAMPLE_ON_HIGH_EN_POS ) & REG_MISC_VD_SAMPLE_ON_HIGH_EN_MSK) #define REG_MISC_VD_SAMPLE_ON_LOW_EN_POS 1 #define REG_MISC_VD_SAMPLE_ON_LOW_EN_MSK (0x1ul << REG_MISC_VD_SAMPLE_ON_LOW_EN_POS) #define REG_MISC_VD_SAMPLE_ON_LOW_EN_SET(num) (((num) << REG_MISC_VD_SAMPLE_ON_LOW_EN_POS ) & REG_MISC_VD_SAMPLE_ON_LOW_EN_MSK) #define REG_MISC_VD_BLANK_TIME_POS 8 #define REG_MISC_VD_BLANK_TIME_MSK (0x7ul << REG_MISC_VD_BLANK_TIME_POS) #define REG_MISC_VD_BLANK_TIME_SET(num) (((num) << REG_MISC_VD_BLANK_TIME_POS ) & REG_MISC_VD_BLANK_TIME_MSK) #define REG_MISC_VD_SAMPLE_TIME_POS 16 #define REG_MISC_VD_SAMPLE_TIME_MSK (0x3ul << REG_MISC_VD_SAMPLE_TIME_POS) #define REG_MISC_VD_SAMPLE_TIME_SET(num) (((num) << REG_MISC_VD_SAMPLE_TIME_POS ) & REG_MISC_VD_SAMPLE_TIME_MSK) #define REG_MISC_VD_DBG_SEL_POS 0 #define REG_MISC_VD_DBG_SEL_MSK (0x2ul << REG_MISC_VD_DBG_SEL_POS) #define REG_MISC_VD_DBG_SEL_SET(num) (((num) << REG_MISC_VD_DBG_SEL_POS ) & REG_MISC_VD_DBG_SEL_MSK) #define REG_MISC_VD_CNT_AC_OFF_CNT_DIS_POS 1 #define REG_MISC_VD_CNT_AC_OFF_CNT_DIS_MSK (0x1ul << REG_MISC_VD_CNT_AC_OFF_CNT_DIS_POS) #define REG_MISC_VD_CNT_AC_OFF_CNT_DIS_SET(num) (((num) << REG_MISC_VD_CNT_AC_OFF_CNT_DIS_POS ) & REG_MISC_VD_CNT_AC_OFF_CNT_DIS_MSK) #define REG_MISC_VD_CNT_RST_CNT_SEL_POS 2 #define REG_MISC_VD_CNT_RST_CNT_SEL_MSK (0x1ul << REG_MISC_VD_CNT_RST_CNT_SEL_POS) #define REG_MISC_VD_CNT_RST_CNT_SEL_SET(num) (((num) << REG_MISC_VD_CNT_RST_CNT_SEL_POS ) & REG_MISC_VD_CNT_RST_CNT_SEL_MSK) #define REG_MISC_VD_CFG_TDRING_SEL_POS 0 #define REG_MISC_VD_CFG_TDRING_SEL_MSK (0x2ul << REG_MISC_VD_CFG_TDRING_SEL_POS) #define REG_MISC_VD_CFG_TDRING_SEL_SET(num) (((num) << REG_MISC_VD_CFG_TDRING_SEL_POS ) & REG_MISC_VD_CFG_TDRING_SEL_MSK) //----------------------------------------------------------------------------- #endif /*__MISC_DEFINE_H__*/