#ifndef __VD_DEFINE_H__
#define __VD_DEFINE_H__
//-----------------------------------------------------------------------------
// vd registers definition                            
//-----------------------------------------------------------------------------
#pragma anon_unions

//-----------------------------------------------------------------------------
// registers structures
typedef struct
{
	//vd low side comparator output high pulse width 41.6ns / lsb,max 21.33us
	uint32_t high_width:9;
	//vd low side comparator output low pulse width 41.6ns / lsb,max21.33us
	uint32_t low_width:9;
	//vd low side comparator output high pulse rising edge interval time                                                                                                                      1. 12-bit with 24mhz clock (41.6ns/lsb) max 170us
	//2. it can be read by mcu
	uint32_t pwm:12;
	//vd low side comparator output high pulse rising edge interval time,time out flag,max170us,canbe  write 1 clr by mcu
	uint32_t pwm_to_flag:1;
	uint32_t reserved_31_31:1;
} REG_vd_ls_comp_bitfiled_TypeDef;

typedef struct
{
	union {
	__IO	REG_vd_ls_comp_bitfiled_TypeDef bf;//bitfiled
	__IO	uint32_t word;
	};
} REG_vd_ls_comp_TypeDef;

typedef struct
{
	//register-optional vd rising edge blanking time,41.6ns / lsb,max:2.67us
	uint32_t blank_time:6;
	uint32_t reserved_31_6:26;
} REG_vd_ls_bitfiled_TypeDef;

typedef struct
{
	union {
	__IO	REG_vd_ls_bitfiled_TypeDef bf;//bitfiled
	__IO	uint32_t word;
	};
} REG_vd_ls_TypeDef;

typedef struct
{
	//debug signal select
	uint32_t sel:2;
	uint32_t reserved_2_2:1;
	//vd width fsm
	uint32_t vdw_cst:2;
	uint32_t reserved_15_5:11;
	//vd width counter
	uint32_t vdw_cnt:16;
} REG_vd_dbg_bitfiled_TypeDef;

typedef struct
{
	union {
	__IO	REG_vd_dbg_bitfiled_TypeDef bf;//bitfiled
	__IO	uint32_t word;
	};
} REG_vd_dbg_TypeDef;

typedef struct
{
	//1'b1:ac off counter 100ms flag, canbe  write 1 clr by mcu
	uint32_t flag:1;
	//1=disable ac_off
	uint32_t dis:1;
	uint32_t reserved_31_2:30;
} REG_vd_ac_off_bitfiled_TypeDef;

typedef struct
{
	union {
	__IO	REG_vd_ac_off_bitfiled_TypeDef bf;//bitfiled
	__IO	uint32_t word;
	};
} REG_vd_ac_off_TypeDef;

typedef struct
{
	//vd reset counter select
	//0: 10ms counter overflow
	//1:100ms counter overflow
	uint32_t cnt_sel:1;
	//1'b1:vd rst counter 10ms/100ms flag or soft rst  ,canbe  write 1 clr by mcu
	uint32_t flag:1;
	//0:soft rst disable ; 1'b1:vd soft rst
	uint32_t soft:1;
	uint32_t reserved_31_3:29;
} REG_vd_rst_bitfiled_TypeDef;

typedef struct
{
	union {
	__IO	REG_vd_rst_bitfiled_TypeDef bf;//bitfiled
	__IO	uint32_t word;
	};
} REG_vd_rst_TypeDef;

typedef struct
{
	//2'b11:ring comparator enbale delay 750ns after vd < vth_sh
	//2'b10:ring comparator enbale delay 500ns after vd < vth_sh
	//2'b01:ring comparator enbale delay 250ns after vd < vth_sh
	//2'b00: disable delay
	uint32_t tdring_sel:2;
	uint32_t reserved_31_2:30;
} REG_vd_cfg_bitfiled_TypeDef;

typedef struct
{
	union {
	__IO	REG_vd_cfg_bitfiled_TypeDef bf;//bitfiled
	__IO	uint32_t word;
	};
} REG_vd_cfg_TypeDef;

//-----------------------------------------------------------------------------
// memory map
#define REG_VD_LS_COMP_BASE                                                    0x4000E800
#define REG_VD_LS_BASE                                                         0x4000E804
#define REG_VD_DBG_BASE                                                        0x4000E808
#define REG_VD_AC_OFF_BASE                                                     0x4000E810
#define REG_VD_RST_BASE                                                        0x4000E814
#define REG_VD_CFG_BASE                                                        0x4000E818
//-----------------------------------------------------------------------------
// declaration
#define REG_VD_LS_COMP                           ((REG_vd_ls_comp_TypeDef                 *) REG_VD_LS_COMP_BASE                      )
#define REG_VD_LS                                ((REG_vd_ls_TypeDef                      *) REG_VD_LS_BASE                           )
#define REG_VD_DBG                               ((REG_vd_dbg_TypeDef                     *) REG_VD_DBG_BASE                          )
#define REG_VD_AC_OFF                            ((REG_vd_ac_off_TypeDef                  *) REG_VD_AC_OFF_BASE                       )
#define REG_VD_RST                               ((REG_vd_rst_TypeDef                     *) REG_VD_RST_BASE                          )
#define REG_VD_CFG                               ((REG_vd_cfg_TypeDef                     *) REG_VD_CFG_BASE                          )
//-----------------------------------------------------------------------------
// set 
#define REG_VD_LS_BLANK_TIME_POS                            0
#define REG_VD_LS_BLANK_TIME_MSK                           (0x3Ful << REG_VD_LS_BLANK_TIME_POS)
#define REG_VD_LS_BLANK_TIME_SET(num)                      (((num) << REG_VD_LS_BLANK_TIME_POS                          ) & REG_VD_LS_BLANK_TIME_MSK)

#define REG_VD_DBG_SEL_POS                                  0
#define REG_VD_DBG_SEL_MSK                                 (0x3ul << REG_VD_DBG_SEL_POS)
#define REG_VD_DBG_SEL_SET(num)                            (((num) << REG_VD_DBG_SEL_POS                                ) & REG_VD_DBG_SEL_MSK)

#define REG_VD_AC_OFF_DIS_POS                               1
#define REG_VD_AC_OFF_DIS_MSK                              (0x1ul << REG_VD_AC_OFF_DIS_POS)
#define REG_VD_AC_OFF_DIS_SET(num)                         (((num) << REG_VD_AC_OFF_DIS_POS                             ) & REG_VD_AC_OFF_DIS_MSK)

#define REG_VD_RST_CNT_SEL_POS                              0
#define REG_VD_RST_CNT_SEL_MSK                             (0x1ul << REG_VD_RST_CNT_SEL_POS)
#define REG_VD_RST_CNT_SEL_SET(num)                        (((num) << REG_VD_RST_CNT_SEL_POS                            ) & REG_VD_RST_CNT_SEL_MSK)

#define REG_VD_RST_SOFT_POS                                 2
#define REG_VD_RST_SOFT_MSK                                (0x1ul << REG_VD_RST_SOFT_POS)
#define REG_VD_RST_SOFT_SET(num)                           (((num) << REG_VD_RST_SOFT_POS                               ) & REG_VD_RST_SOFT_MSK)

#define REG_VD_CFG_TDRING_SEL_POS                           0
#define REG_VD_CFG_TDRING_SEL_MSK                          (0x3ul << REG_VD_CFG_TDRING_SEL_POS)
#define REG_VD_CFG_TDRING_SEL_SET(num)                     (((num) << REG_VD_CFG_TDRING_SEL_POS                         ) & REG_VD_CFG_TDRING_SEL_MSK)

#endif /*__VD_DEFINE_H__*/