/** ****************************************************************************** * @copyright Copyright (C), 2016-2022, ConvenientPower. Co., Ltd. * @file comp_dma.h * @version 1.0 * @author qing.cheng * @date 2022-11-01 * @brief Header file of COMP_DMA_H module. ****************************************************************************** */ #ifndef _COMP_DMA_H_ #define _COMP_DMA_H_ /******************************************* DMA内存排布： dma通道信息分布(2组每组4个通道)： //PORT0 CH0:0x20000000--------0x2000000F-----PD0--TX CH1:0x20000010--------0x2000002F-----PD0--RX CH2:0x20000020--------0x20000030-----DPDN0--RX CH3:0x20000030--------0x20000040-----DPDN0--TX SRAM映射地址 //PORT0 0x20000040-------------0x2000007C----PD0--RX 0x2000007C-------------0x200000B8----PD0--TX 0x200000B8-------------0x200000F8----DPDN0--RX 0x200000F8-------------0x2000013C----DPDN0--TX //PORT1 0x2000013C-------------0x20000178----PD1--RX 0x20000178-------------0x200001B4----PD1--TX 0x200001B4-------------0x200001F4----DPDN1--RX //PORT1 CH0:0x20000200--------0x20000210-----PD0--TX CH1:0x20000210--------0x20000220-----PD0--RX CH2:0x20000220--------0x20000230-----DPDN0--RX CH3:0x20000230--------0x20000240-----DPDN0--TX 0x20000240-------------0x20000288----DPDN1--TX ************************************************/ #include "core_comm.h" #include "drv_dma.h" #define PD_DMA_MAX_BUFF_SIZE (60) #define UFCS_DMA_RX_MAX_BUFF_SIZE (64) #define UFCS_DMA_TX_MAX_BUFF_SIZE (68) #define TX_CONFIG_WORD 0xc0400000 #define RX_CONFIG_WORD 0x0c400000 #define DMA_CFG_BASE_ADDR_POS 9 #define DMA_CFG_BASE_ADDR_MASK (0x7F << 9) #define DMA_CFG_ADDR_CHN_POS 4 #define DMA_ADDR_WORD_SET(cfg_buf, addr)\ do{\ cfg_buf[0] = (uint32_t)(addr) & 0xFF;\ cfg_buf[1] = ((uint32_t)(addr) >> 8) & 0xFF;\ cfg_buf[2] = ((uint32_t)(addr) >> 16) & 0xFF;\ cfg_buf[3] = ((uint32_t)(addr) >> 24) & 0xFF;\ }while(0) #define DMA_CFG_WORD_SET(cfg_buf, dma_buf_len, ctrl_byte)\ do{\ cfg_buf[0] = 0x00;\ cfg_buf[1] = 0x00;\ cfg_buf[2] = dma_buf_len;\ cfg_buf[3] = ctrl_byte;\ }while(0) #define DMA0_CHN_PD_TX 0 #define DMA0_CHN_PD_RX 1 #define DMA0_CHN_PRL_RX 2 #define DMA0_CHN_PRL_TX 3 #define DMA0_CHN_ADC 4 /*not used*/ #define DMA1_CHN_PD_TX 0 #define DMA1_CHN_PD_RX 1 #define DMA1_CHN_PRL_RX 2 #define DMA1_CHN_PRL_TX 3 #define DMA1_CHN_ADC 4 /*not used*/ // must be align with 0x1FF(start with bit9) #define DMA_CFG_BASE_ADDR (uint32_t)0x20000000 #define DMA_DATA_BASE_ADDR (uint32_t)(DMA_CFG_BASE_ADDR + ((DMA0_CHN_PRL_TX + 1 ) << DMA_CFG_ADDR_CHN_POS)) // start from unused cfg space, chn 7~chn31 #define DMA1_CFG_BASE_ADDR (uint32_t)0x20000200 #define DMA1_DATA_BASE_ADDR (uint32_t)(DMA1_CFG_BASE_ADDR + ((DMA1_CHN_PRL_TX + 1) << DMA_CFG_ADDR_CHN_POS)) /*************************PORT0***********************************/ /**********************************PD0*****************/ #define PD0_RX_DATA_REG_ADDR ((uint32_t)REG_PD0_DATA_BASE+1) #define PD0_TX_DATA_REG_ADDR ((uint32_t)REG_PD0_DATA_BASE) #define PD0_RX_SRAM_MCU_ADDR (DMA_DATA_BASE_ADDR + 0) #define PD0_TX_SRAM_MCU_ADDR (PD0_RX_SRAM_MCU_ADDR + PD_DMA_MAX_BUFF_SIZE) #define PD0_RX_SRAM_AHB_ADDR ((uint32_t)0x00000000 + PD0_RX_SRAM_MCU_ADDR) #define PD0_TX_SRAM_AHB_ADDR ((uint32_t)0x00000000 + PD0_TX_SRAM_MCU_ADDR) /*****************************DPDN0**********************/ #define DPDN0_RX_SRAM_MCU_ADDR (PD0_TX_SRAM_MCU_ADDR + PD_DMA_MAX_BUFF_SIZE) #define DPDN0_TX_SRAM_MCU_ADDR (DPDN0_RX_SRAM_MCU_ADDR + UFCS_DMA_RX_MAX_BUFF_SIZE) #define DPDN0_RX_SRAM_AHB_ADDR ((uint32_t)0x00000000 + DPDN0_RX_SRAM_MCU_ADDR) #define DPDN0_TX_SRAM_AHB_ADDR ((uint32_t)0x00000000 + DPDN0_TX_SRAM_MCU_ADDR) #define DPDN0_UFCS_TX_ACK_SRAM_AHB_ADDR DPDN0_TX_SRAM_AHB_ADDR + 64 ////////////////////////////////////////////////// UFCS0 ////////////////////////////////////////////// #define UFCS0_RX_DATA_REG_ADDR ((uint32_t)REG_UFCS_RX_DAT_BASE) #define UFCS0_TX_DATA_REG_ADDR ((uint32_t)REG_UFCS_TX_DAT_BASE) ////////////////////////////////////////////////// SCP0 ////////////////////////////////////////////// #define SCP0_RX_DATA_REG_ADDR ((uint32_t)REG_SCP_RX_DATA_BASE) #define SCP0_TX_DATA_REG_ADDR ((uint32_t)REG_SCP_TX_DATA_BASE) /*************************PORT1***********************************/ /**********************************PD1*****************/ #define PD1_RX_DATA_REG_ADDR ((uint32_t)REG_PD_DATA_BASE+1) #define PD1_TX_DATA_REG_ADDR ((uint32_t)REG_PD_DATA_BASE) #define PD1_RX_SRAM_MCU_ADDR (DPDN0_TX_SRAM_AHB_ADDR + UFCS_DMA_TX_MAX_BUFF_SIZE) #define PD1_TX_SRAM_MCU_ADDR (PD1_RX_SRAM_MCU_ADDR + PD_DMA_MAX_BUFF_SIZE) #define PD1_RX_SRAM_AHB_ADDR ((uint32_t)0x00000000 + PD1_RX_SRAM_MCU_ADDR) #define PD1_TX_SRAM_AHB_ADDR ((uint32_t)0x00000000 + PD1_TX_SRAM_MCU_ADDR) /*****************************DPDN1**********************/ #define DPDN1_RX_SRAM_MCU_ADDR (PD1_TX_SRAM_MCU_ADDR + PD_DMA_MAX_BUFF_SIZE) /**/ #define DPDN1_TX_SRAM_MCU_ADDR (0x00000000 + DMA1_DATA_BASE_ADDR) #define DPDN1_RX_SRAM_AHB_ADDR ((uint32_t)0x00000000 + DPDN1_RX_SRAM_MCU_ADDR) #define DPDN1_TX_SRAM_AHB_ADDR ((uint32_t)0x00000000 + DPDN1_TX_SRAM_MCU_ADDR) #define DPDN1_UFCS_TX_ACK_SRAM_AHB_ADDR DPDN1_TX_SRAM_AHB_ADDR + 64 ////////////////////////////////////////////////// UFCS1 ////////////////////////////////////////////// #define UFCS1_RX_DATA_REG_ADDR ((uint32_t)REG_UFCS1_RX_DAT_BASE) #define UFCS1_TX_DATA_REG_ADDR ((uint32_t)REG_UFCS1_TX_DAT_BASE) ////////////////////////////////////////////////// SCP1 ////////////////////////////////////////////// #define SCP1_RX_DATA_REG_ADDR ((uint32_t)REG_SCP1_RX_DATA_BASE) #define SCP1_TX_DATA_REG_ADDR ((uint32_t)REG_SCP1_TX_DATA_BASE) /******port0**********/ extern uint8_t pd0_dma_rx_buffer[PD_DMA_MAX_BUFF_SIZE]; extern uint8_t pd0_dma_tx_buffer[PD_DMA_MAX_BUFF_SIZE]; extern uint32_t pd0_dma_tx_cfg[4]; extern uint8_t dpdn0_dma_rx_buffer[UFCS_DMA_RX_MAX_BUFF_SIZE]; extern uint8_t dpdn0_dma_tx_buffer[UFCS_DMA_TX_MAX_BUFF_SIZE]; extern uint32_t dpdn0_dma_tx_cfg[4]; /******port1**********/ extern uint8_t pd1_dma_rx_buffer[PD_DMA_MAX_BUFF_SIZE]; extern uint8_t pd1_dma_tx_buffer[PD_DMA_MAX_BUFF_SIZE]; extern uint32_t pd1_dma_tx_cfg[4]; extern uint8_t dpdn1_dma_rx_buffer[UFCS_DMA_RX_MAX_BUFF_SIZE]; extern uint8_t dpdn1_dma_tx_buffer[UFCS_DMA_TX_MAX_BUFF_SIZE]; extern uint32_t dpdn1_dma_tx_cfg[4]; /** * @brief comp_dma_pd_set_tx_size * @note * @param port 0/1 * @param n: send len size * @retval None */ void comp_dma_pd_set_tx_size(uint8_t port, uint16_t n); /** * @brief comp_dma_dpdn_set_tx_size * @note * @param port 0/1 * @param n: send len size * @retval None */ void comp_dma_dpdn_set_tx_size(uint8_t port, uint16_t n); /** * @brief comp_dma_dpdn_set_tx_size * @note * @param port 0/1 * @retval recv num */ uint8_t comp_dma_dpdn_get_recv_size(uint8_t port); /** * @brief init dma module & chn * @note * @param port 0/1 * @retval None */ void comp_dma_init(uint8_t port); /* * @brief comp_dma_pd_init * @param port 0/1 * @note NULL * @retval NULL */ void comp_dma_pd_init(uint8_t port); /* * @brief comp_dma_ufcs_init * @param port 0/1 * @note NULL * @retval NULL */ void comp_dma_ufcs_init(uint8_t port); /* * @brief comp_dma_scp_init * @param port 0/1 * @note NULL * @retval NULL */ void comp_dma_scp_init(uint8_t port); #endif