/**
 ******************************************************************************
 * @copyright Copyright (C), 2016-2022, ConvenientPower. Co., Ltd.
 * @file    drv_ufcs_phy.h
 * @version 1.0
 * @author  qing.cheng
 * @date    2022-11-04
 * @brief   Header file of DRV_UFCS_PHY_H module.
 ******************************************************************************
 */
#ifndef _DRV_UFCS_PHY_H_
#define _DRV_UFCS_PHY_H_

#include "core_comm.h"
#include "ufcs_define.h"
#include "ufcs1_define.h"
#include "pwd_define.h"
#include "extint_define.h"

//pkt_end	0	RX packet end interrupt, write 1 to clear this interrupt source
//pkt_crc_pass	1	RX packet CRC verify pass interrupt, write 1 to clear this interrupt source
//pkt_crc_fail	2	RX packet CRC verify fail interrupt, write 1 to clear this interrupt source
//pkt_type_err	3	RX packet, message type is not 000/001/010. write 1 to clear this interrupt source
//pkt_len_err	4	RX packet, message length is 0. write 1 to clear this interrupt source
//tr_err	5	training byte baudrate not within the spec range/data not 0xAA, write 1 to clear this interrupt source
//infrm_to	6	RX inside data frame timer out interrupt, write 1 to clear this interrupt source
//btwfrm_to	7	RX between data frame timer out interrupt, write 1 to clear this interrupt source
//src_hwrst	8	received hardware reset, only check at the time of rxpkt_end

#define UFCS_RX_INT_PKT_END                 0x01//0
#define UFCS_RX_INT_PKT_CRC_PASS            0x02//1
#define UFCS_RX_INT_PKT_CRC_FAIL            0x04//2
#define UFCS_RX_INT_PKT_TYPE_ERROR          0x08//3
#define UFCS_RX_INT_PKT_LEN_ERROR           0x10//4
#define UFCS_RX_INT_TRANINING_ERROR         0x20//5
#define UFCS_RX_INT_INFRM_TO                0x40//6
#define UFCS_RX_INT_BTWFRM_TO               0x80//7
#define UFCS_RX_INT_SRC_HW_RESET            0x100//8


//pkt_end	0	TX packet end interrupt, write 1 to clear this interrupt source
//fifo_empty	1	TX FIFO empty interrupt, , write 1 to clear this interrupt source,  will be set when dptr >= almemp_tx_th
//fifo_almfull	2	TX FIFO  get almfull_rx_th byte space left, , write 1 to clear this interrupt source, will be set when dtpr >=16-almfull_tx_th
//cble_hwrst	3	cable hardware reset transmist done
//snk_hwrst	4	sink hardware reset transmit done

#define UFCS_TX_INT_PKT_END                 0x01
#define UFCS_TX_INT_CBLE_HW_RESET           0x02
#define UFCS_TX_INT_SNK_HW_RESET            0x04

/*********************************UFCS0*********************************/
/*
* @brief  1=start send packet at the time of this bit toggle from "0" to "1", if the tx fifo is not empty, and this bit is set as high.
* @param    en:1
* @retval   null
*/
#define drv_ufcs0_ctrl_tx_enable(x) \
        do{\
            REG_UFCS_CTRL->bf.tx_enable = x;\
        }while(0)


/*
* @brief  //1=start receive the rx packet data, effective only when the rx fifo is no full
	//packet aligned: hardware clear after packet rx done, software set for new packet
* @param    en:1
* @retval   null
*/
#define drv_ufcs0_ctrl_rx_enable(x) \
        do{\
            REG_UFCS_CTRL->bf.rx_enable = x;\
        }while(0)

/*
* @brief 1: hw clear rx_enable at the time of rxpkt_end, software set rx_enable; 0: sw control rx_enable directly
* @param    en:1
* @retval   null
*/
#define drv_ufcs0_ctrl_rx_stop_en(x) \
        do{\
            REG_UFCS_CTRL->bf.rxstop_en = x;\
        }while(0)

/*
* @brief 1:  send cable hardware reset command, only valid when the "txpkt_end" is high level, set by software, clear by hw;
* @param    en:1
* @retval   null
*/
#define drv_ufcs0_ctrl_hw_reset_cable(x) \
        do{\
            REG_UFCS_CTRL->bf.hwrst_cble = x;\
        }while(0)

/*
* @brief //send sink hardware reset command, only valid when the "txpkt_end" is high level, if tx packet not end status, miss this command
* @param    en:1
* @retval   null
*/

#define drv_ufcs0_ctrl_hw_reset_tx(x) \
        do{\
            REG_UFCS_CTRL->bf.hwrst_tx = x;\
        }while(0)


/*
* @brief
   //source stop tx, set tx(d-) as tri-state, if this bit is high, d- pin output is disabled
//all the following condition is met, then the stop command is not effect
//1 tx packet is processing
//2. hwrst is processing
* @param    en:1
* @retval   null
*/
#define drv_ufcs0_ctrl_stop_src_tx(x) \
        do{\
            REG_UFCS_CTRL->bf.stop_tx = x;\
        }while(0)


/*
* @brief /1=reset just the ufcs phy logic for both the ufcs phy transmitter and receiver.
* @param    en:1
* @retval   null
*/
#define drv_ufcs0_reset_logic() \
        do{\
            REG_UFCS_RESET->bf.reset_logic = 1;\
        }while(0)


/*
* @brief /1=reset just the ufcs phy logic for both the ufcs phy transmitter and receiver.
* @param    en:1
* @retval   null
*/
#define drv_ufcs0_reset_all() \
        do{\
            REG_UFCS_RESET->bf.reset_all = 1;\
        }while(0)

/*
* @brief //clear rx fifo, after write 1, will be cleared
* @param    en:1
* @retval   null
*/
#define drv_ufcs0_reset_clr_rx_fifo() \
        do{\
            REG_UFCS_RESET->bf.rxfifo_clr = 1;\
        }while(0)

/*
* @brief //tx baudrate configure
//0: 115200; 1:57600; 2:38400; 3: 19200bps
* @param    en:1
* @retval   null
*/
#define drv_ufcs0_bdrate_tx(x) \
        do{\
             REG_UFCS_BDRATE->bf.bdrate_tx = x;\
        }while(0)

#define drv_ufcs0_bdrate_rx()\
        (REG_UFCS_BDRATE->bf.rx)


#define drv_ufcs0_txpkt_len(x) \
        do{\
             REG_UFCS_TXPKT->bf.len = x;\
        }while(0)


#define drv_ufcs0_pwd0_extint_enable(x) \
        do{\
            REG_EXTINT_PWD0_INT->bf.en = x; \
        }while(0)

#define drv_ufcs0_pwd1_extint_enable(x) \
        do{\
            REG_EXTINT_PWD1_INT->bf.en = x; \
        }while(0)

#define drv_ufcs0_pwd0_extint_clr() \
        do{\
            REG_EXTINT_PWD0_INT->bf.clr = 1; \
        }while(0)

#define drv_ufcs0_pwd1_extint_clr() \
        do{\
            REG_EXTINT_PWD1_INT->bf.clr = 1; \
        }while(0)

#define drv_ufcs0_get_pwd0_val() \
				(REG_PWD_CH0_VAL->word)

#define drv_ufcs0_get_pwd1_val() \
				(REG_PWD_CH1_VAL->word)

#define drv_ufcs0_get_rx_int()\
        (REG_UFCS_INT_RX->word)

#define drv_ufcs0_get_tx_int()\
        (REG_UFCS_INT_TX->word)

#define drv_ufcs0_rx_int_mask(x)\
        do{\
             REG_UFCS_INT_RX_MASK->word = x;\
            }while(0)

#define drv_ufcs0_tx_int_mask(x)\
        do{\
             REG_UFCS_INT_TX_MASK->word = x;\
            }while(0)


#define drv_ufcs0_rx_int_clr(x)\
        do{\
            REG_UFCS_INT_RX->word = x;\
        }while(0)

#define drv_ufcs0_tx_int_clr(x)\
        do{\
            REG_UFCS_INT_TX->word = x;\
        }while(0)

#define drv_ufcs0_rx_hard_reset_val_set(x)\
        do{\
            REG_UFCS_HWRST->bf.rx_wid = x;\
        }while(0)


/*********************************UFCS1*********************************/
/*
* @brief  1=start send packet at the time of this bit toggle from "0" to "1", if the tx fifo is not empty, and this bit is set as high.
* @param    en:1
* @retval   null
*/
#define drv_ufcs1_ctrl_tx_enable(x) \
        do{\
            REG_UFCS1_CTRL->bf.tx_enable = x;\
        }while(0)


/*
* @brief  //1=start receive the rx packet data, effective only when the rx fifo is no full
	//packet aligned: hardware clear after packet rx done, software set for new packet
* @param    en:1
* @retval   null
*/
#define drv_ufcs1_ctrl_rx_enable(x) \
        do{\
            REG_UFCS1_CTRL->bf.rx_enable = x;\
        }while(0)

/*
* @brief 1: hw clear rx_enable at the time of rxpkt_end, software set rx_enable; 0: sw control rx_enable directly
* @param    en:1
* @retval   null
*/
#define drv_ufcs1_ctrl_rx_stop_en(x) \
        do{\
            REG_UFCS1_CTRL->bf.rxstop_en = x;\
        }while(0)

/*
* @brief 1:  send cable hardware reset command, only valid when the "txpkt_end" is high level, set by software, clear by hw;
* @param    en:1
* @retval   null
*/
#define drv_ufcs1_ctrl_hw_reset_cable(x) \
        do{\
            REG_UFCS1_CTRL->bf.hwrst_cble = x;\
        }while(0)

/*
* @brief //send sink hardware reset command, only valid when the "txpkt_end" is high level, if tx packet not end status, miss this command
* @param    en:1
* @retval   null
*/

#define drv_ufcs1_ctrl_hw_reset_tx(x) \
        do{\
            REG_UFCS1_CTRL->bf.hwrst_tx = x;\
        }while(0)


/*
* @brief
   //source stop tx, set tx(d-) as tri-state, if this bit is high, d- pin output is disabled
//all the following condition is met, then the stop command is not effect
//1 tx packet is processing
//2. hwrst is processing
* @param    en:1
* @retval   null
*/
#define drv_ufcs1_ctrl_stop_src_tx(x) \
        do{\
            REG_UFCS1_CTRL->bf.stop_tx = x;\
        }while(0)


/*
* @brief /1=reset just the ufcs phy logic for both the ufcs phy transmitter and receiver.
* @param    en:1
* @retval   null
*/
#define drv_ufcs1_reset_logic() \
        do{\
            REG_UFCS1_RESET->bf.reset_logic = 1;\
        }while(0)


/*
* @brief /1=reset just the ufcs phy logic for both the ufcs phy transmitter and receiver.
* @param    en:1
* @retval   null
*/
#define drv_ufcs1_reset_all() \
        do{\
            REG_UFCS1_RESET->bf.reset_all = 1;\
        }while(0)

/*
* @brief //clear rx fifo, after write 1, will be cleared
* @param    en:1
* @retval   null
*/
#define drv_ufcs1_reset_clr_rx_fifo() \
        do{\
            REG_UFCS1_RESET->bf.rxfifo_clr = 1;\
        }while(0)

/*
* @brief //tx baudrate configure
//0: 115200; 1:57600; 2:38400; 3: 19200bps
* @param    en:1
* @retval   null
*/
#define drv_ufcs1_bdrate_tx(x) \
        do{\
             REG_UFCS1_BDRATE->bf.bdrate_tx = x;\
        }while(0)

#define drv_ufcs1_bdrate_rx()\
        (REG_UFCS1_BDRATE->bf.rx)


#define drv_ufcs1_txpkt_len(x) \
        do{\
             REG_UFCS1_TXPKT->bf.len = x;\
        }while(0)


#define drv_ufcs1_pwd2_extint_enable(x) \
        do{\
            REG_EXTINT_PWD2_INT->bf.en = x; \
        }while(0)

#define drv_ufcs1_pwd3_extint_enable(x) \
        do{\
            REG_EXTINT_PWD3_INT->bf.en = x; \
        }while(0)

#define drv_ufcs1_pwd2_extint_clr() \
        do{\
            REG_EXTINT_PWD2_INT->bf.clr = 1; \
        }while(0)

#define drv_ufcs1_pwd3_extint_clr() \
        do{\
            REG_EXTINT_PWD3_INT->bf.clr = 1; \
        }while(0)

#define drv_ufcs1_get_pwd2_val() \
				(REG_PWD_CH2_VAL->word)

#define drv_ufcs1_get_pwd3_val() \
				(REG_PWD_CH3_VAL->word)

#define drv_ufcs1_get_rx_int()\
        (REG_UFCS1_INT_RX->word)

#define drv_ufcs1_get_tx_int()\
        (REG_UFCS1_INT_TX->word)

#define drv_ufcs1_rx_int_mask(x)\
        do{\
             REG_UFCS1_INT_RX_MASK->word = x;\
            }while(0)


#define drv_ufcs1_tx_int_mask(x)\
        do{\
             REG_UFCS1_INT_TX_MASK->word = x;\
            }while(0)

#define drv_ufcs1_rx_int_clr(x)\
        do{\
            REG_UFCS1_INT_RX->word = x;\
        }while(0)

#define drv_ufcs1_tx_int_clr(x)\
        do{\
            REG_UFCS1_INT_TX->word = x;\
        }while(0)

#define drv_ufcs1_rx_hard_reset_val_set(x)\
        do{\
            REG_UFCS1_HWRST->bf.rx_wid = x;\
        }while(0)

#endif