/**
 ******************************************************************************
 * @copyright Copyright (C), 2016-2022, ConvenientPower. Co., Ltd.
 * @file    ufcs_flag.h
 * @version 1.0
 * @author  qing.cheng
 * @date    2022-12-02
 * @brief   Header file of UFCS_FLAG_H module.
 ******************************************************************************
 */
#ifndef _UFCS_FLAG_H_
#define _UFCS_FLAG_H_

#include "core_comm.h"
#include "drv_comm.h"

//#define ENABLE_UFCS_IRQ() \
//        do{\
//            NVIC_EnableIRQ(UFCS_TX_IRQn);\
//            NVIC_EnableIRQ(UFCS_RX_IRQn);\
//        }while(0)

//#define DISABLE_UFCS_IRQ() \
//        do{\
//            NVIC_DisableIRQ(UFCS_TX_IRQn);\
//            NVIC_DisableIRQ(UFCS_RX_IRQn);\
//        }while(0)

#define ENABLE_UFCS_IRQ()  //__enable_irq()
#define DISABLE_UFCS_IRQ() //__disable_irq()

#define __UFCS_SET_FLAG(val, mask) \
    do \
    { \
        (val) |= (mask); \
    } while (0)

#define __UFCS_CLR_FLAG(val, mask) \
    do \
    { \
        (val) &= ~(mask); \
    } while (0)

#define UFCS_FLAG(val, mask) (!!((val) & (mask)))

#define UFCS_SET_FLAG(val, mask) \
    do \
    { \
        DISABLE_UFCS_IRQ(); \
        __UFCS_SET_FLAG(val, mask); \
        ENABLE_UFCS_IRQ(); \
    } while (0)

#define UFCS_CLR_FLAG(val, mask) \
    do \
    { \
        DISABLE_UFCS_IRQ(); \
        __UFCS_CLR_FLAG(val, mask);\
        ENABLE_UFCS_IRQ(); \
    } while(0)

#define PRL_HARDRESET_RECIVED_FROM_PHY               BIT_SET(0)
#define PRL_PACKET_RECIVED_FROM_PHY                  BIT_SET(1)
#define PRL_PACKET_SENT_SUCC_FROM_PHY                BIT_SET(2)
#define PRL_CABLE_HARDRESET_SUCESS_FROM_PHY          BIT_SET(3)
#define PRL_SNK_HARDRESET_SUCESS_FROM_PHY            BIT_SET(4)
#define PRL_RECIVED_MSG_ERROR_FROM_PHY               BIT_SET(5)
#define PRL_RECIVED_ERROR_FRAME_FROM_PHY             BIT_SET(6)
#define PRL_RECIVED_CRC_IS_OK_FROM_PHY               BIT_SET(7)
//#define PRL_RELAY_ANCK_START_FROM_PRL                BIT_SET(8)

#endif /* PD_FLAG_H */