/**
 ******************************************************************************
 * @copyright Copyright (C), 2016-2022, ConvenientPower. Co., Ltd.
 * @file    ufcs_prl_define.h
 * @version 1.0
 * @author  qing.cheng
 * @date    2022-12-02
 * @brief   Header file of UFCS_PRL_DEFINE_H module.
 ******************************************************************************
 */
#ifndef _UFCS_PRL_DEFINE_H_
#define _UFCS_PRL_DEFINE_H_

#include "core_comm.h"
#include "drv_comm.h"
#include "ufcs_flag.h"

#define UFCS_CTRL_PKT			0
#define UFCS_DATA_PKT			1
#define UFCS_EXT_PKT		    2


#define T_DET_VALID_MIN         1000
#define T_DET_VALID_MAX         12000

#define T_DET1_MIN              1400
#define T_DET1_MAX              2600

#define T_DET2_MIN              5600
#define T_DET2_MAX              10800

#define HDSK_DEC_TIMES          6

#define UFCS_TRAINING     0xAA
#define ufcs_clr_timeout_flag(_port, _timer)\
    do\
    {\
        (_port)->ufcs_flags.ufcs_timer_flag.word &= ~((1u << (_timer)) & 0xfff);\
    }while(0)
typedef enum
{
    UFCS_PRL_Rx_Wait_for_PHY_Message = 0,
//    UFCS_PRL_Rx_Check_CRC,
    UFCS_PRL_Rx_Check_MsgNumber,
    UFCS_PRL_Rx_Max

} ufcs_prl_rx_status_e;


typedef enum
{
    UFCS_PRL_Tx_Reset = 0,
    UFCS_PRL_Tx_Wait_for_Msg_Request,
    UFCS_PRL_Tx_Send_Msg,
    UFCS_PRL_Tx_Wait_Response,
//    UFCS_PRL_Tx_Match_MsgNumber,
    UFCS_PRL_Tx_Check_RetryCounter,
    UFCS_PRL_Tx_Max
} ufcs_prl_tx_status_e;

typedef enum
{
    UFCS_PRL_HDSK_Pulse = 0,
    UFCS_PRL_HDSK_Wait_Ping,
    UFCS_PRL_HDSK_RDY,
    UFCS_PRL_HDSK_Max,
} ufcs_prl_hdsk_status_e;



typedef enum
{

    UFCS_PRL_HR_RESET_LAYER = 0,
    UFCS_PRL_HR_WAIT_HARD_RESET_COMPLETE,
    UFCS_PRL_HR_WAIT_HARD_RESET_Max
} ufcs_prl_hr_status_e;

typedef enum UFCS_PROCESS_STATUS_e
{
    UFCS_ENTER = 0,
    UFCS_EXIT,
} UFCS_PROCESS_STATUS_e;

typedef enum
{
    ufcs_prl_rx_entry_status,
    ufcs_prl_rx_exit_status,
} ufcs_prl_rx_process_status_e;


typedef enum
{
    ufcs_prl_tx_entry_status,
    ufcs_prl_tx_exit_status,
} ufcs_prl_tx_process_status_e;



typedef enum
{
    ufcs_prl_hr_entry_status,
    ufcs_prl_hr_exit_status,
} ufcs_prl_hr_process_status_e;


typedef enum
{
    ufcs_prl_hdsk_entry_status,
    ufcs_prl_hdsk_exit_status,
} ufcs_prl_hdsk_process_status_e;


typedef union
{
    uint16_t data16;
    uint8_t byte[2];
    struct
    {

        uint8_t prl_packet_recived_from_pe: 1;
        uint8_t prl_snk_hardreset_recived_from_pe: 1;
        uint8_t prl_cable_hardreset_recived_from_pe: 1;
        uint8_t prl_recived_start_cable_from_pe: 1;
        uint8_t prl_recived_bdrate_not_support: 1;
        uint8_t prl_open_watchdog_recived_from_prl: 1;
        uint8_t prl_recived_start_cable_: 1;
        uint8_t prl_recived_stop_tx_pe: 1;

        uint8_t prl_packet_wait_ack_from_phy: 1;
        uint8_t reserved: 7;
    };
} ufcs_prl_flags_u;

typedef union ufcs_prl_int_flags_u
{
    uint16_t data16;
    uint8_t byte[2];
    struct
    {
        uint8_t prl_hardreset_recived_from_phy: 1;
        uint8_t prl_packet_recived_from_phy: 1;
        uint8_t prl_packet_sent_succ_from_phy: 1;
        uint8_t prl_cable_hardreset_succ_from_phy: 1;
        uint8_t prl_snk_hardreset_succ_from_phy: 1;
        uint8_t prl_recived_msg_error_from_phy: 1;
        uint8_t prl_recived_error_frame_from_phy: 1;
        uint8_t prl_recived_crc_is_ok_from_phy: 1;

        //BYTE1
        uint8_t prl_relay_anck_start_from_prl: 1;
        uint8_t reserved: 7;

    };
} ufcs_prl_int_flags_u;


//4 *8 32byte sram calc zxs
typedef struct
{

//    ufcs_prl_hr_status_e prl_hr_status;
//    ufcs_prl_hr_process_status_e prl_hr_process_status;

    ufcs_prl_tx_status_e prl_tx_status;                   // tx status
    ufcs_prl_tx_process_status_e prl_tx_process_status;   // tx process status

    ufcs_prl_rx_status_e prl_rx_status;									  // rx status
    ufcs_prl_rx_process_status_e prl_rx_process_status;   // rx process status

    ufcs_prl_hdsk_status_e ufcs_prl_hdsk_status;
    ufcs_prl_hdsk_process_status_e prl_hdsk_process_status;

} ufcs_prl_status_s;


#endif