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1029 lines
56 KiB
1029 lines
56 KiB
#ifndef __CLKCTRL_DEFINE_H__
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#define __CLKCTRL_DEFINE_H__
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//-----------------------------------------------------------------------------
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// clkctrl registers definition
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//-----------------------------------------------------------------------------
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#pragma anon_unions
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//-----------------------------------------------------------------------------
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// registers structures
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typedef struct
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{
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//1'b0:mclk=24mhz,
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//1'b1:mclk=6mhz
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uint32_t mclk_sel:1;
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//1. green mode enable
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//0. green mode disable
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//*set by sw, clear by sw or hw, check details in digital top design spec or cdr doc
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uint32_t green_mode:1;
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//1. sleep mode enable
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//0. sleep mode disable
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//*set by sw valid only when sleep_req is high, clear by sw or hw(exit sleep mode by analog request not active), check details in digital top design spec or cdr doc
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uint32_t sleep_mode:1;
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//0: unmask vin ov/ vin ratio ov exit sleep/green
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//1: mask vin ov/ vin ratio ov exit sleep/green
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uint32_t mask_vin_ov:1;
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//0: unmask vin uv exit sleep/green
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//1: mask vin uv exit sleep/green
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uint32_t mask_vin_uv:1;
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//0: unmask vin1 ov/ vin ratio ov exit sleep/green
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//1: mask vin1 ov/ vin ratio ov exit sleep/green
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uint32_t mask_vin1_ov:1;
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//0: unmask vin1 uv exit sleep/green
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//1: mask vin1 uv exit sleep/green
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uint32_t mask_vin1_uv:1;
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//0: unmask vin2 ov/ vin ratio ov exit sleep/green
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//1: mask vin2 ov/ vin ratio ov exit sleep/green
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uint32_t mask_vin2_ov:1;
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//0: unmask vin2 uv exit sleep/green
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//1: mask vin2 uv exit sleep/green
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uint32_t mask_vin2_uv:1;
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//0: unmask vubs1 ocp comparator high level exit sleep_green
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//1: mask vubs1 ocpcomparator high level exit sleep_green
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uint32_t mask_vbus1_ocp:1;
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//0: unmask vubs2 ocp comparator high level exit sleep_green
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//1: mask vubs2 ocpcomparator high level exit sleep_green
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uint32_t mask_vbus2_ocp:1;
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//0: unmask gate1 uvp comparator high level exit sleep_green
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//1: mask gate1 uvpcomparator high level exit sleep_green
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uint32_t mask_gate1_uv:1;
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//0: unmask gate2 uvp comparator high level exit sleep_green
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//1: mask gate2 uvpcomparator high level exit sleep_green
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uint32_t mask_gate2_uv:1;
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//0: unmask gate3 uvp comparator high level exit sleep_green
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//1: mask gate3 uvpcomparator high level exit sleep_green
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uint32_t mask_gate3_uv:1;
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//0: unmask v2 ocp comparator high level exit sleep_green
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//1: mask v2 ocp comparator high level exit sleep_green
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uint32_t mask_v2_ocp:1;
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//i2c 0 i/o comparator change mask
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//0:unmask i2c io change wake on sleep/green exit(detect falling edge)
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//1:mask i2c io change wake on sleep/green exit(detect falling edge)
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uint32_t mask_i2c1:1;
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//i2c 1 i/o comparator change mask
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//0:unmask i2c io change wake on sleep/green exit(detect falling edge)
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//1:mask i2c io change wake on sleep/green exit(detect falling edge)
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uint32_t mask_i2c2:1;
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//0: unmask current sense1 on sleep/green entry(<80mv/120mv)/exit(>80mv/120mv)
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//1: mask current sense1 on sleep/green entry(<80mv/120mv)/exit(>80mv/120mv)
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uint32_t mask_cs1:1;
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//0: unmask current sense2 on sleep/green entry(<80mv/120mv)/exit(>80mv/120mv)
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//1: mask current sense2 on sleep/green entry(<80mv/120mv)/exit(>80mv/120mv)
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uint32_t mask_cs2:1;
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//0: unmask cc_comp_wake on sleep/green entry(>2.6v)
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//1: mask cc_comp_wake on sleep/green entry(>2.6v)
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uint32_t mask_pd1_cc_comp_entry:1;
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//0: unmask cc_comp_wake on sleep/green exit(<=2.6v)
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//1: mask cc_comp_wake on sleep/green exit(<=2.6v)
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uint32_t mask_pd1_cc_comp_exit:1;
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//0: unmask bmc comparator change on green /greenexit
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//1: mask bmc comparator change on green /greenexit
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uint32_t mask_pd1_bmc:1;
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//0: unmask dp/dn on sleep/green entry(<0.45v)/exit(>=0.45v)
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//1: mask dp/dn on sleep/green entry(<0.45v)/exit(>=0.45v)
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uint32_t mask_dpdn1_0p4v:1;
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//0: unmask dp/dn on green/green exit(<=2v)
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//1: mask dp/dn on green/green exit(<=2v)
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uint32_t mask_dpdn1_2p0v:1;
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//0: unmask dp/dn on sleep/green entry(<1.2v)/exit(>=1.2v)
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//1: mask dp/dn on sleep/green entry(<1.2v)/exit(>=1.2v)
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uint32_t mask_dpdn1_1p2v:1;
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//0: unmask dp/dm comparator high level exit sleep/green
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//1: mask dp/dm comparator high level exit sleep/green
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uint32_t mask_dpdn1_ov:1;
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//0: unmask cc1/cc2 comparator high level exit sleep/green
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//1: mask cc1/cc2 comparator high level exit sleep/green
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uint32_t mask_pd1_ccx_ov:1;
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//0: unmask pd vcon oc comparator high level exit sleep_green
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//1: mask pd vcon occomparator high level exit sleep_green
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uint32_t mask_pd1_vcon_oc:1;
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//0: unmask 1.6/2.6 comparator or 0.2/0.4/0.8 comparator change on green/sleep exit
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//1: mask 1.6/2.6 comparator or 0.2/0.4/0.8 comparator change on green/sleep exit
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uint32_t mask_pd1_ccx_status:1;
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//1: disable trim key1 (address offset 0x1e wod, 32'h5724_e185) check
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//0: enable trim key1 (address offset 0x1e word) check
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uint32_t trim_mcu_start_dis:1;
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//1: disable trim key2 (address offset 0x1f word, 32'h7455_874e ) check
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//0: enable trim key3 (address offset 0x1f word) check
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uint32_t trim_trim_start_dis:1;
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//triming load function control
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//0: triming load function is enabled
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//1: triming load function is disabled
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uint32_t trim_dis:1;
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} REG_clkctrl_sys_ctrl_bitfiled_TypeDef;
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typedef struct
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{
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union {
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__IO REG_clkctrl_sys_ctrl_bitfiled_TypeDef bf;//bitfiled
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__IO uint32_t word;
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};
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} REG_clkctrl_sys_ctrl_TypeDef;
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typedef struct
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{
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//use pclk, same as mclk, based on clk_sel
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uint32_t timer0_en:1;
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//use pclk, same as mclk, based on clk_sel
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uint32_t timer1_en:1;
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//use pclk, same as mclk, based on clk_sel
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uint32_t timer2_en:1;
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//use pclk, same as mclk, based on clk_sel
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uint32_t uart1_en:1;
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//use pclk, same as mclk, based on clk_sel
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uint32_t uart2_en:1;
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//use 2mhz clock
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uint32_t adc_en:1;
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//use 1mhz clock
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uint32_t dac_ctrl_en:1;
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//i2c func 0 use pclk, same as mclk, based on clk_sel, must be enabled for this device regsiter read/write access
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uint32_t i2c_master0_en:1;
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//i2c func 1 use pclk
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uint32_t i2c_master1_en:1;
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//use 12mhz clock
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uint32_t vd_en:1;
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//use 1mhz clock
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uint32_t pwd0_en:1;
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//use 1mhz clock
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uint32_t pwd1_en:1;
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//use 1mhz clock
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uint32_t pwd2_en:1;
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//use 1mhz clock
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uint32_t pwd3_en:1;
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//use 12mhz clock
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uint32_t pd0_h_en:1;
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//use 12mhz clock
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uint32_t pd1_h_en:1;
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//use 343hz clock
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uint32_t pd0_l_en:1;
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//use 343hz clock
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uint32_t pd1_l_en:1;
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//use 12mhz clock
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uint32_t ufcs0_en:1;
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//use 12mhz clock
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uint32_t ufcs1_en:1;
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//use 12mhz clock
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uint32_t scp0_en:1;
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//use 12mhz clock
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uint32_t scp1_en:1;
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//watchdog enable, use pclk, same as mclk, based on clk_sel
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uint32_t wdog_en:1;
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//vin dischargre enable, use 1mhz
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uint32_t vin_dis_en:1;
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uint32_t reserved_31_24:8;
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} REG_clkctrl_peri_cg_bitfiled_TypeDef;
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typedef struct
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{
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union {
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__IO REG_clkctrl_peri_cg_bitfiled_TypeDef bf;//bitfiled
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__IO uint32_t word;
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};
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} REG_clkctrl_peri_cg_TypeDef;
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typedef struct
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{
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//write 1 to reset m0
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uint32_t mcu:1;
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uint32_t reserved_7_1:7;
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//write 1 to reset apb bus
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uint32_t apb:1;
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uint32_t reserved_15_9:7;
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//write 1 to reset m0 and hold, 0 mcu run
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uint32_t mcu_hold:1;
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uint32_t reserved_23_17:7;
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//reset both mcu and bus
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uint32_t system:1;
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uint32_t reserved_31_25:7;
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} REG_clkctrl_sys_rstreq_bitfiled_TypeDef;
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typedef struct
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{
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union {
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__IO REG_clkctrl_sys_rstreq_bitfiled_TypeDef bf;//bitfiled
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__IO uint32_t word;
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};
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} REG_clkctrl_sys_rstreq_TypeDef;
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typedef struct
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{
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//gp0 alter func, refer to pin mux doc
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uint32_t gp0:2;
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//gp1 alter func, refer to pin mux doc
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uint32_t gp1:2;
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//gp2 alter func, refer to pin mux doc
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uint32_t gp2:2;
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//gp3 alter func, refer to pin mux doc
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uint32_t gp3:2;
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//gp4 alter func, refer to pin mux doc
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uint32_t gp4:2;
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//gp5 alter func, refer to pin mux doc
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uint32_t gp5:2;
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//cc1_1 alter func, refer to pin mux doc
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uint32_t cc1_1:2;
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//cc2_1 alter func, refer to pin mux doc
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uint32_t cc2_1:2;
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//cc1_2 alter func, refer to pin mux doc
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uint32_t cc1_2:2;
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//cc2_2 alter func, refer to pin mux doc
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uint32_t cc2_2:2;
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//fb1 alter func, refer to pin mux doc
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uint32_t fb1:2;
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//comp1 alter func, refer to pin mux doc
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uint32_t comp1:2;
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//fb2 alter func, refer to pin mux doc
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uint32_t fb2:2;
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//comp2 alter func, refer to pin mux doc
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uint32_t comp2:2;
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//vfb alter func, refer to pin mux doc
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uint32_t vfb:2;
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//ifb alter func, refer to pin mux doc
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uint32_t ifb:2;
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} REG_clkctrl_pin_mul_set_bitfiled_TypeDef;
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typedef struct
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{
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union {
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__IO REG_clkctrl_pin_mul_set_bitfiled_TypeDef bf;//bitfiled
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__IO uint32_t word;
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};
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} REG_clkctrl_pin_mul_set_TypeDef;
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typedef struct
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{
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//margin adjust
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uint32_t sram_2p5k_s:4;
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//sleep mode (active high)
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uint32_t sram_2p5k_sl:1;
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//shutdown mode (active high)
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uint32_t sram_2p5k_sd:1;
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//source bias level adjust in sl mode(default is vcsb = low)
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uint32_t sram_2p5k_vcsb:1;
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uint32_t reserved_31_7:25;
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} REG_clkctrl_mem_bitfiled_TypeDef;
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typedef struct
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{
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union {
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__IO REG_clkctrl_mem_bitfiled_TypeDef bf;//bitfiled
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__IO uint32_t word;
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};
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} REG_clkctrl_mem_TypeDef;
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typedef struct
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{
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//dtb1 output selection
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uint32_t sel1:7;
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//dtb2 output selection
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uint32_t sel2:7;
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uint32_t reserved_15_14:2;
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//dtb1 enable，1：dtb,0:atb
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uint32_t enable1:1;
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//dtb2 enable，1：dtb,0:atb
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uint32_t enable2:1;
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uint32_t reserved_23_18:6;
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//analog to digital signal selection on dtb1
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uint32_t a2d_sel1:3;
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//analog to digital signal selection on dtb2
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uint32_t a2d_sel2:3;
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uint32_t reserved_31_30:2;
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} REG_clkctrl_dtest_bitfiled_TypeDef;
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typedef struct
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{
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union {
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__IO REG_clkctrl_dtest_bitfiled_TypeDef bf;//bitfiled
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__IO uint32_t word;
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};
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} REG_clkctrl_dtest_TypeDef;
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typedef struct
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{
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//use 12mhz clock,"sw clock gating control
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//1: clock is enable 0: clock is disabled
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uint32_t en:1;
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//dft_mbist_start
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uint32_t start:1;
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uint32_t reserved_29_2:28;
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//dft_mbist_done
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uint32_t done:1;
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//dft_mbist_failed
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uint32_t failed:1;
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} REG_clkctrl_mbist_bitfiled_TypeDef;
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typedef struct
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{
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union {
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__IO REG_clkctrl_mbist_bitfiled_TypeDef bf;//bitfiled
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__IO uint32_t word;
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};
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} REG_clkctrl_mbist_TypeDef;
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typedef struct
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{
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//write 16‘h9a6e to 0x4001_401c to enable this module password hit register
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uint32_t pw_hit:1;
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uint32_t reserved_31_1:31;
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} REG_clkctrl_clkctrl_bitfiled_TypeDef;
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typedef struct
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{
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union {
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__IO REG_clkctrl_clkctrl_bitfiled_TypeDef bf;//bitfiled
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__IO uint32_t word;
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};
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} REG_clkctrl_clkctrl_TypeDef;
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typedef struct
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{
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//a2d_dpdn_dn_comp_0p4v filter time select, 0:100us 1:200us
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uint32_t dn_0p4v:1;
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//a2d_dpdn_dn_comp_2p0v filter time select, 0:100us 1:200us
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uint32_t dn_2p0v:1;
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//a2d_dpdn_dp_comp_0p4v filter time select, 0:100us 1:200us
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uint32_t dp_0p4v:1;
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//a2d_dpdn_dp_comp_2p0v filter time select, 0:100us 1:200us
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uint32_t dp_2p0v:1;
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//a2d_dpdn_ov filter time select, configure: 0: 50us 1:100us 2:500us 3:1000us
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uint32_t dpdn_ov:2;
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//00: disable; step is 12mhz clock cycle, 83.3ns/step
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uint32_t dn_in:4;
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//00: disable; step is 12mhz clock cycle, 83.3ns/step
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uint32_t dp_in:4;
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uint32_t reserved_15_14:2;
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//00: disable; step is 12mhz clock cycle, 83.3ns/step
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uint32_t pd_rxd:4;
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//a2d_pd_ccx_ovp;configure: 0: 50us 1:100us 2:500us 3:1000us
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uint32_t pd_ccx_ovp:2;
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//a2d_short_vdc_comp_vbusoc ;configure: 0: 10us 1: 20us
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uint32_t vdc_comp_vbusoc:1;
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uint32_t reserved_31_23:9;
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} REG_clkctrl_filter_bitfiled_TypeDef;
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typedef struct
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{
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union {
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__IO REG_clkctrl_filter_bitfiled_TypeDef bf;//bitfiled
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__IO uint32_t word;
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};
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} REG_clkctrl_filter_TypeDef;
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typedef struct
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{
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//ufcs/vfcp train baud rate valid range config based on 115200 bps.
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//standard 115200 is 104cycle in 12mhz, config this reg to set the valid range x=104 +/- vlld_skew.
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//57600 range = x*2, 38400 range=x*3, 19200 range=x*6.
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uint32_t vld_skew:5;
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uint32_t reserved_31_5:27;
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} REG_clkctrl_baudrate_bitfiled_TypeDef;
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typedef struct
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{
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union {
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__IO REG_clkctrl_baudrate_bitfiled_TypeDef bf;//bitfiled
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__IO uint32_t word;
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};
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} REG_clkctrl_baudrate_TypeDef;
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typedef struct
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{
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//opto alter func, refer to pin mux doc
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uint32_t opto:2;
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//vd alter func, refer to pin mux doc
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uint32_t vd:2;
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uint32_t reserved_31_4:28;
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} REG_clkctrl_pin_mul_set1_bitfiled_TypeDef;
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typedef struct
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{
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union {
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__IO REG_clkctrl_pin_mul_set1_bitfiled_TypeDef bf;//bitfiled
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__IO uint32_t word;
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};
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} REG_clkctrl_pin_mul_set1_TypeDef;
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typedef struct
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{
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//0: unmask cc_comp_wake on sleep/green entry(>2.6v)
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//1: mask cc_comp_wake on sleep/green entry(>2.6v)
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uint32_t mask_pd2_cc_comp_entry:1;
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//0: unmask cc_comp_wake on sleep/green exit(<=2.6v)
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//1: mask cc_comp_wake on sleep/green exit(<=2.6v)
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uint32_t mask_pd2_cc_comp_exit:1;
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//0: unmask bmc comparator change on green /greenexit
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//1: mask bmc comparator change on green /greenexit
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uint32_t mask_pd2_bmc:1;
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//0: unmask cc1/cc2 comparator high level exit sleep/green
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//1: mask cc1/cc2 comparator high level exit sleep/green
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uint32_t mask_pd2_ccx_ov:1;
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//0: unmask pd vcon oc comparator high level exit sleep_green
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//1: mask pd vcon occomparator high level exit sleep_green
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uint32_t mask_pd2_vcon_oc:1;
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//0: unmask 1.6/2.6 comparator or 0.2/0.4/0.8 comparator change on green/sleep exit
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//1: mask 1.6/2.6 comparator or 0.2/0.4/0.8 comparator change on green/sleep exit
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uint32_t mask_pd2_ccx_status:1;
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//0: unmask dp/dn on sleep/green entry(<0.45v)/exit(>=0.45v)
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//1: mask dp/dn on sleep/green entry(<0.45v)/exit(>=0.45v)
|
|
uint32_t mask_dpdn2_0p4v:1;
|
|
//0: unmask dp/dn on green/green exit(<=2v)
|
|
//1: mask dp/dn on green/green exit(<=2v)
|
|
uint32_t mask_dpdn2_2p0v:1;
|
|
//0: unmask dp/dn on sleep/green entry(<1.2v)/exit(>=1.2v)
|
|
//1: mask dp/dn on sleep/green entry(<1.2v)/exit(>=1.2v)
|
|
uint32_t mask_dpdn2_1p2v:1;
|
|
//0: unmask dp/dm comparator high level exit sleep/green
|
|
//1: mask dp/dm comparator high level exit sleep/green
|
|
uint32_t mask_dpdn2_ov:1;
|
|
//0: unmask vin1_uvlo high level exit sleep/green
|
|
//1: mask vin1_uvlo level exit sleep/green
|
|
uint32_t mask_vin1_uvlo:1;
|
|
//0: unmask vin2_uvlo high level exit sleep/green
|
|
//1: mask vin2_uvlo level exit sleep/green
|
|
uint32_t mask_vin2_uvlo:1;
|
|
uint32_t reserved_31_12:20;
|
|
} REG_clkctrl_sys_ctrl1_bitfiled_TypeDef;
|
|
|
|
typedef struct
|
|
{
|
|
union {
|
|
__IO REG_clkctrl_sys_ctrl1_bitfiled_TypeDef bf;//bitfiled
|
|
__IO uint32_t word;
|
|
};
|
|
} REG_clkctrl_sys_ctrl1_TypeDef;
|
|
|
|
typedef struct
|
|
{
|
|
//swd pin sel:
|
|
//0: use rt1/rt2 as swclk/swdio
|
|
//1: use vfb/ifb as swclk/swdio.
|
|
uint32_t swd:1;
|
|
//uart2_tx pin sel:
|
|
//0: use rt2 as uart2_tx
|
|
//1: use cc2_1 as uart2_tx.
|
|
uint32_t uart2:1;
|
|
uint32_t reserved_31_2:30;
|
|
} REG_clkctrl_sel_bitfiled_TypeDef;
|
|
|
|
typedef struct
|
|
{
|
|
union {
|
|
__IO REG_clkctrl_sel_bitfiled_TypeDef bf;//bitfiled
|
|
__IO uint32_t word;
|
|
};
|
|
} REG_clkctrl_sel_TypeDef;
|
|
|
|
typedef struct
|
|
{
|
|
//sleep request status
|
|
uint32_t sleep_req:1;
|
|
uint32_t reserved_31_1:31;
|
|
} REG_clkctrl_sys_stat_bitfiled_TypeDef;
|
|
|
|
typedef struct
|
|
{
|
|
union {
|
|
__IO REG_clkctrl_sys_stat_bitfiled_TypeDef bf;//bitfiled
|
|
__IO uint32_t word;
|
|
};
|
|
} REG_clkctrl_sys_stat_TypeDef;
|
|
|
|
typedef struct
|
|
{
|
|
//write 0x5724e185 to 'h00002078 will release mcu‘s reset at power up
|
|
uint32_t value:1;
|
|
uint32_t reserved_31_1:31;
|
|
} REG_clkctrl_mcu_start_flag_bitfiled_TypeDef;
|
|
|
|
typedef struct
|
|
{
|
|
union {
|
|
__IO REG_clkctrl_mcu_start_flag_bitfiled_TypeDef bf;//bitfiled
|
|
__IO uint32_t word;
|
|
};
|
|
} REG_clkctrl_mcu_start_flag_TypeDef;
|
|
|
|
typedef struct
|
|
{
|
|
//write 0x7455874e to 'h0000207c will load trim area to analog register at power up
|
|
uint32_t value:1;
|
|
uint32_t reserved_31_1:31;
|
|
} REG_clkctrl_trim_start_flag_bitfiled_TypeDef;
|
|
|
|
typedef struct
|
|
{
|
|
union {
|
|
__IO REG_clkctrl_trim_start_flag_bitfiled_TypeDef bf;//bitfiled
|
|
__IO uint32_t word;
|
|
};
|
|
} REG_clkctrl_trim_start_flag_TypeDef;
|
|
|
|
typedef struct
|
|
{
|
|
//mcu reset, from rstctl
|
|
uint32_t reset_flag:1;
|
|
//from ahb_trimming
|
|
uint32_t trim_done_flag:1;
|
|
uint32_t reserved_31_2:30;
|
|
} REG_clkctrl_mcu_stat_bitfiled_TypeDef;
|
|
|
|
typedef struct
|
|
{
|
|
union {
|
|
__IO REG_clkctrl_mcu_stat_bitfiled_TypeDef bf;//bitfiled
|
|
__IO uint32_t word;
|
|
};
|
|
} REG_clkctrl_mcu_stat_TypeDef;
|
|
|
|
//-----------------------------------------------------------------------------
|
|
// memory map
|
|
#define REG_CLKCTRL_SYS_CTRL_BASE 0x40014000
|
|
#define REG_CLKCTRL_PERI_CG_BASE 0x40014004
|
|
#define REG_CLKCTRL_SYS_RSTREQ_BASE 0x40014008
|
|
#define REG_CLKCTRL_PIN_MUL_SET_BASE 0x4001400C
|
|
#define REG_CLKCTRL_MEM_BASE 0x40014010
|
|
#define REG_CLKCTRL_DTEST_BASE 0x40014014
|
|
#define REG_CLKCTRL_MBIST_BASE 0x40014018
|
|
#define REG_CLKCTRL_CLKCTRL_BASE 0x4001401C
|
|
#define REG_CLKCTRL_FILTER_BASE 0x40014020
|
|
#define REG_CLKCTRL_BAUDRATE_BASE 0x40014024
|
|
#define REG_CLKCTRL_PIN_MUL_SET1_BASE 0x40014028
|
|
#define REG_CLKCTRL_SYS_CTRL1_BASE 0x4001402C
|
|
#define REG_CLKCTRL_SEL_BASE 0x40014030
|
|
#define REG_CLKCTRL_SYS_STAT_BASE 0x40014034
|
|
#define REG_CLKCTRL_MCU_START_FLAG_BASE 0x40014038
|
|
#define REG_CLKCTRL_TRIM_START_FLAG_BASE 0x4001403C
|
|
#define REG_CLKCTRL_MCU_STAT_BASE 0x40014088
|
|
//-----------------------------------------------------------------------------
|
|
// declaration
|
|
#define REG_CLKCTRL_SYS_CTRL ((REG_clkctrl_sys_ctrl_TypeDef *) REG_CLKCTRL_SYS_CTRL_BASE )
|
|
#define REG_CLKCTRL_PERI_CG ((REG_clkctrl_peri_cg_TypeDef *) REG_CLKCTRL_PERI_CG_BASE )
|
|
#define REG_CLKCTRL_SYS_RSTREQ ((REG_clkctrl_sys_rstreq_TypeDef *) REG_CLKCTRL_SYS_RSTREQ_BASE )
|
|
#define REG_CLKCTRL_PIN_MUL_SET ((REG_clkctrl_pin_mul_set_TypeDef *) REG_CLKCTRL_PIN_MUL_SET_BASE )
|
|
#define REG_CLKCTRL_MEM ((REG_clkctrl_mem_TypeDef *) REG_CLKCTRL_MEM_BASE )
|
|
#define REG_CLKCTRL_DTEST ((REG_clkctrl_dtest_TypeDef *) REG_CLKCTRL_DTEST_BASE )
|
|
#define REG_CLKCTRL_MBIST ((REG_clkctrl_mbist_TypeDef *) REG_CLKCTRL_MBIST_BASE )
|
|
#define REG_CLKCTRL_CLKCTRL ((REG_clkctrl_clkctrl_TypeDef *) REG_CLKCTRL_CLKCTRL_BASE )
|
|
#define REG_CLKCTRL_FILTER ((REG_clkctrl_filter_TypeDef *) REG_CLKCTRL_FILTER_BASE )
|
|
#define REG_CLKCTRL_BAUDRATE ((REG_clkctrl_baudrate_TypeDef *) REG_CLKCTRL_BAUDRATE_BASE )
|
|
#define REG_CLKCTRL_PIN_MUL_SET1 ((REG_clkctrl_pin_mul_set1_TypeDef *) REG_CLKCTRL_PIN_MUL_SET1_BASE )
|
|
#define REG_CLKCTRL_SYS_CTRL1 ((REG_clkctrl_sys_ctrl1_TypeDef *) REG_CLKCTRL_SYS_CTRL1_BASE )
|
|
#define REG_CLKCTRL_SEL ((REG_clkctrl_sel_TypeDef *) REG_CLKCTRL_SEL_BASE )
|
|
#define REG_CLKCTRL_SYS_STAT ((REG_clkctrl_sys_stat_TypeDef *) REG_CLKCTRL_SYS_STAT_BASE )
|
|
#define REG_CLKCTRL_MCU_START_FLAG ((REG_clkctrl_mcu_start_flag_TypeDef *) REG_CLKCTRL_MCU_START_FLAG_BASE )
|
|
#define REG_CLKCTRL_TRIM_START_FLAG ((REG_clkctrl_trim_start_flag_TypeDef *) REG_CLKCTRL_TRIM_START_FLAG_BASE )
|
|
#define REG_CLKCTRL_MCU_STAT ((REG_clkctrl_mcu_stat_TypeDef *) REG_CLKCTRL_MCU_STAT_BASE )
|
|
//-----------------------------------------------------------------------------
|
|
// set
|
|
#define REG_CLKCTRL_SYS_CTRL_MCLK_SEL_POS 0
|
|
#define REG_CLKCTRL_SYS_CTRL_MCLK_SEL_MSK (0x1ul << REG_CLKCTRL_SYS_CTRL_MCLK_SEL_POS)
|
|
#define REG_CLKCTRL_SYS_CTRL_MCLK_SEL_SET(num) (((num) << REG_CLKCTRL_SYS_CTRL_MCLK_SEL_POS ) & REG_CLKCTRL_SYS_CTRL_MCLK_SEL_MSK)
|
|
|
|
#define REG_CLKCTRL_SYS_CTRL_MASK_VIN_OV_POS 3
|
|
#define REG_CLKCTRL_SYS_CTRL_MASK_VIN_OV_MSK (0x1ul << REG_CLKCTRL_SYS_CTRL_MASK_VIN_OV_POS)
|
|
#define REG_CLKCTRL_SYS_CTRL_MASK_VIN_OV_SET(num) (((num) << REG_CLKCTRL_SYS_CTRL_MASK_VIN_OV_POS ) & REG_CLKCTRL_SYS_CTRL_MASK_VIN_OV_MSK)
|
|
|
|
#define REG_CLKCTRL_SYS_CTRL_MASK_VIN_UV_POS 4
|
|
#define REG_CLKCTRL_SYS_CTRL_MASK_VIN_UV_MSK (0x1ul << REG_CLKCTRL_SYS_CTRL_MASK_VIN_UV_POS)
|
|
#define REG_CLKCTRL_SYS_CTRL_MASK_VIN_UV_SET(num) (((num) << REG_CLKCTRL_SYS_CTRL_MASK_VIN_UV_POS ) & REG_CLKCTRL_SYS_CTRL_MASK_VIN_UV_MSK)
|
|
|
|
#define REG_CLKCTRL_SYS_CTRL_MASK_VIN1_OV_POS 5
|
|
#define REG_CLKCTRL_SYS_CTRL_MASK_VIN1_OV_MSK (0x1ul << REG_CLKCTRL_SYS_CTRL_MASK_VIN1_OV_POS)
|
|
#define REG_CLKCTRL_SYS_CTRL_MASK_VIN1_OV_SET(num) (((num) << REG_CLKCTRL_SYS_CTRL_MASK_VIN1_OV_POS ) & REG_CLKCTRL_SYS_CTRL_MASK_VIN1_OV_MSK)
|
|
|
|
#define REG_CLKCTRL_SYS_CTRL_MASK_VIN1_UV_POS 6
|
|
#define REG_CLKCTRL_SYS_CTRL_MASK_VIN1_UV_MSK (0x1ul << REG_CLKCTRL_SYS_CTRL_MASK_VIN1_UV_POS)
|
|
#define REG_CLKCTRL_SYS_CTRL_MASK_VIN1_UV_SET(num) (((num) << REG_CLKCTRL_SYS_CTRL_MASK_VIN1_UV_POS ) & REG_CLKCTRL_SYS_CTRL_MASK_VIN1_UV_MSK)
|
|
|
|
#define REG_CLKCTRL_SYS_CTRL_MASK_VIN2_OV_POS 7
|
|
#define REG_CLKCTRL_SYS_CTRL_MASK_VIN2_OV_MSK (0x1ul << REG_CLKCTRL_SYS_CTRL_MASK_VIN2_OV_POS)
|
|
#define REG_CLKCTRL_SYS_CTRL_MASK_VIN2_OV_SET(num) (((num) << REG_CLKCTRL_SYS_CTRL_MASK_VIN2_OV_POS ) & REG_CLKCTRL_SYS_CTRL_MASK_VIN2_OV_MSK)
|
|
|
|
#define REG_CLKCTRL_SYS_CTRL_MASK_VIN2_UV_POS 8
|
|
#define REG_CLKCTRL_SYS_CTRL_MASK_VIN2_UV_MSK (0x1ul << REG_CLKCTRL_SYS_CTRL_MASK_VIN2_UV_POS)
|
|
#define REG_CLKCTRL_SYS_CTRL_MASK_VIN2_UV_SET(num) (((num) << REG_CLKCTRL_SYS_CTRL_MASK_VIN2_UV_POS ) & REG_CLKCTRL_SYS_CTRL_MASK_VIN2_UV_MSK)
|
|
|
|
#define REG_CLKCTRL_SYS_CTRL_MASK_VBUS1_OCP_POS 9
|
|
#define REG_CLKCTRL_SYS_CTRL_MASK_VBUS1_OCP_MSK (0x1ul << REG_CLKCTRL_SYS_CTRL_MASK_VBUS1_OCP_POS)
|
|
#define REG_CLKCTRL_SYS_CTRL_MASK_VBUS1_OCP_SET(num) (((num) << REG_CLKCTRL_SYS_CTRL_MASK_VBUS1_OCP_POS ) & REG_CLKCTRL_SYS_CTRL_MASK_VBUS1_OCP_MSK)
|
|
|
|
#define REG_CLKCTRL_SYS_CTRL_MASK_VBUS2_OCP_POS 10
|
|
#define REG_CLKCTRL_SYS_CTRL_MASK_VBUS2_OCP_MSK (0x1ul << REG_CLKCTRL_SYS_CTRL_MASK_VBUS2_OCP_POS)
|
|
#define REG_CLKCTRL_SYS_CTRL_MASK_VBUS2_OCP_SET(num) (((num) << REG_CLKCTRL_SYS_CTRL_MASK_VBUS2_OCP_POS ) & REG_CLKCTRL_SYS_CTRL_MASK_VBUS2_OCP_MSK)
|
|
|
|
#define REG_CLKCTRL_SYS_CTRL_MASK_GATE1_UV_POS 11
|
|
#define REG_CLKCTRL_SYS_CTRL_MASK_GATE1_UV_MSK (0x1ul << REG_CLKCTRL_SYS_CTRL_MASK_GATE1_UV_POS)
|
|
#define REG_CLKCTRL_SYS_CTRL_MASK_GATE1_UV_SET(num) (((num) << REG_CLKCTRL_SYS_CTRL_MASK_GATE1_UV_POS ) & REG_CLKCTRL_SYS_CTRL_MASK_GATE1_UV_MSK)
|
|
|
|
#define REG_CLKCTRL_SYS_CTRL_MASK_GATE2_UV_POS 12
|
|
#define REG_CLKCTRL_SYS_CTRL_MASK_GATE2_UV_MSK (0x1ul << REG_CLKCTRL_SYS_CTRL_MASK_GATE2_UV_POS)
|
|
#define REG_CLKCTRL_SYS_CTRL_MASK_GATE2_UV_SET(num) (((num) << REG_CLKCTRL_SYS_CTRL_MASK_GATE2_UV_POS ) & REG_CLKCTRL_SYS_CTRL_MASK_GATE2_UV_MSK)
|
|
|
|
#define REG_CLKCTRL_SYS_CTRL_MASK_GATE3_UV_POS 13
|
|
#define REG_CLKCTRL_SYS_CTRL_MASK_GATE3_UV_MSK (0x1ul << REG_CLKCTRL_SYS_CTRL_MASK_GATE3_UV_POS)
|
|
#define REG_CLKCTRL_SYS_CTRL_MASK_GATE3_UV_SET(num) (((num) << REG_CLKCTRL_SYS_CTRL_MASK_GATE3_UV_POS ) & REG_CLKCTRL_SYS_CTRL_MASK_GATE3_UV_MSK)
|
|
|
|
#define REG_CLKCTRL_SYS_CTRL_MASK_V2_OCP_POS 14
|
|
#define REG_CLKCTRL_SYS_CTRL_MASK_V2_OCP_MSK (0x1ul << REG_CLKCTRL_SYS_CTRL_MASK_V2_OCP_POS)
|
|
#define REG_CLKCTRL_SYS_CTRL_MASK_V2_OCP_SET(num) (((num) << REG_CLKCTRL_SYS_CTRL_MASK_V2_OCP_POS ) & REG_CLKCTRL_SYS_CTRL_MASK_V2_OCP_MSK)
|
|
|
|
#define REG_CLKCTRL_SYS_CTRL_MASK_I2C1_POS 15
|
|
#define REG_CLKCTRL_SYS_CTRL_MASK_I2C1_MSK (0x1ul << REG_CLKCTRL_SYS_CTRL_MASK_I2C1_POS)
|
|
#define REG_CLKCTRL_SYS_CTRL_MASK_I2C1_SET(num) (((num) << REG_CLKCTRL_SYS_CTRL_MASK_I2C1_POS ) & REG_CLKCTRL_SYS_CTRL_MASK_I2C1_MSK)
|
|
|
|
#define REG_CLKCTRL_SYS_CTRL_MASK_I2C2_POS 16
|
|
#define REG_CLKCTRL_SYS_CTRL_MASK_I2C2_MSK (0x1ul << REG_CLKCTRL_SYS_CTRL_MASK_I2C2_POS)
|
|
#define REG_CLKCTRL_SYS_CTRL_MASK_I2C2_SET(num) (((num) << REG_CLKCTRL_SYS_CTRL_MASK_I2C2_POS ) & REG_CLKCTRL_SYS_CTRL_MASK_I2C2_MSK)
|
|
|
|
#define REG_CLKCTRL_SYS_CTRL_MASK_CS1_POS 17
|
|
#define REG_CLKCTRL_SYS_CTRL_MASK_CS1_MSK (0x1ul << REG_CLKCTRL_SYS_CTRL_MASK_CS1_POS)
|
|
#define REG_CLKCTRL_SYS_CTRL_MASK_CS1_SET(num) (((num) << REG_CLKCTRL_SYS_CTRL_MASK_CS1_POS ) & REG_CLKCTRL_SYS_CTRL_MASK_CS1_MSK)
|
|
|
|
#define REG_CLKCTRL_SYS_CTRL_MASK_CS2_POS 18
|
|
#define REG_CLKCTRL_SYS_CTRL_MASK_CS2_MSK (0x1ul << REG_CLKCTRL_SYS_CTRL_MASK_CS2_POS)
|
|
#define REG_CLKCTRL_SYS_CTRL_MASK_CS2_SET(num) (((num) << REG_CLKCTRL_SYS_CTRL_MASK_CS2_POS ) & REG_CLKCTRL_SYS_CTRL_MASK_CS2_MSK)
|
|
|
|
#define REG_CLKCTRL_SYS_CTRL_MASK_PD1_CC_COMP_ENTRY_POS 19
|
|
#define REG_CLKCTRL_SYS_CTRL_MASK_PD1_CC_COMP_ENTRY_MSK (0x1ul << REG_CLKCTRL_SYS_CTRL_MASK_PD1_CC_COMP_ENTRY_POS)
|
|
#define REG_CLKCTRL_SYS_CTRL_MASK_PD1_CC_COMP_ENTRY_SET(num) (((num) << REG_CLKCTRL_SYS_CTRL_MASK_PD1_CC_COMP_ENTRY_POS ) & REG_CLKCTRL_SYS_CTRL_MASK_PD1_CC_COMP_ENTRY_MSK)
|
|
|
|
#define REG_CLKCTRL_SYS_CTRL_MASK_PD1_CC_COMP_EXIT_POS 20
|
|
#define REG_CLKCTRL_SYS_CTRL_MASK_PD1_CC_COMP_EXIT_MSK (0x1ul << REG_CLKCTRL_SYS_CTRL_MASK_PD1_CC_COMP_EXIT_POS)
|
|
#define REG_CLKCTRL_SYS_CTRL_MASK_PD1_CC_COMP_EXIT_SET(num) (((num) << REG_CLKCTRL_SYS_CTRL_MASK_PD1_CC_COMP_EXIT_POS ) & REG_CLKCTRL_SYS_CTRL_MASK_PD1_CC_COMP_EXIT_MSK)
|
|
|
|
#define REG_CLKCTRL_SYS_CTRL_MASK_PD1_BMC_POS 21
|
|
#define REG_CLKCTRL_SYS_CTRL_MASK_PD1_BMC_MSK (0x1ul << REG_CLKCTRL_SYS_CTRL_MASK_PD1_BMC_POS)
|
|
#define REG_CLKCTRL_SYS_CTRL_MASK_PD1_BMC_SET(num) (((num) << REG_CLKCTRL_SYS_CTRL_MASK_PD1_BMC_POS ) & REG_CLKCTRL_SYS_CTRL_MASK_PD1_BMC_MSK)
|
|
|
|
#define REG_CLKCTRL_SYS_CTRL_MASK_DPDN1_0P4V_POS 22
|
|
#define REG_CLKCTRL_SYS_CTRL_MASK_DPDN1_0P4V_MSK (0x1ul << REG_CLKCTRL_SYS_CTRL_MASK_DPDN1_0P4V_POS)
|
|
#define REG_CLKCTRL_SYS_CTRL_MASK_DPDN1_0P4V_SET(num) (((num) << REG_CLKCTRL_SYS_CTRL_MASK_DPDN1_0P4V_POS ) & REG_CLKCTRL_SYS_CTRL_MASK_DPDN1_0P4V_MSK)
|
|
|
|
#define REG_CLKCTRL_SYS_CTRL_MASK_DPDN1_2P0V_POS 23
|
|
#define REG_CLKCTRL_SYS_CTRL_MASK_DPDN1_2P0V_MSK (0x1ul << REG_CLKCTRL_SYS_CTRL_MASK_DPDN1_2P0V_POS)
|
|
#define REG_CLKCTRL_SYS_CTRL_MASK_DPDN1_2P0V_SET(num) (((num) << REG_CLKCTRL_SYS_CTRL_MASK_DPDN1_2P0V_POS ) & REG_CLKCTRL_SYS_CTRL_MASK_DPDN1_2P0V_MSK)
|
|
|
|
#define REG_CLKCTRL_SYS_CTRL_MASK_DPDN1_1P2V_POS 24
|
|
#define REG_CLKCTRL_SYS_CTRL_MASK_DPDN1_1P2V_MSK (0x1ul << REG_CLKCTRL_SYS_CTRL_MASK_DPDN1_1P2V_POS)
|
|
#define REG_CLKCTRL_SYS_CTRL_MASK_DPDN1_1P2V_SET(num) (((num) << REG_CLKCTRL_SYS_CTRL_MASK_DPDN1_1P2V_POS ) & REG_CLKCTRL_SYS_CTRL_MASK_DPDN1_1P2V_MSK)
|
|
|
|
#define REG_CLKCTRL_SYS_CTRL_MASK_DPDN1_OV_POS 25
|
|
#define REG_CLKCTRL_SYS_CTRL_MASK_DPDN1_OV_MSK (0x1ul << REG_CLKCTRL_SYS_CTRL_MASK_DPDN1_OV_POS)
|
|
#define REG_CLKCTRL_SYS_CTRL_MASK_DPDN1_OV_SET(num) (((num) << REG_CLKCTRL_SYS_CTRL_MASK_DPDN1_OV_POS ) & REG_CLKCTRL_SYS_CTRL_MASK_DPDN1_OV_MSK)
|
|
|
|
#define REG_CLKCTRL_SYS_CTRL_MASK_PD1_CCX_OV_POS 26
|
|
#define REG_CLKCTRL_SYS_CTRL_MASK_PD1_CCX_OV_MSK (0x1ul << REG_CLKCTRL_SYS_CTRL_MASK_PD1_CCX_OV_POS)
|
|
#define REG_CLKCTRL_SYS_CTRL_MASK_PD1_CCX_OV_SET(num) (((num) << REG_CLKCTRL_SYS_CTRL_MASK_PD1_CCX_OV_POS ) & REG_CLKCTRL_SYS_CTRL_MASK_PD1_CCX_OV_MSK)
|
|
|
|
#define REG_CLKCTRL_SYS_CTRL_MASK_PD1_VCON_OC_POS 27
|
|
#define REG_CLKCTRL_SYS_CTRL_MASK_PD1_VCON_OC_MSK (0x1ul << REG_CLKCTRL_SYS_CTRL_MASK_PD1_VCON_OC_POS)
|
|
#define REG_CLKCTRL_SYS_CTRL_MASK_PD1_VCON_OC_SET(num) (((num) << REG_CLKCTRL_SYS_CTRL_MASK_PD1_VCON_OC_POS ) & REG_CLKCTRL_SYS_CTRL_MASK_PD1_VCON_OC_MSK)
|
|
|
|
#define REG_CLKCTRL_SYS_CTRL_MASK_PD1_CCX_STATUS_POS 28
|
|
#define REG_CLKCTRL_SYS_CTRL_MASK_PD1_CCX_STATUS_MSK (0x1ul << REG_CLKCTRL_SYS_CTRL_MASK_PD1_CCX_STATUS_POS)
|
|
#define REG_CLKCTRL_SYS_CTRL_MASK_PD1_CCX_STATUS_SET(num) (((num) << REG_CLKCTRL_SYS_CTRL_MASK_PD1_CCX_STATUS_POS ) & REG_CLKCTRL_SYS_CTRL_MASK_PD1_CCX_STATUS_MSK)
|
|
|
|
#define REG_CLKCTRL_SYS_CTRL_TRIM_MCU_START_DIS_POS 29
|
|
#define REG_CLKCTRL_SYS_CTRL_TRIM_MCU_START_DIS_MSK (0x1ul << REG_CLKCTRL_SYS_CTRL_TRIM_MCU_START_DIS_POS)
|
|
#define REG_CLKCTRL_SYS_CTRL_TRIM_MCU_START_DIS_SET(num) (((num) << REG_CLKCTRL_SYS_CTRL_TRIM_MCU_START_DIS_POS ) & REG_CLKCTRL_SYS_CTRL_TRIM_MCU_START_DIS_MSK)
|
|
|
|
#define REG_CLKCTRL_SYS_CTRL_TRIM_TRIM_START_DIS_POS 30
|
|
#define REG_CLKCTRL_SYS_CTRL_TRIM_TRIM_START_DIS_MSK (0x1ul << REG_CLKCTRL_SYS_CTRL_TRIM_TRIM_START_DIS_POS)
|
|
#define REG_CLKCTRL_SYS_CTRL_TRIM_TRIM_START_DIS_SET(num) (((num) << REG_CLKCTRL_SYS_CTRL_TRIM_TRIM_START_DIS_POS ) & REG_CLKCTRL_SYS_CTRL_TRIM_TRIM_START_DIS_MSK)
|
|
|
|
#define REG_CLKCTRL_SYS_CTRL_TRIM_DIS_POS 31
|
|
#define REG_CLKCTRL_SYS_CTRL_TRIM_DIS_MSK (0x1ul << REG_CLKCTRL_SYS_CTRL_TRIM_DIS_POS)
|
|
#define REG_CLKCTRL_SYS_CTRL_TRIM_DIS_SET(num) (((num) << REG_CLKCTRL_SYS_CTRL_TRIM_DIS_POS ) & REG_CLKCTRL_SYS_CTRL_TRIM_DIS_MSK)
|
|
|
|
#define REG_CLKCTRL_PERI_CG_TIMER0_EN_POS 0
|
|
#define REG_CLKCTRL_PERI_CG_TIMER0_EN_MSK (0x1ul << REG_CLKCTRL_PERI_CG_TIMER0_EN_POS)
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#define REG_CLKCTRL_PERI_CG_TIMER0_EN_SET(num) (((num) << REG_CLKCTRL_PERI_CG_TIMER0_EN_POS ) & REG_CLKCTRL_PERI_CG_TIMER0_EN_MSK)
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#define REG_CLKCTRL_PERI_CG_TIMER1_EN_POS 1
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#define REG_CLKCTRL_PERI_CG_TIMER1_EN_MSK (0x1ul << REG_CLKCTRL_PERI_CG_TIMER1_EN_POS)
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#define REG_CLKCTRL_PERI_CG_TIMER1_EN_SET(num) (((num) << REG_CLKCTRL_PERI_CG_TIMER1_EN_POS ) & REG_CLKCTRL_PERI_CG_TIMER1_EN_MSK)
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#define REG_CLKCTRL_PERI_CG_TIMER2_EN_POS 2
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#define REG_CLKCTRL_PERI_CG_TIMER2_EN_MSK (0x1ul << REG_CLKCTRL_PERI_CG_TIMER2_EN_POS)
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#define REG_CLKCTRL_PERI_CG_TIMER2_EN_SET(num) (((num) << REG_CLKCTRL_PERI_CG_TIMER2_EN_POS ) & REG_CLKCTRL_PERI_CG_TIMER2_EN_MSK)
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#define REG_CLKCTRL_PERI_CG_UART1_EN_POS 3
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#define REG_CLKCTRL_PERI_CG_UART1_EN_MSK (0x1ul << REG_CLKCTRL_PERI_CG_UART1_EN_POS)
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#define REG_CLKCTRL_PERI_CG_UART1_EN_SET(num) (((num) << REG_CLKCTRL_PERI_CG_UART1_EN_POS ) & REG_CLKCTRL_PERI_CG_UART1_EN_MSK)
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#define REG_CLKCTRL_PERI_CG_UART2_EN_POS 4
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#define REG_CLKCTRL_PERI_CG_UART2_EN_MSK (0x1ul << REG_CLKCTRL_PERI_CG_UART2_EN_POS)
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#define REG_CLKCTRL_PERI_CG_UART2_EN_SET(num) (((num) << REG_CLKCTRL_PERI_CG_UART2_EN_POS ) & REG_CLKCTRL_PERI_CG_UART2_EN_MSK)
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#define REG_CLKCTRL_PERI_CG_ADC_EN_POS 5
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#define REG_CLKCTRL_PERI_CG_ADC_EN_MSK (0x1ul << REG_CLKCTRL_PERI_CG_ADC_EN_POS)
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#define REG_CLKCTRL_PERI_CG_ADC_EN_SET(num) (((num) << REG_CLKCTRL_PERI_CG_ADC_EN_POS ) & REG_CLKCTRL_PERI_CG_ADC_EN_MSK)
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#define REG_CLKCTRL_PERI_CG_DAC_CTRL_EN_POS 6
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#define REG_CLKCTRL_PERI_CG_DAC_CTRL_EN_MSK (0x1ul << REG_CLKCTRL_PERI_CG_DAC_CTRL_EN_POS)
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#define REG_CLKCTRL_PERI_CG_DAC_CTRL_EN_SET(num) (((num) << REG_CLKCTRL_PERI_CG_DAC_CTRL_EN_POS ) & REG_CLKCTRL_PERI_CG_DAC_CTRL_EN_MSK)
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#define REG_CLKCTRL_PERI_CG_I2C_MASTER0_EN_POS 7
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#define REG_CLKCTRL_PERI_CG_I2C_MASTER0_EN_MSK (0x1ul << REG_CLKCTRL_PERI_CG_I2C_MASTER0_EN_POS)
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#define REG_CLKCTRL_PERI_CG_I2C_MASTER0_EN_SET(num) (((num) << REG_CLKCTRL_PERI_CG_I2C_MASTER0_EN_POS ) & REG_CLKCTRL_PERI_CG_I2C_MASTER0_EN_MSK)
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#define REG_CLKCTRL_PERI_CG_I2C_MASTER1_EN_POS 8
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#define REG_CLKCTRL_PERI_CG_I2C_MASTER1_EN_MSK (0x1ul << REG_CLKCTRL_PERI_CG_I2C_MASTER1_EN_POS)
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#define REG_CLKCTRL_PERI_CG_I2C_MASTER1_EN_SET(num) (((num) << REG_CLKCTRL_PERI_CG_I2C_MASTER1_EN_POS ) & REG_CLKCTRL_PERI_CG_I2C_MASTER1_EN_MSK)
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#define REG_CLKCTRL_PERI_CG_VD_EN_POS 9
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#define REG_CLKCTRL_PERI_CG_VD_EN_MSK (0x1ul << REG_CLKCTRL_PERI_CG_VD_EN_POS)
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#define REG_CLKCTRL_PERI_CG_VD_EN_SET(num) (((num) << REG_CLKCTRL_PERI_CG_VD_EN_POS ) & REG_CLKCTRL_PERI_CG_VD_EN_MSK)
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#define REG_CLKCTRL_PERI_CG_PWD0_EN_POS 10
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#define REG_CLKCTRL_PERI_CG_PWD0_EN_MSK (0x1ul << REG_CLKCTRL_PERI_CG_PWD0_EN_POS)
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#define REG_CLKCTRL_PERI_CG_PWD0_EN_SET(num) (((num) << REG_CLKCTRL_PERI_CG_PWD0_EN_POS ) & REG_CLKCTRL_PERI_CG_PWD0_EN_MSK)
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#define REG_CLKCTRL_PERI_CG_PWD1_EN_POS 11
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#define REG_CLKCTRL_PERI_CG_PWD1_EN_MSK (0x1ul << REG_CLKCTRL_PERI_CG_PWD1_EN_POS)
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#define REG_CLKCTRL_PERI_CG_PWD1_EN_SET(num) (((num) << REG_CLKCTRL_PERI_CG_PWD1_EN_POS ) & REG_CLKCTRL_PERI_CG_PWD1_EN_MSK)
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#define REG_CLKCTRL_PERI_CG_PWD2_EN_POS 12
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#define REG_CLKCTRL_PERI_CG_PWD2_EN_MSK (0x1ul << REG_CLKCTRL_PERI_CG_PWD2_EN_POS)
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#define REG_CLKCTRL_PERI_CG_PWD2_EN_SET(num) (((num) << REG_CLKCTRL_PERI_CG_PWD2_EN_POS ) & REG_CLKCTRL_PERI_CG_PWD2_EN_MSK)
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#define REG_CLKCTRL_PERI_CG_PWD3_EN_POS 13
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#define REG_CLKCTRL_PERI_CG_PWD3_EN_MSK (0x1ul << REG_CLKCTRL_PERI_CG_PWD3_EN_POS)
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#define REG_CLKCTRL_PERI_CG_PWD3_EN_SET(num) (((num) << REG_CLKCTRL_PERI_CG_PWD3_EN_POS ) & REG_CLKCTRL_PERI_CG_PWD3_EN_MSK)
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#define REG_CLKCTRL_PERI_CG_PD0_H_EN_POS 14
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#define REG_CLKCTRL_PERI_CG_PD0_H_EN_MSK (0x1ul << REG_CLKCTRL_PERI_CG_PD0_H_EN_POS)
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#define REG_CLKCTRL_PERI_CG_PD0_H_EN_SET(num) (((num) << REG_CLKCTRL_PERI_CG_PD0_H_EN_POS ) & REG_CLKCTRL_PERI_CG_PD0_H_EN_MSK)
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#define REG_CLKCTRL_PERI_CG_PD1_H_EN_POS 15
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#define REG_CLKCTRL_PERI_CG_PD1_H_EN_MSK (0x1ul << REG_CLKCTRL_PERI_CG_PD1_H_EN_POS)
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#define REG_CLKCTRL_PERI_CG_PD1_H_EN_SET(num) (((num) << REG_CLKCTRL_PERI_CG_PD1_H_EN_POS ) & REG_CLKCTRL_PERI_CG_PD1_H_EN_MSK)
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#define REG_CLKCTRL_PERI_CG_PD0_L_EN_POS 16
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#define REG_CLKCTRL_PERI_CG_PD0_L_EN_MSK (0x1ul << REG_CLKCTRL_PERI_CG_PD0_L_EN_POS)
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#define REG_CLKCTRL_PERI_CG_PD0_L_EN_SET(num) (((num) << REG_CLKCTRL_PERI_CG_PD0_L_EN_POS ) & REG_CLKCTRL_PERI_CG_PD0_L_EN_MSK)
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#define REG_CLKCTRL_PERI_CG_PD1_L_EN_POS 17
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#define REG_CLKCTRL_PERI_CG_PD1_L_EN_MSK (0x1ul << REG_CLKCTRL_PERI_CG_PD1_L_EN_POS)
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#define REG_CLKCTRL_PERI_CG_PD1_L_EN_SET(num) (((num) << REG_CLKCTRL_PERI_CG_PD1_L_EN_POS ) & REG_CLKCTRL_PERI_CG_PD1_L_EN_MSK)
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#define REG_CLKCTRL_PERI_CG_UFCS0_EN_POS 18
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#define REG_CLKCTRL_PERI_CG_UFCS0_EN_MSK (0x1ul << REG_CLKCTRL_PERI_CG_UFCS0_EN_POS)
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#define REG_CLKCTRL_PERI_CG_UFCS0_EN_SET(num) (((num) << REG_CLKCTRL_PERI_CG_UFCS0_EN_POS ) & REG_CLKCTRL_PERI_CG_UFCS0_EN_MSK)
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#define REG_CLKCTRL_PERI_CG_UFCS1_EN_POS 19
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#define REG_CLKCTRL_PERI_CG_UFCS1_EN_MSK (0x1ul << REG_CLKCTRL_PERI_CG_UFCS1_EN_POS)
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#define REG_CLKCTRL_PERI_CG_UFCS1_EN_SET(num) (((num) << REG_CLKCTRL_PERI_CG_UFCS1_EN_POS ) & REG_CLKCTRL_PERI_CG_UFCS1_EN_MSK)
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#define REG_CLKCTRL_PERI_CG_SCP0_EN_POS 20
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#define REG_CLKCTRL_PERI_CG_SCP0_EN_MSK (0x1ul << REG_CLKCTRL_PERI_CG_SCP0_EN_POS)
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#define REG_CLKCTRL_PERI_CG_SCP0_EN_SET(num) (((num) << REG_CLKCTRL_PERI_CG_SCP0_EN_POS ) & REG_CLKCTRL_PERI_CG_SCP0_EN_MSK)
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#define REG_CLKCTRL_PERI_CG_SCP1_EN_POS 21
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#define REG_CLKCTRL_PERI_CG_SCP1_EN_MSK (0x1ul << REG_CLKCTRL_PERI_CG_SCP1_EN_POS)
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#define REG_CLKCTRL_PERI_CG_SCP1_EN_SET(num) (((num) << REG_CLKCTRL_PERI_CG_SCP1_EN_POS ) & REG_CLKCTRL_PERI_CG_SCP1_EN_MSK)
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#define REG_CLKCTRL_PERI_CG_WDOG_EN_POS 22
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#define REG_CLKCTRL_PERI_CG_WDOG_EN_MSK (0x1ul << REG_CLKCTRL_PERI_CG_WDOG_EN_POS)
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#define REG_CLKCTRL_PERI_CG_WDOG_EN_SET(num) (((num) << REG_CLKCTRL_PERI_CG_WDOG_EN_POS ) & REG_CLKCTRL_PERI_CG_WDOG_EN_MSK)
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#define REG_CLKCTRL_PERI_CG_VIN_DIS_EN_POS 23
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#define REG_CLKCTRL_PERI_CG_VIN_DIS_EN_MSK (0x1ul << REG_CLKCTRL_PERI_CG_VIN_DIS_EN_POS)
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#define REG_CLKCTRL_PERI_CG_VIN_DIS_EN_SET(num) (((num) << REG_CLKCTRL_PERI_CG_VIN_DIS_EN_POS ) & REG_CLKCTRL_PERI_CG_VIN_DIS_EN_MSK)
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#define REG_CLKCTRL_SYS_RSTREQ_MCU_POS 0
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#define REG_CLKCTRL_SYS_RSTREQ_MCU_MSK (0x1ul << REG_CLKCTRL_SYS_RSTREQ_MCU_POS)
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#define REG_CLKCTRL_SYS_RSTREQ_MCU_SET(num) (((num) << REG_CLKCTRL_SYS_RSTREQ_MCU_POS ) & REG_CLKCTRL_SYS_RSTREQ_MCU_MSK)
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#define REG_CLKCTRL_SYS_RSTREQ_APB_POS 8
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#define REG_CLKCTRL_SYS_RSTREQ_APB_MSK (0x1ul << REG_CLKCTRL_SYS_RSTREQ_APB_POS)
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#define REG_CLKCTRL_SYS_RSTREQ_APB_SET(num) (((num) << REG_CLKCTRL_SYS_RSTREQ_APB_POS ) & REG_CLKCTRL_SYS_RSTREQ_APB_MSK)
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#define REG_CLKCTRL_SYS_RSTREQ_MCU_HOLD_POS 16
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#define REG_CLKCTRL_SYS_RSTREQ_MCU_HOLD_MSK (0x1ul << REG_CLKCTRL_SYS_RSTREQ_MCU_HOLD_POS)
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#define REG_CLKCTRL_SYS_RSTREQ_MCU_HOLD_SET(num) (((num) << REG_CLKCTRL_SYS_RSTREQ_MCU_HOLD_POS ) & REG_CLKCTRL_SYS_RSTREQ_MCU_HOLD_MSK)
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#define REG_CLKCTRL_SYS_RSTREQ_SYSTEM_POS 24
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#define REG_CLKCTRL_SYS_RSTREQ_SYSTEM_MSK (0x1ul << REG_CLKCTRL_SYS_RSTREQ_SYSTEM_POS)
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#define REG_CLKCTRL_SYS_RSTREQ_SYSTEM_SET(num) (((num) << REG_CLKCTRL_SYS_RSTREQ_SYSTEM_POS ) & REG_CLKCTRL_SYS_RSTREQ_SYSTEM_MSK)
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#define REG_CLKCTRL_PIN_MUL_SET_GP0_POS 0
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#define REG_CLKCTRL_PIN_MUL_SET_GP0_MSK (0x3ul << REG_CLKCTRL_PIN_MUL_SET_GP0_POS)
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#define REG_CLKCTRL_PIN_MUL_SET_GP0_SET(num) (((num) << REG_CLKCTRL_PIN_MUL_SET_GP0_POS ) & REG_CLKCTRL_PIN_MUL_SET_GP0_MSK)
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#define REG_CLKCTRL_PIN_MUL_SET_GP1_POS 2
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#define REG_CLKCTRL_PIN_MUL_SET_GP1_MSK (0x3ul << REG_CLKCTRL_PIN_MUL_SET_GP1_POS)
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#define REG_CLKCTRL_PIN_MUL_SET_GP1_SET(num) (((num) << REG_CLKCTRL_PIN_MUL_SET_GP1_POS ) & REG_CLKCTRL_PIN_MUL_SET_GP1_MSK)
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#define REG_CLKCTRL_PIN_MUL_SET_GP2_POS 4
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#define REG_CLKCTRL_PIN_MUL_SET_GP2_MSK (0x3ul << REG_CLKCTRL_PIN_MUL_SET_GP2_POS)
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#define REG_CLKCTRL_PIN_MUL_SET_GP2_SET(num) (((num) << REG_CLKCTRL_PIN_MUL_SET_GP2_POS ) & REG_CLKCTRL_PIN_MUL_SET_GP2_MSK)
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#define REG_CLKCTRL_PIN_MUL_SET_GP3_POS 6
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#define REG_CLKCTRL_PIN_MUL_SET_GP3_MSK (0x3ul << REG_CLKCTRL_PIN_MUL_SET_GP3_POS)
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#define REG_CLKCTRL_PIN_MUL_SET_GP3_SET(num) (((num) << REG_CLKCTRL_PIN_MUL_SET_GP3_POS ) & REG_CLKCTRL_PIN_MUL_SET_GP3_MSK)
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#define REG_CLKCTRL_PIN_MUL_SET_GP4_POS 8
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#define REG_CLKCTRL_PIN_MUL_SET_GP4_MSK (0x3ul << REG_CLKCTRL_PIN_MUL_SET_GP4_POS)
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#define REG_CLKCTRL_PIN_MUL_SET_GP4_SET(num) (((num) << REG_CLKCTRL_PIN_MUL_SET_GP4_POS ) & REG_CLKCTRL_PIN_MUL_SET_GP4_MSK)
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#define REG_CLKCTRL_PIN_MUL_SET_GP5_POS 10
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#define REG_CLKCTRL_PIN_MUL_SET_GP5_MSK (0x3ul << REG_CLKCTRL_PIN_MUL_SET_GP5_POS)
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#define REG_CLKCTRL_PIN_MUL_SET_GP5_SET(num) (((num) << REG_CLKCTRL_PIN_MUL_SET_GP5_POS ) & REG_CLKCTRL_PIN_MUL_SET_GP5_MSK)
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#define REG_CLKCTRL_PIN_MUL_SET_CC1_1_POS 12
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#define REG_CLKCTRL_PIN_MUL_SET_CC1_1_MSK (0x3ul << REG_CLKCTRL_PIN_MUL_SET_CC1_1_POS)
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#define REG_CLKCTRL_PIN_MUL_SET_CC1_1_SET(num) (((num) << REG_CLKCTRL_PIN_MUL_SET_CC1_1_POS ) & REG_CLKCTRL_PIN_MUL_SET_CC1_1_MSK)
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#define REG_CLKCTRL_PIN_MUL_SET_CC2_1_POS 14
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#define REG_CLKCTRL_PIN_MUL_SET_CC2_1_MSK (0x3ul << REG_CLKCTRL_PIN_MUL_SET_CC2_1_POS)
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#define REG_CLKCTRL_PIN_MUL_SET_CC2_1_SET(num) (((num) << REG_CLKCTRL_PIN_MUL_SET_CC2_1_POS ) & REG_CLKCTRL_PIN_MUL_SET_CC2_1_MSK)
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#define REG_CLKCTRL_PIN_MUL_SET_CC1_2_POS 16
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#define REG_CLKCTRL_PIN_MUL_SET_CC1_2_MSK (0x3ul << REG_CLKCTRL_PIN_MUL_SET_CC1_2_POS)
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#define REG_CLKCTRL_PIN_MUL_SET_CC1_2_SET(num) (((num) << REG_CLKCTRL_PIN_MUL_SET_CC1_2_POS ) & REG_CLKCTRL_PIN_MUL_SET_CC1_2_MSK)
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#define REG_CLKCTRL_PIN_MUL_SET_CC2_2_POS 18
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#define REG_CLKCTRL_PIN_MUL_SET_CC2_2_MSK (0x3ul << REG_CLKCTRL_PIN_MUL_SET_CC2_2_POS)
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#define REG_CLKCTRL_PIN_MUL_SET_CC2_2_SET(num) (((num) << REG_CLKCTRL_PIN_MUL_SET_CC2_2_POS ) & REG_CLKCTRL_PIN_MUL_SET_CC2_2_MSK)
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#define REG_CLKCTRL_PIN_MUL_SET_FB1_POS 20
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#define REG_CLKCTRL_PIN_MUL_SET_FB1_MSK (0x3ul << REG_CLKCTRL_PIN_MUL_SET_FB1_POS)
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#define REG_CLKCTRL_PIN_MUL_SET_FB1_SET(num) (((num) << REG_CLKCTRL_PIN_MUL_SET_FB1_POS ) & REG_CLKCTRL_PIN_MUL_SET_FB1_MSK)
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#define REG_CLKCTRL_PIN_MUL_SET_COMP1_POS 22
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#define REG_CLKCTRL_PIN_MUL_SET_COMP1_MSK (0x3ul << REG_CLKCTRL_PIN_MUL_SET_COMP1_POS)
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#define REG_CLKCTRL_PIN_MUL_SET_COMP1_SET(num) (((num) << REG_CLKCTRL_PIN_MUL_SET_COMP1_POS ) & REG_CLKCTRL_PIN_MUL_SET_COMP1_MSK)
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#define REG_CLKCTRL_PIN_MUL_SET_FB2_POS 24
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#define REG_CLKCTRL_PIN_MUL_SET_FB2_MSK (0x3ul << REG_CLKCTRL_PIN_MUL_SET_FB2_POS)
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#define REG_CLKCTRL_PIN_MUL_SET_FB2_SET(num) (((num) << REG_CLKCTRL_PIN_MUL_SET_FB2_POS ) & REG_CLKCTRL_PIN_MUL_SET_FB2_MSK)
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#define REG_CLKCTRL_PIN_MUL_SET_COMP2_POS 26
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#define REG_CLKCTRL_PIN_MUL_SET_COMP2_MSK (0x3ul << REG_CLKCTRL_PIN_MUL_SET_COMP2_POS)
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#define REG_CLKCTRL_PIN_MUL_SET_COMP2_SET(num) (((num) << REG_CLKCTRL_PIN_MUL_SET_COMP2_POS ) & REG_CLKCTRL_PIN_MUL_SET_COMP2_MSK)
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#define REG_CLKCTRL_PIN_MUL_SET_VFB_POS 28
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#define REG_CLKCTRL_PIN_MUL_SET_VFB_MSK (0x3ul << REG_CLKCTRL_PIN_MUL_SET_VFB_POS)
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#define REG_CLKCTRL_PIN_MUL_SET_VFB_SET(num) (((num) << REG_CLKCTRL_PIN_MUL_SET_VFB_POS ) & REG_CLKCTRL_PIN_MUL_SET_VFB_MSK)
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#define REG_CLKCTRL_PIN_MUL_SET_IFB_POS 30
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#define REG_CLKCTRL_PIN_MUL_SET_IFB_MSK (0x3ul << REG_CLKCTRL_PIN_MUL_SET_IFB_POS)
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#define REG_CLKCTRL_PIN_MUL_SET_IFB_SET(num) (((num) << REG_CLKCTRL_PIN_MUL_SET_IFB_POS ) & REG_CLKCTRL_PIN_MUL_SET_IFB_MSK)
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#define REG_CLKCTRL_MEM_SRAM_2P5K_S_POS 0
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#define REG_CLKCTRL_MEM_SRAM_2P5K_S_MSK (0xFul << REG_CLKCTRL_MEM_SRAM_2P5K_S_POS)
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#define REG_CLKCTRL_MEM_SRAM_2P5K_S_SET(num) (((num) << REG_CLKCTRL_MEM_SRAM_2P5K_S_POS ) & REG_CLKCTRL_MEM_SRAM_2P5K_S_MSK)
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#define REG_CLKCTRL_MEM_SRAM_2P5K_SL_POS 4
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#define REG_CLKCTRL_MEM_SRAM_2P5K_SL_MSK (0x1ul << REG_CLKCTRL_MEM_SRAM_2P5K_SL_POS)
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#define REG_CLKCTRL_MEM_SRAM_2P5K_SL_SET(num) (((num) << REG_CLKCTRL_MEM_SRAM_2P5K_SL_POS ) & REG_CLKCTRL_MEM_SRAM_2P5K_SL_MSK)
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#define REG_CLKCTRL_MEM_SRAM_2P5K_SD_POS 5
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#define REG_CLKCTRL_MEM_SRAM_2P5K_SD_MSK (0x1ul << REG_CLKCTRL_MEM_SRAM_2P5K_SD_POS)
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#define REG_CLKCTRL_MEM_SRAM_2P5K_SD_SET(num) (((num) << REG_CLKCTRL_MEM_SRAM_2P5K_SD_POS ) & REG_CLKCTRL_MEM_SRAM_2P5K_SD_MSK)
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#define REG_CLKCTRL_MEM_SRAM_2P5K_VCSB_POS 6
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#define REG_CLKCTRL_MEM_SRAM_2P5K_VCSB_MSK (0x1ul << REG_CLKCTRL_MEM_SRAM_2P5K_VCSB_POS)
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#define REG_CLKCTRL_MEM_SRAM_2P5K_VCSB_SET(num) (((num) << REG_CLKCTRL_MEM_SRAM_2P5K_VCSB_POS ) & REG_CLKCTRL_MEM_SRAM_2P5K_VCSB_MSK)
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#define REG_CLKCTRL_DTEST_SEL1_POS 0
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#define REG_CLKCTRL_DTEST_SEL1_MSK (0x7Ful << REG_CLKCTRL_DTEST_SEL1_POS)
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#define REG_CLKCTRL_DTEST_SEL1_SET(num) (((num) << REG_CLKCTRL_DTEST_SEL1_POS ) & REG_CLKCTRL_DTEST_SEL1_MSK)
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#define REG_CLKCTRL_DTEST_SEL2_POS 7
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#define REG_CLKCTRL_DTEST_SEL2_MSK (0x7Ful << REG_CLKCTRL_DTEST_SEL2_POS)
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#define REG_CLKCTRL_DTEST_SEL2_SET(num) (((num) << REG_CLKCTRL_DTEST_SEL2_POS ) & REG_CLKCTRL_DTEST_SEL2_MSK)
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#define REG_CLKCTRL_DTEST_ENABLE1_POS 16
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#define REG_CLKCTRL_DTEST_ENABLE1_MSK (0x1ul << REG_CLKCTRL_DTEST_ENABLE1_POS)
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#define REG_CLKCTRL_DTEST_ENABLE1_SET(num) (((num) << REG_CLKCTRL_DTEST_ENABLE1_POS ) & REG_CLKCTRL_DTEST_ENABLE1_MSK)
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#define REG_CLKCTRL_DTEST_ENABLE2_POS 17
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#define REG_CLKCTRL_DTEST_ENABLE2_MSK (0x1ul << REG_CLKCTRL_DTEST_ENABLE2_POS)
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#define REG_CLKCTRL_DTEST_ENABLE2_SET(num) (((num) << REG_CLKCTRL_DTEST_ENABLE2_POS ) & REG_CLKCTRL_DTEST_ENABLE2_MSK)
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#define REG_CLKCTRL_DTEST_A2D_SEL1_POS 24
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#define REG_CLKCTRL_DTEST_A2D_SEL1_MSK (0x7ul << REG_CLKCTRL_DTEST_A2D_SEL1_POS)
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#define REG_CLKCTRL_DTEST_A2D_SEL1_SET(num) (((num) << REG_CLKCTRL_DTEST_A2D_SEL1_POS ) & REG_CLKCTRL_DTEST_A2D_SEL1_MSK)
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#define REG_CLKCTRL_DTEST_A2D_SEL2_POS 27
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#define REG_CLKCTRL_DTEST_A2D_SEL2_MSK (0x7ul << REG_CLKCTRL_DTEST_A2D_SEL2_POS)
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#define REG_CLKCTRL_DTEST_A2D_SEL2_SET(num) (((num) << REG_CLKCTRL_DTEST_A2D_SEL2_POS ) & REG_CLKCTRL_DTEST_A2D_SEL2_MSK)
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#define REG_CLKCTRL_MBIST_EN_POS 0
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#define REG_CLKCTRL_MBIST_EN_MSK (0x1ul << REG_CLKCTRL_MBIST_EN_POS)
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#define REG_CLKCTRL_MBIST_EN_SET(num) (((num) << REG_CLKCTRL_MBIST_EN_POS ) & REG_CLKCTRL_MBIST_EN_MSK)
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#define REG_CLKCTRL_MBIST_START_POS 1
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#define REG_CLKCTRL_MBIST_START_MSK (0x1ul << REG_CLKCTRL_MBIST_START_POS)
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#define REG_CLKCTRL_MBIST_START_SET(num) (((num) << REG_CLKCTRL_MBIST_START_POS ) & REG_CLKCTRL_MBIST_START_MSK)
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#define REG_CLKCTRL_FILTER_DN_0P4V_POS 0
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#define REG_CLKCTRL_FILTER_DN_0P4V_MSK (0x1ul << REG_CLKCTRL_FILTER_DN_0P4V_POS)
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#define REG_CLKCTRL_FILTER_DN_0P4V_SET(num) (((num) << REG_CLKCTRL_FILTER_DN_0P4V_POS ) & REG_CLKCTRL_FILTER_DN_0P4V_MSK)
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#define REG_CLKCTRL_FILTER_DN_2P0V_POS 1
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#define REG_CLKCTRL_FILTER_DN_2P0V_MSK (0x1ul << REG_CLKCTRL_FILTER_DN_2P0V_POS)
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#define REG_CLKCTRL_FILTER_DN_2P0V_SET(num) (((num) << REG_CLKCTRL_FILTER_DN_2P0V_POS ) & REG_CLKCTRL_FILTER_DN_2P0V_MSK)
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#define REG_CLKCTRL_FILTER_DP_0P4V_POS 2
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#define REG_CLKCTRL_FILTER_DP_0P4V_MSK (0x1ul << REG_CLKCTRL_FILTER_DP_0P4V_POS)
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#define REG_CLKCTRL_FILTER_DP_0P4V_SET(num) (((num) << REG_CLKCTRL_FILTER_DP_0P4V_POS ) & REG_CLKCTRL_FILTER_DP_0P4V_MSK)
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#define REG_CLKCTRL_FILTER_DP_2P0V_POS 3
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#define REG_CLKCTRL_FILTER_DP_2P0V_MSK (0x1ul << REG_CLKCTRL_FILTER_DP_2P0V_POS)
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#define REG_CLKCTRL_FILTER_DP_2P0V_SET(num) (((num) << REG_CLKCTRL_FILTER_DP_2P0V_POS ) & REG_CLKCTRL_FILTER_DP_2P0V_MSK)
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#define REG_CLKCTRL_FILTER_DPDN_OV_POS 4
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#define REG_CLKCTRL_FILTER_DPDN_OV_MSK (0x3ul << REG_CLKCTRL_FILTER_DPDN_OV_POS)
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#define REG_CLKCTRL_FILTER_DPDN_OV_SET(num) (((num) << REG_CLKCTRL_FILTER_DPDN_OV_POS ) & REG_CLKCTRL_FILTER_DPDN_OV_MSK)
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#define REG_CLKCTRL_FILTER_DN_IN_POS 6
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#define REG_CLKCTRL_FILTER_DN_IN_MSK (0xFul << REG_CLKCTRL_FILTER_DN_IN_POS)
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#define REG_CLKCTRL_FILTER_DN_IN_SET(num) (((num) << REG_CLKCTRL_FILTER_DN_IN_POS ) & REG_CLKCTRL_FILTER_DN_IN_MSK)
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#define REG_CLKCTRL_FILTER_DP_IN_POS 10
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#define REG_CLKCTRL_FILTER_DP_IN_MSK (0xFul << REG_CLKCTRL_FILTER_DP_IN_POS)
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#define REG_CLKCTRL_FILTER_DP_IN_SET(num) (((num) << REG_CLKCTRL_FILTER_DP_IN_POS ) & REG_CLKCTRL_FILTER_DP_IN_MSK)
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#define REG_CLKCTRL_FILTER_PD_RXD_POS 16
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#define REG_CLKCTRL_FILTER_PD_RXD_MSK (0xFul << REG_CLKCTRL_FILTER_PD_RXD_POS)
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#define REG_CLKCTRL_FILTER_PD_RXD_SET(num) (((num) << REG_CLKCTRL_FILTER_PD_RXD_POS ) & REG_CLKCTRL_FILTER_PD_RXD_MSK)
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#define REG_CLKCTRL_FILTER_PD_CCX_OVP_POS 20
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#define REG_CLKCTRL_FILTER_PD_CCX_OVP_MSK (0x3ul << REG_CLKCTRL_FILTER_PD_CCX_OVP_POS)
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#define REG_CLKCTRL_FILTER_PD_CCX_OVP_SET(num) (((num) << REG_CLKCTRL_FILTER_PD_CCX_OVP_POS ) & REG_CLKCTRL_FILTER_PD_CCX_OVP_MSK)
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#define REG_CLKCTRL_FILTER_VDC_COMP_VBUSOC_POS 22
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#define REG_CLKCTRL_FILTER_VDC_COMP_VBUSOC_MSK (0x1ul << REG_CLKCTRL_FILTER_VDC_COMP_VBUSOC_POS)
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#define REG_CLKCTRL_FILTER_VDC_COMP_VBUSOC_SET(num) (((num) << REG_CLKCTRL_FILTER_VDC_COMP_VBUSOC_POS ) & REG_CLKCTRL_FILTER_VDC_COMP_VBUSOC_MSK)
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#define REG_CLKCTRL_BAUDRATE_VLD_SKEW_POS 0
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#define REG_CLKCTRL_BAUDRATE_VLD_SKEW_MSK (0x1Ful << REG_CLKCTRL_BAUDRATE_VLD_SKEW_POS)
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#define REG_CLKCTRL_BAUDRATE_VLD_SKEW_SET(num) (((num) << REG_CLKCTRL_BAUDRATE_VLD_SKEW_POS ) & REG_CLKCTRL_BAUDRATE_VLD_SKEW_MSK)
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#define REG_CLKCTRL_PIN_MUL_SET1_OPTO_POS 0
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#define REG_CLKCTRL_PIN_MUL_SET1_OPTO_MSK (0x3ul << REG_CLKCTRL_PIN_MUL_SET1_OPTO_POS)
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#define REG_CLKCTRL_PIN_MUL_SET1_OPTO_SET(num) (((num) << REG_CLKCTRL_PIN_MUL_SET1_OPTO_POS ) & REG_CLKCTRL_PIN_MUL_SET1_OPTO_MSK)
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#define REG_CLKCTRL_PIN_MUL_SET1_VD_POS 2
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#define REG_CLKCTRL_PIN_MUL_SET1_VD_MSK (0x3ul << REG_CLKCTRL_PIN_MUL_SET1_VD_POS)
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#define REG_CLKCTRL_PIN_MUL_SET1_VD_SET(num) (((num) << REG_CLKCTRL_PIN_MUL_SET1_VD_POS ) & REG_CLKCTRL_PIN_MUL_SET1_VD_MSK)
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#define REG_CLKCTRL_SYS_CTRL1_MASK_PD2_CC_COMP_ENTRY_POS 0
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#define REG_CLKCTRL_SYS_CTRL1_MASK_PD2_CC_COMP_ENTRY_MSK (0x1ul << REG_CLKCTRL_SYS_CTRL1_MASK_PD2_CC_COMP_ENTRY_POS)
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#define REG_CLKCTRL_SYS_CTRL1_MASK_PD2_CC_COMP_ENTRY_SET(num) (((num) << REG_CLKCTRL_SYS_CTRL1_MASK_PD2_CC_COMP_ENTRY_POS ) & REG_CLKCTRL_SYS_CTRL1_MASK_PD2_CC_COMP_ENTRY_MSK)
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#define REG_CLKCTRL_SYS_CTRL1_MASK_PD2_CC_COMP_EXIT_POS 1
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#define REG_CLKCTRL_SYS_CTRL1_MASK_PD2_CC_COMP_EXIT_MSK (0x1ul << REG_CLKCTRL_SYS_CTRL1_MASK_PD2_CC_COMP_EXIT_POS)
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#define REG_CLKCTRL_SYS_CTRL1_MASK_PD2_CC_COMP_EXIT_SET(num) (((num) << REG_CLKCTRL_SYS_CTRL1_MASK_PD2_CC_COMP_EXIT_POS ) & REG_CLKCTRL_SYS_CTRL1_MASK_PD2_CC_COMP_EXIT_MSK)
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#define REG_CLKCTRL_SYS_CTRL1_MASK_PD2_BMC_POS 2
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#define REG_CLKCTRL_SYS_CTRL1_MASK_PD2_BMC_MSK (0x1ul << REG_CLKCTRL_SYS_CTRL1_MASK_PD2_BMC_POS)
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#define REG_CLKCTRL_SYS_CTRL1_MASK_PD2_BMC_SET(num) (((num) << REG_CLKCTRL_SYS_CTRL1_MASK_PD2_BMC_POS ) & REG_CLKCTRL_SYS_CTRL1_MASK_PD2_BMC_MSK)
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#define REG_CLKCTRL_SYS_CTRL1_MASK_PD2_CCX_OV_POS 3
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#define REG_CLKCTRL_SYS_CTRL1_MASK_PD2_CCX_OV_MSK (0x1ul << REG_CLKCTRL_SYS_CTRL1_MASK_PD2_CCX_OV_POS)
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#define REG_CLKCTRL_SYS_CTRL1_MASK_PD2_CCX_OV_SET(num) (((num) << REG_CLKCTRL_SYS_CTRL1_MASK_PD2_CCX_OV_POS ) & REG_CLKCTRL_SYS_CTRL1_MASK_PD2_CCX_OV_MSK)
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#define REG_CLKCTRL_SYS_CTRL1_MASK_PD2_VCON_OC_POS 4
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#define REG_CLKCTRL_SYS_CTRL1_MASK_PD2_VCON_OC_MSK (0x1ul << REG_CLKCTRL_SYS_CTRL1_MASK_PD2_VCON_OC_POS)
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#define REG_CLKCTRL_SYS_CTRL1_MASK_PD2_VCON_OC_SET(num) (((num) << REG_CLKCTRL_SYS_CTRL1_MASK_PD2_VCON_OC_POS ) & REG_CLKCTRL_SYS_CTRL1_MASK_PD2_VCON_OC_MSK)
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#define REG_CLKCTRL_SYS_CTRL1_MASK_PD2_CCX_STATUS_POS 5
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#define REG_CLKCTRL_SYS_CTRL1_MASK_PD2_CCX_STATUS_MSK (0x1ul << REG_CLKCTRL_SYS_CTRL1_MASK_PD2_CCX_STATUS_POS)
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#define REG_CLKCTRL_SYS_CTRL1_MASK_PD2_CCX_STATUS_SET(num) (((num) << REG_CLKCTRL_SYS_CTRL1_MASK_PD2_CCX_STATUS_POS ) & REG_CLKCTRL_SYS_CTRL1_MASK_PD2_CCX_STATUS_MSK)
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#define REG_CLKCTRL_SYS_CTRL1_MASK_DPDN2_0P4V_POS 6
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#define REG_CLKCTRL_SYS_CTRL1_MASK_DPDN2_0P4V_MSK (0x1ul << REG_CLKCTRL_SYS_CTRL1_MASK_DPDN2_0P4V_POS)
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#define REG_CLKCTRL_SYS_CTRL1_MASK_DPDN2_0P4V_SET(num) (((num) << REG_CLKCTRL_SYS_CTRL1_MASK_DPDN2_0P4V_POS ) & REG_CLKCTRL_SYS_CTRL1_MASK_DPDN2_0P4V_MSK)
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#define REG_CLKCTRL_SYS_CTRL1_MASK_DPDN2_2P0V_POS 7
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#define REG_CLKCTRL_SYS_CTRL1_MASK_DPDN2_2P0V_MSK (0x1ul << REG_CLKCTRL_SYS_CTRL1_MASK_DPDN2_2P0V_POS)
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#define REG_CLKCTRL_SYS_CTRL1_MASK_DPDN2_2P0V_SET(num) (((num) << REG_CLKCTRL_SYS_CTRL1_MASK_DPDN2_2P0V_POS ) & REG_CLKCTRL_SYS_CTRL1_MASK_DPDN2_2P0V_MSK)
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#define REG_CLKCTRL_SYS_CTRL1_MASK_DPDN2_1P2V_POS 8
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#define REG_CLKCTRL_SYS_CTRL1_MASK_DPDN2_1P2V_MSK (0x1ul << REG_CLKCTRL_SYS_CTRL1_MASK_DPDN2_1P2V_POS)
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#define REG_CLKCTRL_SYS_CTRL1_MASK_DPDN2_1P2V_SET(num) (((num) << REG_CLKCTRL_SYS_CTRL1_MASK_DPDN2_1P2V_POS ) & REG_CLKCTRL_SYS_CTRL1_MASK_DPDN2_1P2V_MSK)
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#define REG_CLKCTRL_SYS_CTRL1_MASK_DPDN2_OV_POS 9
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#define REG_CLKCTRL_SYS_CTRL1_MASK_DPDN2_OV_MSK (0x1ul << REG_CLKCTRL_SYS_CTRL1_MASK_DPDN2_OV_POS)
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#define REG_CLKCTRL_SYS_CTRL1_MASK_DPDN2_OV_SET(num) (((num) << REG_CLKCTRL_SYS_CTRL1_MASK_DPDN2_OV_POS ) & REG_CLKCTRL_SYS_CTRL1_MASK_DPDN2_OV_MSK)
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#define REG_CLKCTRL_SYS_CTRL1_MASK_VIN1_UVLO_POS 10
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#define REG_CLKCTRL_SYS_CTRL1_MASK_VIN1_UVLO_MSK (0x1ul << REG_CLKCTRL_SYS_CTRL1_MASK_VIN1_UVLO_POS)
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#define REG_CLKCTRL_SYS_CTRL1_MASK_VIN1_UVLO_SET(num) (((num) << REG_CLKCTRL_SYS_CTRL1_MASK_VIN1_UVLO_POS ) & REG_CLKCTRL_SYS_CTRL1_MASK_VIN1_UVLO_MSK)
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#define REG_CLKCTRL_SYS_CTRL1_MASK_VIN2_UVLO_POS 11
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#define REG_CLKCTRL_SYS_CTRL1_MASK_VIN2_UVLO_MSK (0x1ul << REG_CLKCTRL_SYS_CTRL1_MASK_VIN2_UVLO_POS)
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#define REG_CLKCTRL_SYS_CTRL1_MASK_VIN2_UVLO_SET(num) (((num) << REG_CLKCTRL_SYS_CTRL1_MASK_VIN2_UVLO_POS ) & REG_CLKCTRL_SYS_CTRL1_MASK_VIN2_UVLO_MSK)
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#define REG_CLKCTRL_SEL_SWD_POS 0
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#define REG_CLKCTRL_SEL_SWD_MSK (0x1ul << REG_CLKCTRL_SEL_SWD_POS)
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#define REG_CLKCTRL_SEL_SWD_SET(num) (((num) << REG_CLKCTRL_SEL_SWD_POS ) & REG_CLKCTRL_SEL_SWD_MSK)
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#define REG_CLKCTRL_SEL_UART2_POS 1
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#define REG_CLKCTRL_SEL_UART2_MSK (0x1ul << REG_CLKCTRL_SEL_UART2_POS)
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#define REG_CLKCTRL_SEL_UART2_SET(num) (((num) << REG_CLKCTRL_SEL_UART2_POS ) & REG_CLKCTRL_SEL_UART2_MSK)
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#endif /*__CLKCTRL_DEFINE_H__*/
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