CPS/MXWK_美芯微科/common/reg_def/dma1_define.h

/*================================================================
* COPYRIGHT (C) 2016-2023 CPS LIMITED. ALL RIGHTS RESERVED.
*   
*   Filename: dma1_define.h
*   Author  : Zhenyu.Li <zhenyu.li@convenientpower.com>
*   Date    : 2023-02-13
*   Description: 
*
================================================================*/
#ifndef __DMA1_DEFINE_H__
#define __DMA1_DEFINE_H__
//-----------------------------------------------------------------------------
// dma1 registers definition                            
//-----------------------------------------------------------------------------
#pragma anon_unions

//-----------------------------------------------------------------------------
// registers structures
typedef struct
{
	uint32_t value:5;
	uint32_t reserved_31_5:27;
} REG_dma1_chl_enable_bitfiled_TypeDef;

typedef struct
{
	union {
	__IO	REG_dma1_chl_enable_bitfiled_TypeDef bf;//bitfiled
	__IO	uint32_t word;
	};
} REG_dma1_chl_enable_TypeDef;


typedef struct
{
	uint32_t value:7;
	uint32_t reserved_31_7:25;
} REG_dma1_ctrl_base_ptr_bitfiled_TypeDef;

typedef struct
{
	union {
	__IO	REG_dma1_ctrl_base_ptr_bitfiled_TypeDef bf;//bitfiled
	__IO	uint32_t word;
	};
} REG_dma1_ctrl_base_ptr_TypeDef;


typedef struct
{
	uint32_t value:5;
	uint32_t reserved_31_5:27;
} REG_dma1_dmadone_int_mask_bitfiled_TypeDef;

typedef struct
{
	union {
	__IO	REG_dma1_dmadone_int_mask_bitfiled_TypeDef bf;//bitfiled
	__IO	uint32_t word;
	};
} REG_dma1_dmadone_int_mask_TypeDef;


typedef struct
{
	uint32_t value:5;
	uint32_t reserved_31_5:27;
} REG_dma1_dmadone_int_bitfiled_TypeDef;

typedef struct
{
	union {
	__IO	REG_dma1_dmadone_int_bitfiled_TypeDef bf;//bitfiled
	__IO	uint32_t word;
	};
} REG_dma1_dmadone_int_TypeDef;


typedef struct
{
	uint32_t value:5;
	uint32_t reserved_31_5:27;
} REG_dma1_dma_done_clr_bitfiled_TypeDef;

typedef struct
{
	union {
	__IO	REG_dma1_dma_done_clr_bitfiled_TypeDef bf;//bitfiled
	__IO	uint32_t word;
	};
} REG_dma1_dma_done_clr_TypeDef;


//-----------------------------------------------------------------------------


//-----------------------------------------------------------------------------
// memory map
#define REG_DMA1_CHL_ENABLE_BASE                    0X40001800
#define REG_DMA1_CTRL_BASE_PTR_BASE                 0X40001804
#define REG_DMA1_DMADONE_INT_MASK_BASE              0X40001808
#define REG_DMA1_DMADONE_INT_BASE                   0X4000180C
#define REG_DMA1_DMA_DONE_CLR_BASE                  0X40001810
//-----------------------------------------------------------------------------


//-----------------------------------------------------------------------------
// declaration
#define REG_DMA1_CHL_ENABLE                     ((REG_dma1_chl_enable_TypeDef                *) REG_DMA1_CHL_ENABLE_BASE)
#define REG_DMA1_CTRL_BASE_PTR                  ((REG_dma1_ctrl_base_ptr_TypeDef             *) REG_DMA1_CTRL_BASE_PTR_BASE)
#define REG_DMA1_DMADONE_INT_MASK               ((REG_dma1_dmadone_int_mask_TypeDef          *) REG_DMA1_DMADONE_INT_MASK_BASE)
#define REG_DMA1_DMADONE_INT                    ((REG_dma1_dmadone_int_TypeDef               *) REG_DMA1_DMADONE_INT_BASE)
#define REG_DMA1_DMA_DONE_CLR                   ((REG_dma1_dma_done_clr_TypeDef              *) REG_DMA1_DMA_DONE_CLR_BASE)
//-----------------------------------------------------------------------------


//-----------------------------------------------------------------------------
// set
#define REG_DMA1_CHL_ENABLE__POS                              0
#define REG_DMA1_CHL_ENABLE__MSK                              (0x5ul           << REG_DMA1_CHL_ENABLE__POS)
#define REG_DMA1_CHL_ENABLE__SET(num)                         (((num)          << REG_DMA1_CHL_ENABLE__POS                ) & REG_DMA1_CHL_ENABLE__MSK)

#define REG_DMA1_CTRL_BASE_PTR__POS                           0
#define REG_DMA1_CTRL_BASE_PTR__MSK                           (0x7ul           << REG_DMA1_CTRL_BASE_PTR__POS)
#define REG_DMA1_CTRL_BASE_PTR__SET(num)                      (((num)          << REG_DMA1_CTRL_BASE_PTR__POS             ) & REG_DMA1_CTRL_BASE_PTR__MSK)

#define REG_DMA1_DMADONE_INT_MASK__POS                        0
#define REG_DMA1_DMADONE_INT_MASK__MSK                        (0x5ul           << REG_DMA1_DMADONE_INT_MASK__POS)
#define REG_DMA1_DMADONE_INT_MASK__SET(num)                   (((num)          << REG_DMA1_DMADONE_INT_MASK__POS          ) & REG_DMA1_DMADONE_INT_MASK__MSK)

#define REG_DMA1_DMA_DONE_CLR__POS                            0
#define REG_DMA1_DMA_DONE_CLR__MSK                            (0x5ul           << REG_DMA1_DMA_DONE_CLR__POS)
#define REG_DMA1_DMA_DONE_CLR__SET(num)                       (((num)          << REG_DMA1_DMA_DONE_CLR__POS              ) & REG_DMA1_DMA_DONE_CLR__MSK)

//-----------------------------------------------------------------------------


#endif /*__DMA1_DEFINE_H__*/