CPS/MXWK_美芯微科/common/reg_def/dma_define.h

#ifndef __DMA_DEFINE_H__
#define __DMA_DEFINE_H__
//-----------------------------------------------------------------------------
// dma registers definition                            
//-----------------------------------------------------------------------------
#pragma anon_unions

//-----------------------------------------------------------------------------
// registers structures
typedef struct
{
	uint32_t value:5;
	uint32_t reserved_31_5:27;
} REG_dma_chl_enable_bitfiled_TypeDef;

typedef struct
{
	union {
	__IO	REG_dma_chl_enable_bitfiled_TypeDef bf;//bitfiled
	__IO	uint32_t word;
	};
} REG_dma_chl_enable_TypeDef;


typedef struct
{
	uint32_t value:7;
	uint32_t reserved_31_7:25;
} REG_dma_ctrl_base_ptr_bitfiled_TypeDef;

typedef struct
{
	union {
	__IO	REG_dma_ctrl_base_ptr_bitfiled_TypeDef bf;//bitfiled
	__IO	uint32_t word;
	};
} REG_dma_ctrl_base_ptr_TypeDef;


typedef struct
{
	uint32_t value:5;
	uint32_t reserved_31_5:27;
} REG_dma_dmadone_int_mask_bitfiled_TypeDef;

typedef struct
{
	union {
	__IO	REG_dma_dmadone_int_mask_bitfiled_TypeDef bf;//bitfiled
	__IO	uint32_t word;
	};
} REG_dma_dmadone_int_mask_TypeDef;


typedef struct
{
	uint32_t value:5;
	uint32_t reserved_31_5:27;
} REG_dma_dmadone_int_bitfiled_TypeDef;

typedef struct
{
	union {
	__IO	REG_dma_dmadone_int_bitfiled_TypeDef bf;//bitfiled
	__IO	uint32_t word;
	};
} REG_dma_dmadone_int_TypeDef;


typedef struct
{
	uint32_t value:5;
	uint32_t reserved_31_5:27;
} REG_dma_dma_done_clr_bitfiled_TypeDef;

typedef struct
{
	union {
	__IO	REG_dma_dma_done_clr_bitfiled_TypeDef bf;//bitfiled
	__IO	uint32_t word;
	};
} REG_dma_dma_done_clr_TypeDef;


//-----------------------------------------------------------------------------


//-----------------------------------------------------------------------------
// memory map
#define REG_DMA_CHL_ENABLE_BASE                     0X40005000
#define REG_DMA_CTRL_BASE_PTR_BASE                  0X40005004
#define REG_DMA_DMADONE_INT_MASK_BASE               0X40005008
#define REG_DMA_DMADONE_INT_BASE                    0X4000500C
#define REG_DMA_DMA_DONE_CLR_BASE                   0X40005010
//-----------------------------------------------------------------------------


//-----------------------------------------------------------------------------
// declaration
#define REG_DMA_CHL_ENABLE                      ((REG_dma_chl_enable_TypeDef                 *) REG_DMA_CHL_ENABLE_BASE)
#define REG_DMA_CTRL_BASE_PTR                   ((REG_dma_ctrl_base_ptr_TypeDef              *) REG_DMA_CTRL_BASE_PTR_BASE)
#define REG_DMA_DMADONE_INT_MASK                ((REG_dma_dmadone_int_mask_TypeDef           *) REG_DMA_DMADONE_INT_MASK_BASE)
#define REG_DMA_DMADONE_INT                     ((REG_dma_dmadone_int_TypeDef                *) REG_DMA_DMADONE_INT_BASE)
#define REG_DMA_DMA_DONE_CLR                    ((REG_dma_dma_done_clr_TypeDef               *) REG_DMA_DMA_DONE_CLR_BASE)
//-----------------------------------------------------------------------------


//-----------------------------------------------------------------------------
// set
#define REG_DMA_CHL_ENABLE__POS                               0
#define REG_DMA_CHL_ENABLE__MSK                               (0x5ul           << REG_DMA_CHL_ENABLE__POS)
#define REG_DMA_CHL_ENABLE__SET(num)                          (((num)          << REG_DMA_CHL_ENABLE__POS                 ) & REG_DMA_CHL_ENABLE__MSK)

#define REG_DMA_CTRL_BASE_PTR__POS                            0
#define REG_DMA_CTRL_BASE_PTR__MSK                            (0x7ul           << REG_DMA_CTRL_BASE_PTR__POS)
#define REG_DMA_CTRL_BASE_PTR__SET(num)                       (((num)          << REG_DMA_CTRL_BASE_PTR__POS              ) & REG_DMA_CTRL_BASE_PTR__MSK)

#define REG_DMA_DMADONE_INT_MASK__POS                         0
#define REG_DMA_DMADONE_INT_MASK__MSK                         (0x5ul           << REG_DMA_DMADONE_INT_MASK__POS)
#define REG_DMA_DMADONE_INT_MASK__SET(num)                    (((num)          << REG_DMA_DMADONE_INT_MASK__POS           ) & REG_DMA_DMADONE_INT_MASK__MSK)

#define REG_DMA_DMA_DONE_CLR__POS                             0
#define REG_DMA_DMA_DONE_CLR__MSK                             (0x5ul           << REG_DMA_DMA_DONE_CLR__POS)
#define REG_DMA_DMA_DONE_CLR__SET(num)                        (((num)          << REG_DMA_DMA_DONE_CLR__POS               ) & REG_DMA_DMA_DONE_CLR__MSK)

//-----------------------------------------------------------------------------


#endif /*__DMA_DEFINE_H__*/