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CPS/MXWK_美芯微科/common/reg_def/mtp_define.h

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#ifndef __MTP_DEFINE_H__
#define __MTP_DEFINE_H__
//-----------------------------------------------------------------------------
// mtp registers definition
//-----------------------------------------------------------------------------
#pragma anon_unions
//-----------------------------------------------------------------------------
// registers structures
typedef struct
{
//0 : normal mode, mcu read through ahb
//1 : test mode, control otp use reg pin directly
uint32_t en:1;
uint32_t reserved_31_1:31;
} REG_mtp_test_mode_bitfiled_TypeDef;
typedef struct
{
union {
__IO REG_mtp_test_mode_bitfiled_TypeDef bf;//bitfiled
__IO uint32_t word;
};
} REG_mtp_test_mode_TypeDef;
typedef struct
{
//tap = 2+tap, step is 41ns,(min 50ns)
uint32_t tap:3;
//tpa,step is 1us,default：20+ tpa，(12 as worst osc fast60%)
uint32_t tpa:5;
uint32_t reserved_31_8:24;
} REG_mtp_deep_sleep_bitfiled_TypeDef;
typedef struct
{
union {
__IO REG_mtp_deep_sleep_bitfiled_TypeDef bf;//bitfiled
__IO uint32_t word;
};
} REG_mtp_deep_sleep_TypeDef;
typedef struct
{
//word address bus
uint32_t ad:12;
uint32_t reserved_15_12:4;
//memory block select:
//1'b0: select main block
//1'b1: select infromation block
uint32_t bks:1;
//read control signal, high active (min 20/50ns)
uint32_t re:1;
//program control signal, high active
uint32_t pg:1;
//sector erase(2k bits), high active,only address[12:6] is valid
uint32_t er:1;
//page erase(16k bits), high active,only address[12:9] is valid
uint32_t per:1;
//chip erase, high active, when activated, whole chip is eerased
uint32_t cer:1;
//pgh is used to control programming from 1st phase to 2nd phase, high active
uint32_t pgh:1;
//program and erase timing control, high active
uint32_t pep:1;
//pg_mode function is user to accelerate testing during cp &ft
//1'b0: 8 i/os will be programmed by 4time and vddh could vary within spec;
//1'b1: 32 i/os will be programmed by 1time and vddh is limited to >=5v;
uint32_t pg_mode:1;
//this signal is used for internal reference calibration. it shoule stay as low unless calibration is needed
uint32_t trf:1;
//power down analog circuits inside the memory macro,low active
uint32_t pdn:1;
//read mode description:
//1'b0: default
//1'b1: don't care duty cycle
//
uint32_t re_mode:1;
uint32_t reserved_31_28:4;
} REG_mtp_pin0_bitfiled_TypeDef;
typedef struct
{
union {
__IO REG_mtp_pin0_bitfiled_TypeDef bf;//bitfiled
__IO uint32_t word;
};
} REG_mtp_pin0_TypeDef;
typedef struct
{
//whole chip lock
//1'b0: whole chip is locked, and can‘t be program/erase
//1'b1:normal function
uint32_t lckn:1;
//sector lock
//1'b0:sector 127(ad[12:6]=(7f h) is locked and can not sector erase, page erase or chip erase. program and read still work as normal
//1'b1:normal function
uint32_t locksn:1;
//these are static signals which should be stabilized at least 100ns before memory is accessed, these signals control the pump voltages:
//2'b00: pump voltages 3% higher than nominal
//2'b01:pump voltages 6% higher than nominal
//2'b10: nominal pump voltages (default setting)
//2'b11:pump voltages 3% lower than nominal
uint32_t trim:2;
//control gate bias voltage during read
//1'b0:read mode bias 0v
//1'b1:read mode bias 1.2v(default)
uint32_t vrdcg_sel:1;
//these are static signals. value in this signals set the sensing current during read. iref is cell current on reference cell.
//2'b00: 2*iref/3
//2'b01 - 2*iref/4
//2'b10 - 2*iref/6(default)
//2'b11 - 2*iref/8
uint32_t marrd:2;
uint32_t reserved_12_7:6;
//enable ecc correct when read,high active
uint32_t eccon:1;
//these are static signals which should be stabilized at least 100ns before memory is accessed, these signals control the vbb pump voltages:
//2'b11 - pump voltages 3% lower than nominal
//2'b10 - nominal pump voltages (default setting)
// 2'b00 - pump voltages 3% higher than nominal
// 2'b01 - pump voltages 6% higher than nominal
uint32_t vbb_sel:2;
//mtp din parity byte for mtp test
uint32_t din_parity:8;
//mtp dout parity byte for mtp test
uint32_t dout_parity:8;
} REG_mtp_pin1_bitfiled_TypeDef;
typedef struct
{
union {
__IO REG_mtp_pin1_bitfiled_TypeDef bf;//bitfiled
__IO uint32_t word;
};
} REG_mtp_pin1_TypeDef;
typedef struct
{
//icell measurement enable,high active,it need work with pin trf:
//trf set high, measure cell current;
//trf set low, measure reference cell current
//1'b0: normal mode
//1'b1:allow icell measurement from "icell_q"pin
uint32_t icell:1;
//io selected in icell mode
uint32_t icell_ad:6;
//test mode option for sector erase. all memory block erase stress
//test mode select:
//stress_er=0, normal operation
//stress_er=1, memory block entry erase stress mode
uint32_t stress_er:1;
//control input and output of bandgap
//1'b0 build-in bandgap.(default)
//1'b1 external 1.2v reference voltage input from vbg pin.
uint32_t en_exbgr:1;
//control build-in bandgap testing
//1'b0 disable build-in bandgap voltage test .(default)
//1'b1 enable build-in bandgap voltage test.
uint32_t en_vbg_test:1;
uint32_t reserved_31_10:22;
} REG_mtp_pin2_bitfiled_TypeDef;
typedef struct
{
union {
__IO REG_mtp_pin2_bitfiled_TypeDef bf;//bitfiled
__IO uint32_t word;
};
} REG_mtp_pin2_TypeDef;
typedef struct
{
//mtp ip program data input
uint32_t value:32;
} REG_mtp_pin_pdin_bitfiled_TypeDef;
typedef struct
{
union {
__IO REG_mtp_pin_pdin_bitfiled_TypeDef bf;//bitfiled
__IO uint32_t word;
};
} REG_mtp_pin_pdin_TypeDef;
typedef struct
{
//mtp ip data output
uint32_t value:32;
} REG_mtp_pin_pdout_bitfiled_TypeDef;
typedef struct
{
union {
__IO REG_mtp_pin_pdout_bitfiled_TypeDef bf;//bitfiled
__IO uint32_t word;
};
} REG_mtp_pin_pdout_TypeDef;
typedef struct
{
//1 : disable swd read otp data area except the trim data area(higher 128byte)
uint32_t data:1;
uint32_t reserved_31_1:31;
} REG_mtp_read_disable_bitfiled_TypeDef;
typedef struct
{
union {
__IO REG_mtp_read_disable_bitfiled_TypeDef bf;//bitfiled
__IO uint32_t word;
};
} REG_mtp_read_disable_TypeDef;
typedef struct
{
//debug source select
uint32_t value:2;
uint32_t reserved_31_2:30;
} REG_mtp_debug_sel_bitfiled_TypeDef;
typedef struct
{
union {
__IO REG_mtp_debug_sel_bitfiled_TypeDef bf;//bitfiled
__IO uint32_t word;
};
} REG_mtp_debug_sel_TypeDef;
typedef struct
{
//mtp vddh control for analog
uint32_t value:1;
uint32_t reserved_31_1:31;
} REG_mtp_vddh_en_bitfiled_TypeDef;
typedef struct
{
union {
__IO REG_mtp_vddh_en_bitfiled_TypeDef bf;//bitfiled
__IO uint32_t word;
};
} REG_mtp_vddh_en_TypeDef;
typedef struct
{
//analog vddh ready flag
uint32_t value:1;
uint32_t reserved_31_1:31;
} REG_mtp_vddh_rdy_bitfiled_TypeDef;
typedef struct
{
union {
__IO REG_mtp_vddh_rdy_bitfiled_TypeDef bf;//bitfiled
__IO uint32_t word;
};
} REG_mtp_vddh_rdy_TypeDef;
typedef struct
{
//mtp deep stand by req flag
uint32_t value:1;
uint32_t reserved_31_1:31;
} REG_mtp_sleep_req_st_bitfiled_TypeDef;
typedef struct
{
union {
__IO REG_mtp_sleep_req_st_bitfiled_TypeDef bf;//bitfiled
__IO uint32_t word;
};
} REG_mtp_sleep_req_st_TypeDef;
typedef struct
{
//mtp mode control state for debug
uint32_t mtp_cst:3;
uint32_t reserved_31_3:29;
} REG_mtp_fsm_bitfiled_TypeDef;
typedef struct
{
union {
__IO REG_mtp_fsm_bitfiled_TypeDef bf;//bitfiled
__IO uint32_t word;
};
} REG_mtp_fsm_TypeDef;
typedef struct
{
//ecc active flag
uint32_t act_flag:1;
//ecc error flag
uint32_t err_flag:1;
uint32_t reserved_31_2:30;
} REG_mtp_ecc_bitfiled_TypeDef;
typedef struct
{
union {
__IO REG_mtp_ecc_bitfiled_TypeDef bf;//bitfiled
__IO uint32_t word;
};
} REG_mtp_ecc_TypeDef;
typedef struct
{
//write 16'h8e9f to 0x4001204c to enable this module password hit register
uint32_t pw_hit:1;
uint32_t reserved_31_1:31;
} REG_mtp_trim_bitfiled_TypeDef;
typedef struct
{
union {
__IO REG_mtp_trim_bitfiled_TypeDef bf;//bitfiled
__IO uint32_t word;
};
} REG_mtp_trim_TypeDef;
//-----------------------------------------------------------------------------
// memory map
#define REG_MTP_TEST_MODE_BASE 0x40012000
#define REG_MTP_DEEP_SLEEP_BASE 0x40012008
#define REG_MTP_PIN0_BASE 0x4001200C
#define REG_MTP_PIN1_BASE 0x40012010
#define REG_MTP_PIN2_BASE 0x40012014
#define REG_MTP_PIN_PDIN_BASE 0x40012018
#define REG_MTP_PIN_PDOUT_BASE 0x4001201C
#define REG_MTP_READ_DISABLE_BASE 0x40012020
#define REG_MTP_DEBUG_SEL_BASE 0x40012024
#define REG_MTP_VDDH_EN_BASE 0x40012028
#define REG_MTP_VDDH_RDY_BASE 0x4001202C
#define REG_MTP_SLEEP_REQ_ST_BASE 0x40012030
#define REG_MTP_FSM_BASE 0x40012034
#define REG_MTP_ECC_BASE 0x40012038
#define REG_MTP_TRIM_BASE 0x4001204C
//-----------------------------------------------------------------------------
// declaration
#define REG_MTP_TEST_MODE ((REG_mtp_test_mode_TypeDef *) REG_MTP_TEST_MODE_BASE )
#define REG_MTP_DEEP_SLEEP ((REG_mtp_deep_sleep_TypeDef *) REG_MTP_DEEP_SLEEP_BASE )
#define REG_MTP_PIN0 ((REG_mtp_pin0_TypeDef *) REG_MTP_PIN0_BASE )
#define REG_MTP_PIN1 ((REG_mtp_pin1_TypeDef *) REG_MTP_PIN1_BASE )
#define REG_MTP_PIN2 ((REG_mtp_pin2_TypeDef *) REG_MTP_PIN2_BASE )
#define REG_MTP_PIN_PDIN ((REG_mtp_pin_pdin_TypeDef *) REG_MTP_PIN_PDIN_BASE )
#define REG_MTP_PIN_PDOUT ((REG_mtp_pin_pdout_TypeDef *) REG_MTP_PIN_PDOUT_BASE )
#define REG_MTP_READ_DISABLE ((REG_mtp_read_disable_TypeDef *) REG_MTP_READ_DISABLE_BASE )
#define REG_MTP_DEBUG_SEL ((REG_mtp_debug_sel_TypeDef *) REG_MTP_DEBUG_SEL_BASE )
#define REG_MTP_VDDH_EN ((REG_mtp_vddh_en_TypeDef *) REG_MTP_VDDH_EN_BASE )
#define REG_MTP_VDDH_RDY ((REG_mtp_vddh_rdy_TypeDef *) REG_MTP_VDDH_RDY_BASE )
#define REG_MTP_SLEEP_REQ_ST ((REG_mtp_sleep_req_st_TypeDef *) REG_MTP_SLEEP_REQ_ST_BASE )
#define REG_MTP_FSM ((REG_mtp_fsm_TypeDef *) REG_MTP_FSM_BASE )
#define REG_MTP_ECC ((REG_mtp_ecc_TypeDef *) REG_MTP_ECC_BASE )
#define REG_MTP_TRIM ((REG_mtp_trim_TypeDef *) REG_MTP_TRIM_BASE )
//-----------------------------------------------------------------------------
// set
#define REG_MTP_TEST_MODE_EN_POS 0
#define REG_MTP_TEST_MODE_EN_MSK (0x1ul << REG_MTP_TEST_MODE_EN_POS)
#define REG_MTP_TEST_MODE_EN_SET(num) (((num) << REG_MTP_TEST_MODE_EN_POS ) & REG_MTP_TEST_MODE_EN_MSK)
#define REG_MTP_DEEP_SLEEP_TAP_POS 0
#define REG_MTP_DEEP_SLEEP_TAP_MSK (0x7ul << REG_MTP_DEEP_SLEEP_TAP_POS)
#define REG_MTP_DEEP_SLEEP_TAP_SET(num) (((num) << REG_MTP_DEEP_SLEEP_TAP_POS ) & REG_MTP_DEEP_SLEEP_TAP_MSK)
#define REG_MTP_DEEP_SLEEP_TPA_POS 3
#define REG_MTP_DEEP_SLEEP_TPA_MSK (0x1Ful << REG_MTP_DEEP_SLEEP_TPA_POS)
#define REG_MTP_DEEP_SLEEP_TPA_SET(num) (((num) << REG_MTP_DEEP_SLEEP_TPA_POS ) & REG_MTP_DEEP_SLEEP_TPA_MSK)
#define REG_MTP_PIN0_AD_POS 0
#define REG_MTP_PIN0_AD_MSK (0xFFFul << REG_MTP_PIN0_AD_POS)
#define REG_MTP_PIN0_AD_SET(num) (((num) << REG_MTP_PIN0_AD_POS ) & REG_MTP_PIN0_AD_MSK)
#define REG_MTP_PIN0_BKS_POS 16
#define REG_MTP_PIN0_BKS_MSK (0x1ul << REG_MTP_PIN0_BKS_POS)
#define REG_MTP_PIN0_BKS_SET(num) (((num) << REG_MTP_PIN0_BKS_POS ) & REG_MTP_PIN0_BKS_MSK)
#define REG_MTP_PIN0_RE_POS 17
#define REG_MTP_PIN0_RE_MSK (0x1ul << REG_MTP_PIN0_RE_POS)
#define REG_MTP_PIN0_RE_SET(num) (((num) << REG_MTP_PIN0_RE_POS ) & REG_MTP_PIN0_RE_MSK)
#define REG_MTP_PIN0_PG_POS 18
#define REG_MTP_PIN0_PG_MSK (0x1ul << REG_MTP_PIN0_PG_POS)
#define REG_MTP_PIN0_PG_SET(num) (((num) << REG_MTP_PIN0_PG_POS ) & REG_MTP_PIN0_PG_MSK)
#define REG_MTP_PIN0_ER_POS 19
#define REG_MTP_PIN0_ER_MSK (0x1ul << REG_MTP_PIN0_ER_POS)
#define REG_MTP_PIN0_ER_SET(num) (((num) << REG_MTP_PIN0_ER_POS ) & REG_MTP_PIN0_ER_MSK)
#define REG_MTP_PIN0_PER_POS 20
#define REG_MTP_PIN0_PER_MSK (0x1ul << REG_MTP_PIN0_PER_POS)
#define REG_MTP_PIN0_PER_SET(num) (((num) << REG_MTP_PIN0_PER_POS ) & REG_MTP_PIN0_PER_MSK)
#define REG_MTP_PIN0_CER_POS 21
#define REG_MTP_PIN0_CER_MSK (0x1ul << REG_MTP_PIN0_CER_POS)
#define REG_MTP_PIN0_CER_SET(num) (((num) << REG_MTP_PIN0_CER_POS ) & REG_MTP_PIN0_CER_MSK)
#define REG_MTP_PIN0_PGH_POS 22
#define REG_MTP_PIN0_PGH_MSK (0x1ul << REG_MTP_PIN0_PGH_POS)
#define REG_MTP_PIN0_PGH_SET(num) (((num) << REG_MTP_PIN0_PGH_POS ) & REG_MTP_PIN0_PGH_MSK)
#define REG_MTP_PIN0_PEP_POS 23
#define REG_MTP_PIN0_PEP_MSK (0x1ul << REG_MTP_PIN0_PEP_POS)
#define REG_MTP_PIN0_PEP_SET(num) (((num) << REG_MTP_PIN0_PEP_POS ) & REG_MTP_PIN0_PEP_MSK)
#define REG_MTP_PIN0_PG_MODE_POS 24
#define REG_MTP_PIN0_PG_MODE_MSK (0x1ul << REG_MTP_PIN0_PG_MODE_POS)
#define REG_MTP_PIN0_PG_MODE_SET(num) (((num) << REG_MTP_PIN0_PG_MODE_POS ) & REG_MTP_PIN0_PG_MODE_MSK)
#define REG_MTP_PIN0_TRF_POS 25
#define REG_MTP_PIN0_TRF_MSK (0x1ul << REG_MTP_PIN0_TRF_POS)
#define REG_MTP_PIN0_TRF_SET(num) (((num) << REG_MTP_PIN0_TRF_POS ) & REG_MTP_PIN0_TRF_MSK)
#define REG_MTP_PIN0_PDN_POS 26
#define REG_MTP_PIN0_PDN_MSK (0x1ul << REG_MTP_PIN0_PDN_POS)
#define REG_MTP_PIN0_PDN_SET(num) (((num) << REG_MTP_PIN0_PDN_POS ) & REG_MTP_PIN0_PDN_MSK)
#define REG_MTP_PIN0_RE_MODE_POS 27
#define REG_MTP_PIN0_RE_MODE_MSK (0x1ul << REG_MTP_PIN0_RE_MODE_POS)
#define REG_MTP_PIN0_RE_MODE_SET(num) (((num) << REG_MTP_PIN0_RE_MODE_POS ) & REG_MTP_PIN0_RE_MODE_MSK)
#define REG_MTP_PIN1_LCKN_POS 0
#define REG_MTP_PIN1_LCKN_MSK (0x1ul << REG_MTP_PIN1_LCKN_POS)
#define REG_MTP_PIN1_LCKN_SET(num) (((num) << REG_MTP_PIN1_LCKN_POS ) & REG_MTP_PIN1_LCKN_MSK)
#define REG_MTP_PIN1_LOCKSN_POS 1
#define REG_MTP_PIN1_LOCKSN_MSK (0x1ul << REG_MTP_PIN1_LOCKSN_POS)
#define REG_MTP_PIN1_LOCKSN_SET(num) (((num) << REG_MTP_PIN1_LOCKSN_POS ) & REG_MTP_PIN1_LOCKSN_MSK)
#define REG_MTP_PIN1_TRIM_POS 2
#define REG_MTP_PIN1_TRIM_MSK (0x3ul << REG_MTP_PIN1_TRIM_POS)
#define REG_MTP_PIN1_TRIM_SET(num) (((num) << REG_MTP_PIN1_TRIM_POS ) & REG_MTP_PIN1_TRIM_MSK)
#define REG_MTP_PIN1_VRDCG_SEL_POS 4
#define REG_MTP_PIN1_VRDCG_SEL_MSK (0x1ul << REG_MTP_PIN1_VRDCG_SEL_POS)
#define REG_MTP_PIN1_VRDCG_SEL_SET(num) (((num) << REG_MTP_PIN1_VRDCG_SEL_POS ) & REG_MTP_PIN1_VRDCG_SEL_MSK)
#define REG_MTP_PIN1_MARRD_POS 5
#define REG_MTP_PIN1_MARRD_MSK (0x3ul << REG_MTP_PIN1_MARRD_POS)
#define REG_MTP_PIN1_MARRD_SET(num) (((num) << REG_MTP_PIN1_MARRD_POS ) & REG_MTP_PIN1_MARRD_MSK)
#define REG_MTP_PIN1_ECCON_POS 13
#define REG_MTP_PIN1_ECCON_MSK (0x1ul << REG_MTP_PIN1_ECCON_POS)
#define REG_MTP_PIN1_ECCON_SET(num) (((num) << REG_MTP_PIN1_ECCON_POS ) & REG_MTP_PIN1_ECCON_MSK)
#define REG_MTP_PIN1_VBB_SEL_POS 14
#define REG_MTP_PIN1_VBB_SEL_MSK (0x3ul << REG_MTP_PIN1_VBB_SEL_POS)
#define REG_MTP_PIN1_VBB_SEL_SET(num) (((num) << REG_MTP_PIN1_VBB_SEL_POS ) & REG_MTP_PIN1_VBB_SEL_MSK)
#define REG_MTP_PIN1_DIN_PARITY_POS 16
#define REG_MTP_PIN1_DIN_PARITY_MSK (0xFFul << REG_MTP_PIN1_DIN_PARITY_POS)
#define REG_MTP_PIN1_DIN_PARITY_SET(num) (((num) << REG_MTP_PIN1_DIN_PARITY_POS ) & REG_MTP_PIN1_DIN_PARITY_MSK)
#define REG_MTP_PIN2_ICELL_POS 0
#define REG_MTP_PIN2_ICELL_MSK (0x1ul << REG_MTP_PIN2_ICELL_POS)
#define REG_MTP_PIN2_ICELL_SET(num) (((num) << REG_MTP_PIN2_ICELL_POS ) & REG_MTP_PIN2_ICELL_MSK)
#define REG_MTP_PIN2_ICELL_AD_POS 1
#define REG_MTP_PIN2_ICELL_AD_MSK (0x3Ful << REG_MTP_PIN2_ICELL_AD_POS)
#define REG_MTP_PIN2_ICELL_AD_SET(num) (((num) << REG_MTP_PIN2_ICELL_AD_POS ) & REG_MTP_PIN2_ICELL_AD_MSK)
#define REG_MTP_PIN2_STRESS_ER_POS 7
#define REG_MTP_PIN2_STRESS_ER_MSK (0x1ul << REG_MTP_PIN2_STRESS_ER_POS)
#define REG_MTP_PIN2_STRESS_ER_SET(num) (((num) << REG_MTP_PIN2_STRESS_ER_POS ) & REG_MTP_PIN2_STRESS_ER_MSK)
#define REG_MTP_PIN2_EN_EXBGR_POS 8
#define REG_MTP_PIN2_EN_EXBGR_MSK (0x1ul << REG_MTP_PIN2_EN_EXBGR_POS)
#define REG_MTP_PIN2_EN_EXBGR_SET(num) (((num) << REG_MTP_PIN2_EN_EXBGR_POS ) & REG_MTP_PIN2_EN_EXBGR_MSK)
#define REG_MTP_PIN2_EN_VBG_TEST_POS 9
#define REG_MTP_PIN2_EN_VBG_TEST_MSK (0x1ul << REG_MTP_PIN2_EN_VBG_TEST_POS)
#define REG_MTP_PIN2_EN_VBG_TEST_SET(num) (((num) << REG_MTP_PIN2_EN_VBG_TEST_POS ) & REG_MTP_PIN2_EN_VBG_TEST_MSK)
#define REG_MTP_PIN_PDIN_POS 0
#define REG_MTP_PIN_PDIN_MSK (0xFFFFFFFFul << REG_MTP_PIN_PDIN_POS)
#define REG_MTP_PIN_PDIN_SET(num) (((num) << REG_MTP_PIN_PDIN_POS ) & REG_MTP_PIN_PDIN_MSK)
#define REG_MTP_READ_DISABLE_DATA_POS 0
#define REG_MTP_READ_DISABLE_DATA_MSK (0x1ul << REG_MTP_READ_DISABLE_DATA_POS)
#define REG_MTP_READ_DISABLE_DATA_SET(num) (((num) << REG_MTP_READ_DISABLE_DATA_POS ) & REG_MTP_READ_DISABLE_DATA_MSK)
#define REG_MTP_DEBUG_SEL_POS 0
#define REG_MTP_DEBUG_SEL_MSK (0x3ul << REG_MTP_DEBUG_SEL_POS)
#define REG_MTP_DEBUG_SEL_SET(num) (((num) << REG_MTP_DEBUG_SEL_POS ) & REG_MTP_DEBUG_SEL_MSK)
#define REG_MTP_VDDH_EN_POS 0
#define REG_MTP_VDDH_EN_MSK (0x1ul << REG_MTP_VDDH_EN_POS)
#define REG_MTP_VDDH_EN_SET(num) (((num) << REG_MTP_VDDH_EN_POS ) & REG_MTP_VDDH_EN_MSK)
#endif /*__MTP_DEFINE_H__*/