CPS/MXWK_美芯微科/common/reg_def/pd0_define.h

#ifndef __PD0_DEFINE_H__
#define __PD0_DEFINE_H__
//-----------------------------------------------------------------------------
// pd0 registers definition                            
//-----------------------------------------------------------------------------
#pragma anon_unions

//-----------------------------------------------------------------------------
// registers structures
typedef struct
{
	uint32_t meas_cc1:1;
	uint32_t meas_cc2:1;
	uint32_t vconn_cc1:1;
	uint32_t vconn_cc2:1;
	uint32_t pu_en1:1;
	uint32_t pu_en2:1;
	uint32_t reserved_7_6:2;
	uint32_t comp_en_cc1:1;
	uint32_t comp_en_cc2:1;
	uint32_t reserved_31_10:22;
} REG_pd0_sw1_bitfiled_TypeDef;

typedef struct
{
	union {
	__IO	REG_pd0_sw1_bitfiled_TypeDef bf;//bitfiled
	__IO	uint32_t word;
	};
} REG_pd0_sw1_TypeDef;


typedef struct
{
	uint32_t txcc1:1;
	uint32_t txcc2:1;
	uint32_t auto_crc:1;
	uint32_t reserved_3_3:1;
	uint32_t datarole:1;
	uint32_t specrev:2;
	uint32_t powerrole:1;
	uint32_t reserved_31_8:24;
} REG_pd0_sw2_bitfiled_TypeDef;

typedef struct
{
	union {
	__IO	REG_pd0_sw2_bitfiled_TypeDef bf;//bitfiled
	__IO	uint32_t word;
	};
} REG_pd0_sw2_TypeDef;


typedef struct
{
	uint32_t tx:8;
	uint32_t rx:8;
	uint32_t reserved_31_16:16;
} REG_pd0_data_bitfiled_TypeDef;

typedef struct
{
	union {
	__IO	REG_pd0_data_bitfiled_TypeDef bf;//bitfiled
	__IO	uint32_t word;
	};
} REG_pd0_data_TypeDef;


typedef struct
{
	uint32_t tx_start:1;
	uint32_t tx_sop:3;
	uint32_t n_retries:2;
	uint32_t host_cur:2;
	uint32_t en_sop:1;
	uint32_t en_sop1:1;
	uint32_t en_sop2:1;
	uint32_t en_sop1db:1;
	uint32_t en_sop2db:1;
	uint32_t reserved_15_13:3;
	uint32_t en_sop_auto_crc:1;
	uint32_t en_sop1_auto_crc:1;
	uint32_t en_sop2_auto_crc:1;
	uint32_t en_sop1_db_auto_crc:1;
	uint32_t en_sop2_db_auto_crc:1;
	uint32_t reserved_23_21:3;
	uint32_t bist_mode2:1;
	uint32_t send_softrst:1;
	uint32_t send_hardrst:1;
	uint32_t auto_retry:1;
	uint32_t bist_always_on:1;
	uint32_t wake_en:1;
	uint32_t reserved_31_30:2;
} REG_pd0_ctrl_bitfiled_TypeDef;

typedef struct
{
	union {
	__IO	REG_pd0_ctrl_bitfiled_TypeDef bf;//bitfiled
	__IO	uint32_t word;
	};
} REG_pd0_ctrl_TypeDef;


typedef struct
{
	uint32_t cc_comp_en:1;
	uint32_t reserved_31_1:31;
} REG_pd0_power_bitfiled_TypeDef;

typedef struct
{
	union {
	__IO	REG_pd0_power_bitfiled_TypeDef bf;//bitfiled
	__IO	uint32_t word;
	};
} REG_pd0_power_TypeDef;


typedef struct
{
	uint32_t sw_reset:1;
	uint32_t pd_reset:1;
	uint32_t reserved_31_2:30;
} REG_pd0_reset_bitfiled_TypeDef;

typedef struct
{
	union {
	__IO	REG_pd0_reset_bitfiled_TypeDef bf;//bitfiled
	__IO	uint32_t word;
	};
} REG_pd0_reset_TypeDef;


typedef struct
{
	uint32_t hardrst:1;
	uint32_t softrst:1;
	uint32_t rertyfail:1;
	uint32_t rx_sop:1;
	uint32_t rx_sop1:1;
	uint32_t rx_sop2:1;
	uint32_t rx_sop1_db:1;
	uint32_t rx_sop2_db:1;
	uint32_t cc1:2;
	uint32_t cc2:2;
	uint32_t reserved_14_12:3;
	uint32_t crc_chk:1;
	uint32_t reserved_16_16:1;
	uint32_t activity:1;
	uint32_t reserved_29_18:12;
	uint32_t enddrviebmc_overtime:1;
	uint32_t reserved_31_31:1;
} REG_pd0_status_bitfiled_TypeDef;

typedef struct
{
	union {
	__IO	REG_pd0_status_bitfiled_TypeDef bf;//bitfiled
	__IO	uint32_t word;
	};
} REG_pd0_status_TypeDef;


typedef struct
{
	uint32_t value:14;
	uint32_t reserved_31_14:18;
} REG_pd0_int_mask_bitfiled_TypeDef;

typedef struct
{
	union {
	__IO	REG_pd0_int_mask_bitfiled_TypeDef bf;//bitfiled
	__IO	uint32_t word;
	};
} REG_pd0_int_mask_TypeDef;


typedef struct
{
	uint32_t value:14;
	uint32_t reserved_31_14:18;
} REG_pd0_int_flag_bitfiled_TypeDef;

typedef struct
{
	union {
	__IO	REG_pd0_int_flag_bitfiled_TypeDef bf;//bitfiled
	__IO	uint32_t word;
	};
} REG_pd0_int_flag_TypeDef;


typedef struct
{
	uint32_t reserved_0_0:1;
	//1=rx fifo wr ptr rollback if crc error (default), 0=disable
	uint32_t en_rx_rollback:1;
	//1=check msg_id only when goodcrc feedback(default)   0:check msg_id+sop*
	uint32_t dis_fullcheck:1;
	//00=rxd_activity  or txd_activity   01=rxd_activity   1x= txd_activity
	uint32_t activity_mode:2;
	uint32_t reserved_5_5:1;
	//1=force_txen
	uint32_t force_txen:1;
	//1=force_rxen
	uint32_t force_rxen:1;
	uint32_t reserved_11_8:4;
	//for dig_testsel
	uint32_t dig_testsel:4;
	uint32_t reserved_18_16:3;
	//reply goodcrc timer  0=80us   1=110us
	uint32_t transmit_timer:1;
	//wait time(us) for reply goodcrc
	uint32_t gap_gcf:12;
} REG_pd0_cfg_bitfiled_TypeDef;

typedef struct
{
	union {
	__IO	REG_pd0_cfg_bitfiled_TypeDef bf;//bitfiled
	__IO	uint32_t word;
	};
} REG_pd0_cfg_TypeDef;


typedef struct
{
	uint32_t host_inf_gcf_cs:4;
	uint32_t host_inf_hdr_cs:4;
	uint32_t host_inf_txs_cs:2;
	uint32_t prltx_cur_state:5;
	uint32_t reserved_15_15:1;
	uint32_t tx_cs:6;
	uint32_t reserved_23_22:2;
	uint32_t rx_cs:6;
	uint32_t reserved_31_30:2;
} REG_pd0_fsm_mac_bitfiled_TypeDef;

typedef struct
{
	union {
	__IO	REG_pd0_fsm_mac_bitfiled_TypeDef bf;//bitfiled
	__IO	uint32_t word;
	};
} REG_pd0_fsm_mac_TypeDef;


typedef struct
{
	uint32_t state_tx_bist:4;
	uint32_t state_tx_phy:3;
	uint32_t reserved_31_7:25;
} REG_pd0_fsm_phy_bitfiled_TypeDef;

typedef struct
{
	union {
	__IO	REG_pd0_fsm_phy_bitfiled_TypeDef bf;//bitfiled
	__IO	uint32_t word;
	};
} REG_pd0_fsm_phy_TypeDef;


//-----------------------------------------------------------------------------


//-----------------------------------------------------------------------------
// memory map
#define REG_PD0_SW1_BASE                            0X4000D000
#define REG_PD0_SW2_BASE                            0X4000D004
#define REG_PD0_DATA_BASE                           0X4000D010
#define REG_PD0_CTRL_BASE                           0X4000D014
#define REG_PD0_POWER_BASE                          0X4000D01C
#define REG_PD0_RESET_BASE                          0X4000D020
#define REG_PD0_STATUS_BASE                         0X4000D024
#define REG_PD0_INT_MASK_BASE                       0X4000D028
#define REG_PD0_INT_FLAG_BASE                       0X4000D02C
#define REG_PD0_CFG_BASE                            0X4000D030
#define REG_PD0_FSM_MAC_BASE                        0X4000D034
#define REG_PD0_FSM_PHY_BASE                        0X4000D038
//-----------------------------------------------------------------------------


//-----------------------------------------------------------------------------
// declaration
#define REG_PD0_SW1                             ((REG_pd0_sw1_TypeDef                        *) REG_PD0_SW1_BASE)
#define REG_PD0_SW2                             ((REG_pd0_sw2_TypeDef                        *) REG_PD0_SW2_BASE)
#define REG_PD0_DATA                            ((REG_pd0_data_TypeDef                       *) REG_PD0_DATA_BASE)
#define REG_PD0_CTRL                            ((REG_pd0_ctrl_TypeDef                       *) REG_PD0_CTRL_BASE)
#define REG_PD0_POWER                           ((REG_pd0_power_TypeDef                      *) REG_PD0_POWER_BASE)
#define REG_PD0_RESET                           ((REG_pd0_reset_TypeDef                      *) REG_PD0_RESET_BASE)
#define REG_PD0_STATUS                          ((REG_pd0_status_TypeDef                     *) REG_PD0_STATUS_BASE)
#define REG_PD0_INT_MASK                        ((REG_pd0_int_mask_TypeDef                   *) REG_PD0_INT_MASK_BASE)
#define REG_PD0_INT_FLAG                        ((REG_pd0_int_flag_TypeDef                   *) REG_PD0_INT_FLAG_BASE)
#define REG_PD0_CFG                             ((REG_pd0_cfg_TypeDef                        *) REG_PD0_CFG_BASE)
#define REG_PD0_FSM_MAC                         ((REG_pd0_fsm_mac_TypeDef                    *) REG_PD0_FSM_MAC_BASE)
#define REG_PD0_FSM_PHY                         ((REG_pd0_fsm_phy_TypeDef                    *) REG_PD0_FSM_PHY_BASE)
//-----------------------------------------------------------------------------


//-----------------------------------------------------------------------------
// set
#define REG_PD0_SW1_MEAS_CC1_POS                              0
#define REG_PD0_SW1_MEAS_CC1_MSK                              (0x1ul           << REG_PD0_SW1_MEAS_CC1_POS)
#define REG_PD0_SW1_MEAS_CC1_SET(num)                         (((num)          << REG_PD0_SW1_MEAS_CC1_POS                ) & REG_PD0_SW1_MEAS_CC1_MSK)

#define REG_PD0_SW1_MEAS_CC2_POS                              1
#define REG_PD0_SW1_MEAS_CC2_MSK                              (0x1ul           << REG_PD0_SW1_MEAS_CC2_POS)
#define REG_PD0_SW1_MEAS_CC2_SET(num)                         (((num)          << REG_PD0_SW1_MEAS_CC2_POS                ) & REG_PD0_SW1_MEAS_CC2_MSK)

#define REG_PD0_SW1_VCONN_CC1_POS                             2
#define REG_PD0_SW1_VCONN_CC1_MSK                             (0x1ul           << REG_PD0_SW1_VCONN_CC1_POS)
#define REG_PD0_SW1_VCONN_CC1_SET(num)                        (((num)          << REG_PD0_SW1_VCONN_CC1_POS               ) & REG_PD0_SW1_VCONN_CC1_MSK)

#define REG_PD0_SW1_VCONN_CC2_POS                             3
#define REG_PD0_SW1_VCONN_CC2_MSK                             (0x1ul           << REG_PD0_SW1_VCONN_CC2_POS)
#define REG_PD0_SW1_VCONN_CC2_SET(num)                        (((num)          << REG_PD0_SW1_VCONN_CC2_POS               ) & REG_PD0_SW1_VCONN_CC2_MSK)

#define REG_PD0_SW1_PU_EN1_POS                                4
#define REG_PD0_SW1_PU_EN1_MSK                                (0x1ul           << REG_PD0_SW1_PU_EN1_POS)
#define REG_PD0_SW1_PU_EN1_SET(num)                           (((num)          << REG_PD0_SW1_PU_EN1_POS                  ) & REG_PD0_SW1_PU_EN1_MSK)

#define REG_PD0_SW1_PU_EN2_POS                                5
#define REG_PD0_SW1_PU_EN2_MSK                                (0x1ul           << REG_PD0_SW1_PU_EN2_POS)
#define REG_PD0_SW1_PU_EN2_SET(num)                           (((num)          << REG_PD0_SW1_PU_EN2_POS                  ) & REG_PD0_SW1_PU_EN2_MSK)

#define REG_PD0_SW1_COMP_EN_CC1_POS                           8
#define REG_PD0_SW1_COMP_EN_CC1_MSK                           (0x1ul           << REG_PD0_SW1_COMP_EN_CC1_POS)
#define REG_PD0_SW1_COMP_EN_CC1_SET(num)                      (((num)          << REG_PD0_SW1_COMP_EN_CC1_POS             ) & REG_PD0_SW1_COMP_EN_CC1_MSK)

#define REG_PD0_SW1_COMP_EN_CC2_POS                           9
#define REG_PD0_SW1_COMP_EN_CC2_MSK                           (0x1ul           << REG_PD0_SW1_COMP_EN_CC2_POS)
#define REG_PD0_SW1_COMP_EN_CC2_SET(num)                      (((num)          << REG_PD0_SW1_COMP_EN_CC2_POS             ) & REG_PD0_SW1_COMP_EN_CC2_MSK)

#define REG_PD0_SW2_TXCC1_POS                                 0
#define REG_PD0_SW2_TXCC1_MSK                                 (0x1ul           << REG_PD0_SW2_TXCC1_POS)
#define REG_PD0_SW2_TXCC1_SET(num)                            (((num)          << REG_PD0_SW2_TXCC1_POS                   ) & REG_PD0_SW2_TXCC1_MSK)

#define REG_PD0_SW2_TXCC2_POS                                 1
#define REG_PD0_SW2_TXCC2_MSK                                 (0x1ul           << REG_PD0_SW2_TXCC2_POS)
#define REG_PD0_SW2_TXCC2_SET(num)                            (((num)          << REG_PD0_SW2_TXCC2_POS                   ) & REG_PD0_SW2_TXCC2_MSK)

#define REG_PD0_SW2_AUTO_CRC_POS                              2
#define REG_PD0_SW2_AUTO_CRC_MSK                              (0x1ul           << REG_PD0_SW2_AUTO_CRC_POS)
#define REG_PD0_SW2_AUTO_CRC_SET(num)                         (((num)          << REG_PD0_SW2_AUTO_CRC_POS                ) & REG_PD0_SW2_AUTO_CRC_MSK)

#define REG_PD0_SW2_DATAROLE_POS                              4
#define REG_PD0_SW2_DATAROLE_MSK                              (0x1ul           << REG_PD0_SW2_DATAROLE_POS)
#define REG_PD0_SW2_DATAROLE_SET(num)                         (((num)          << REG_PD0_SW2_DATAROLE_POS                ) & REG_PD0_SW2_DATAROLE_MSK)

#define REG_PD0_SW2_SPECREV_POS                               5
#define REG_PD0_SW2_SPECREV_MSK                               (0x2ul           << REG_PD0_SW2_SPECREV_POS)
#define REG_PD0_SW2_SPECREV_SET(num)                          (((num)          << REG_PD0_SW2_SPECREV_POS                 ) & REG_PD0_SW2_SPECREV_MSK)

#define REG_PD0_SW2_POWERROLE_POS                             7
#define REG_PD0_SW2_POWERROLE_MSK                             (0x1ul           << REG_PD0_SW2_POWERROLE_POS)
#define REG_PD0_SW2_POWERROLE_SET(num)                        (((num)          << REG_PD0_SW2_POWERROLE_POS               ) & REG_PD0_SW2_POWERROLE_MSK)

#define REG_PD0_DATA_TX_POS                                   0
#define REG_PD0_DATA_TX_MSK                                   (0x8ul           << REG_PD0_DATA_TX_POS)
#define REG_PD0_DATA_TX_SET(num)                              (((num)          << REG_PD0_DATA_TX_POS                     ) & REG_PD0_DATA_TX_MSK)

#define REG_PD0_CTRL_TX_START_POS                             0
#define REG_PD0_CTRL_TX_START_MSK                             (0x1ul           << REG_PD0_CTRL_TX_START_POS)
#define REG_PD0_CTRL_TX_START_SET(num)                        (((num)          << REG_PD0_CTRL_TX_START_POS               ) & REG_PD0_CTRL_TX_START_MSK)

#define REG_PD0_CTRL_TX_SOP_POS                               1
#define REG_PD0_CTRL_TX_SOP_MSK                               (0x3ul           << REG_PD0_CTRL_TX_SOP_POS)
#define REG_PD0_CTRL_TX_SOP_SET(num)                          (((num)          << REG_PD0_CTRL_TX_SOP_POS                 ) & REG_PD0_CTRL_TX_SOP_MSK)

#define REG_PD0_CTRL_N_RETRIES_POS                            4
#define REG_PD0_CTRL_N_RETRIES_MSK                            (0x2ul           << REG_PD0_CTRL_N_RETRIES_POS)
#define REG_PD0_CTRL_N_RETRIES_SET(num)                       (((num)          << REG_PD0_CTRL_N_RETRIES_POS              ) & REG_PD0_CTRL_N_RETRIES_MSK)

#define REG_PD0_CTRL_HOST_CUR_POS                             6
#define REG_PD0_CTRL_HOST_CUR_MSK                             (0x2ul           << REG_PD0_CTRL_HOST_CUR_POS)
#define REG_PD0_CTRL_HOST_CUR_SET(num)                        (((num)          << REG_PD0_CTRL_HOST_CUR_POS               ) & REG_PD0_CTRL_HOST_CUR_MSK)

#define REG_PD0_CTRL_EN_SOP_POS                               8
#define REG_PD0_CTRL_EN_SOP_MSK                               (0x1ul           << REG_PD0_CTRL_EN_SOP_POS)
#define REG_PD0_CTRL_EN_SOP_SET(num)                          (((num)          << REG_PD0_CTRL_EN_SOP_POS                 ) & REG_PD0_CTRL_EN_SOP_MSK)

#define REG_PD0_CTRL_EN_SOP1_POS                              9
#define REG_PD0_CTRL_EN_SOP1_MSK                              (0x1ul           << REG_PD0_CTRL_EN_SOP1_POS)
#define REG_PD0_CTRL_EN_SOP1_SET(num)                         (((num)          << REG_PD0_CTRL_EN_SOP1_POS                ) & REG_PD0_CTRL_EN_SOP1_MSK)

#define REG_PD0_CTRL_EN_SOP2_POS                              10
#define REG_PD0_CTRL_EN_SOP2_MSK                              (0x1ul           << REG_PD0_CTRL_EN_SOP2_POS)
#define REG_PD0_CTRL_EN_SOP2_SET(num)                         (((num)          << REG_PD0_CTRL_EN_SOP2_POS                ) & REG_PD0_CTRL_EN_SOP2_MSK)

#define REG_PD0_CTRL_EN_SOP1DB_POS                            11
#define REG_PD0_CTRL_EN_SOP1DB_MSK                            (0x1ul           << REG_PD0_CTRL_EN_SOP1DB_POS)
#define REG_PD0_CTRL_EN_SOP1DB_SET(num)                       (((num)          << REG_PD0_CTRL_EN_SOP1DB_POS              ) & REG_PD0_CTRL_EN_SOP1DB_MSK)

#define REG_PD0_CTRL_EN_SOP2DB_POS                            12
#define REG_PD0_CTRL_EN_SOP2DB_MSK                            (0x1ul           << REG_PD0_CTRL_EN_SOP2DB_POS)
#define REG_PD0_CTRL_EN_SOP2DB_SET(num)                       (((num)          << REG_PD0_CTRL_EN_SOP2DB_POS              ) & REG_PD0_CTRL_EN_SOP2DB_MSK)

#define REG_PD0_CTRL_EN_SOP_AUTO_CRC_POS                      16
#define REG_PD0_CTRL_EN_SOP_AUTO_CRC_MSK                      (0x1ul           << REG_PD0_CTRL_EN_SOP_AUTO_CRC_POS)
#define REG_PD0_CTRL_EN_SOP_AUTO_CRC_SET(num)                 (((num)          << REG_PD0_CTRL_EN_SOP_AUTO_CRC_POS        ) & REG_PD0_CTRL_EN_SOP_AUTO_CRC_MSK)

#define REG_PD0_CTRL_EN_SOP1_AUTO_CRC_POS                     17
#define REG_PD0_CTRL_EN_SOP1_AUTO_CRC_MSK                     (0x1ul           << REG_PD0_CTRL_EN_SOP1_AUTO_CRC_POS)
#define REG_PD0_CTRL_EN_SOP1_AUTO_CRC_SET(num)                (((num)          << REG_PD0_CTRL_EN_SOP1_AUTO_CRC_POS       ) & REG_PD0_CTRL_EN_SOP1_AUTO_CRC_MSK)

#define REG_PD0_CTRL_EN_SOP2_AUTO_CRC_POS                     18
#define REG_PD0_CTRL_EN_SOP2_AUTO_CRC_MSK                     (0x1ul           << REG_PD0_CTRL_EN_SOP2_AUTO_CRC_POS)
#define REG_PD0_CTRL_EN_SOP2_AUTO_CRC_SET(num)                (((num)          << REG_PD0_CTRL_EN_SOP2_AUTO_CRC_POS       ) & REG_PD0_CTRL_EN_SOP2_AUTO_CRC_MSK)

#define REG_PD0_CTRL_EN_SOP1_DB_AUTO_CRC_POS                  19
#define REG_PD0_CTRL_EN_SOP1_DB_AUTO_CRC_MSK                  (0x1ul           << REG_PD0_CTRL_EN_SOP1_DB_AUTO_CRC_POS)
#define REG_PD0_CTRL_EN_SOP1_DB_AUTO_CRC_SET(num)             (((num)          << REG_PD0_CTRL_EN_SOP1_DB_AUTO_CRC_POS    ) & REG_PD0_CTRL_EN_SOP1_DB_AUTO_CRC_MSK)

#define REG_PD0_CTRL_EN_SOP2_DB_AUTO_CRC_POS                  20
#define REG_PD0_CTRL_EN_SOP2_DB_AUTO_CRC_MSK                  (0x1ul           << REG_PD0_CTRL_EN_SOP2_DB_AUTO_CRC_POS)
#define REG_PD0_CTRL_EN_SOP2_DB_AUTO_CRC_SET(num)             (((num)          << REG_PD0_CTRL_EN_SOP2_DB_AUTO_CRC_POS    ) & REG_PD0_CTRL_EN_SOP2_DB_AUTO_CRC_MSK)

#define REG_PD0_CTRL_BIST_MODE2_POS                           24
#define REG_PD0_CTRL_BIST_MODE2_MSK                           (0x1ul           << REG_PD0_CTRL_BIST_MODE2_POS)
#define REG_PD0_CTRL_BIST_MODE2_SET(num)                      (((num)          << REG_PD0_CTRL_BIST_MODE2_POS             ) & REG_PD0_CTRL_BIST_MODE2_MSK)

#define REG_PD0_CTRL_SEND_SOFTRST_POS                         25
#define REG_PD0_CTRL_SEND_SOFTRST_MSK                         (0x1ul           << REG_PD0_CTRL_SEND_SOFTRST_POS)
#define REG_PD0_CTRL_SEND_SOFTRST_SET(num)                    (((num)          << REG_PD0_CTRL_SEND_SOFTRST_POS           ) & REG_PD0_CTRL_SEND_SOFTRST_MSK)

#define REG_PD0_CTRL_SEND_HARDRST_POS                         26
#define REG_PD0_CTRL_SEND_HARDRST_MSK                         (0x1ul           << REG_PD0_CTRL_SEND_HARDRST_POS)
#define REG_PD0_CTRL_SEND_HARDRST_SET(num)                    (((num)          << REG_PD0_CTRL_SEND_HARDRST_POS           ) & REG_PD0_CTRL_SEND_HARDRST_MSK)

#define REG_PD0_CTRL_AUTO_RETRY_POS                           27
#define REG_PD0_CTRL_AUTO_RETRY_MSK                           (0x1ul           << REG_PD0_CTRL_AUTO_RETRY_POS)
#define REG_PD0_CTRL_AUTO_RETRY_SET(num)                      (((num)          << REG_PD0_CTRL_AUTO_RETRY_POS             ) & REG_PD0_CTRL_AUTO_RETRY_MSK)

#define REG_PD0_CTRL_BIST_ALWAYS_ON_POS                       28
#define REG_PD0_CTRL_BIST_ALWAYS_ON_MSK                       (0x1ul           << REG_PD0_CTRL_BIST_ALWAYS_ON_POS)
#define REG_PD0_CTRL_BIST_ALWAYS_ON_SET(num)                  (((num)          << REG_PD0_CTRL_BIST_ALWAYS_ON_POS         ) & REG_PD0_CTRL_BIST_ALWAYS_ON_MSK)

#define REG_PD0_CTRL_WAKE_EN_POS                              29
#define REG_PD0_CTRL_WAKE_EN_MSK                              (0x1ul           << REG_PD0_CTRL_WAKE_EN_POS)
#define REG_PD0_CTRL_WAKE_EN_SET(num)                         (((num)          << REG_PD0_CTRL_WAKE_EN_POS                ) & REG_PD0_CTRL_WAKE_EN_MSK)

#define REG_PD0_POWER_CC_COMP_EN_POS                          0
#define REG_PD0_POWER_CC_COMP_EN_MSK                          (0x1ul           << REG_PD0_POWER_CC_COMP_EN_POS)
#define REG_PD0_POWER_CC_COMP_EN_SET(num)                     (((num)          << REG_PD0_POWER_CC_COMP_EN_POS            ) & REG_PD0_POWER_CC_COMP_EN_MSK)

#define REG_PD0_RESET_SW_RESET_POS                            0
#define REG_PD0_RESET_SW_RESET_MSK                            (0x1ul           << REG_PD0_RESET_SW_RESET_POS)
#define REG_PD0_RESET_SW_RESET_SET(num)                       (((num)          << REG_PD0_RESET_SW_RESET_POS              ) & REG_PD0_RESET_SW_RESET_MSK)

#define REG_PD0_RESET_PD_RESET_POS                            1
#define REG_PD0_RESET_PD_RESET_MSK                            (0x1ul           << REG_PD0_RESET_PD_RESET_POS)
#define REG_PD0_RESET_PD_RESET_SET(num)                       (((num)          << REG_PD0_RESET_PD_RESET_POS              ) & REG_PD0_RESET_PD_RESET_MSK)

#define REG_PD0_INT_MASK_POS                                  0
#define REG_PD0_INT_MASK_MSK                                  (0xeul           << REG_PD0_INT_MASK_POS)
#define REG_PD0_INT_MASK_SET(num)                             (((num)          << REG_PD0_INT_MASK_POS                    ) & REG_PD0_INT_MASK_MSK)

#define REG_PD0_CFG_EN_RX_ROLLBACK_POS                        1
#define REG_PD0_CFG_EN_RX_ROLLBACK_MSK                        (0x1ul           << REG_PD0_CFG_EN_RX_ROLLBACK_POS)
#define REG_PD0_CFG_EN_RX_ROLLBACK_SET(num)                   (((num)          << REG_PD0_CFG_EN_RX_ROLLBACK_POS          ) & REG_PD0_CFG_EN_RX_ROLLBACK_MSK)

#define REG_PD0_CFG_DIS_FULLCHECK_POS                         2
#define REG_PD0_CFG_DIS_FULLCHECK_MSK                         (0x1ul           << REG_PD0_CFG_DIS_FULLCHECK_POS)
#define REG_PD0_CFG_DIS_FULLCHECK_SET(num)                    (((num)          << REG_PD0_CFG_DIS_FULLCHECK_POS           ) & REG_PD0_CFG_DIS_FULLCHECK_MSK)

#define REG_PD0_CFG_ACTIVITY_MODE_POS                         3
#define REG_PD0_CFG_ACTIVITY_MODE_MSK                         (0x2ul           << REG_PD0_CFG_ACTIVITY_MODE_POS)
#define REG_PD0_CFG_ACTIVITY_MODE_SET(num)                    (((num)          << REG_PD0_CFG_ACTIVITY_MODE_POS           ) & REG_PD0_CFG_ACTIVITY_MODE_MSK)

#define REG_PD0_CFG_FORCE_TXEN_POS                            6
#define REG_PD0_CFG_FORCE_TXEN_MSK                            (0x1ul           << REG_PD0_CFG_FORCE_TXEN_POS)
#define REG_PD0_CFG_FORCE_TXEN_SET(num)                       (((num)          << REG_PD0_CFG_FORCE_TXEN_POS              ) & REG_PD0_CFG_FORCE_TXEN_MSK)

#define REG_PD0_CFG_FORCE_RXEN_POS                            7
#define REG_PD0_CFG_FORCE_RXEN_MSK                            (0x1ul           << REG_PD0_CFG_FORCE_RXEN_POS)
#define REG_PD0_CFG_FORCE_RXEN_SET(num)                       (((num)          << REG_PD0_CFG_FORCE_RXEN_POS              ) & REG_PD0_CFG_FORCE_RXEN_MSK)

#define REG_PD0_CFG_DIG_TESTSEL_POS                           12
#define REG_PD0_CFG_DIG_TESTSEL_MSK                           (0x4ul           << REG_PD0_CFG_DIG_TESTSEL_POS)
#define REG_PD0_CFG_DIG_TESTSEL_SET(num)                      (((num)          << REG_PD0_CFG_DIG_TESTSEL_POS             ) & REG_PD0_CFG_DIG_TESTSEL_MSK)

#define REG_PD0_CFG_TRANSMIT_TIMER_POS                        19
#define REG_PD0_CFG_TRANSMIT_TIMER_MSK                        (0x1ul           << REG_PD0_CFG_TRANSMIT_TIMER_POS)
#define REG_PD0_CFG_TRANSMIT_TIMER_SET(num)                   (((num)          << REG_PD0_CFG_TRANSMIT_TIMER_POS          ) & REG_PD0_CFG_TRANSMIT_TIMER_MSK)

//-----------------------------------------------------------------------------


#endif /*__PD0_DEFINE_H__*/