CPS/MXWK_美芯微科/common/reg_def/pwd_define.h

#ifndef __PWD_DEFINE_H__
#define __PWD_DEFINE_H__
//-----------------------------------------------------------------------------
// pwd registers definition                            
//-----------------------------------------------------------------------------
#pragma anon_unions

//-----------------------------------------------------------------------------
// registers structures
typedef struct
{
	//pulse width detection enable
	uint32_t enable:8;
	uint32_t reserved_31_8:24;
} REG_pwd_cfg_bitfiled_TypeDef;

typedef struct
{
	union {
	__IO	REG_pwd_cfg_bitfiled_TypeDef bf;//bitfiled
	__IO	uint32_t word;
	};
} REG_pwd_cfg_TypeDef;

typedef struct
{
	//usb_dp pulse width 1lsb = 1us
	uint32_t width:16;
	//usb_dp pulse level 1: high level 0: low level
	uint32_t level:1;
	uint32_t reserved_31_17:15;
} REG_pwd_ch0_val_bitfiled_TypeDef;

typedef struct
{
	union {
	__IO	REG_pwd_ch0_val_bitfiled_TypeDef bf;//bitfiled
	__IO	uint32_t word;
	};
} REG_pwd_ch0_val_TypeDef;

typedef struct
{
	//usb_dp pulse width 1lsb = 1us
	uint32_t width:16;
	//usb_dp pulse level 1: high level 0: low level
	uint32_t level:1;
	uint32_t reserved_31_17:15;
} REG_pwd_ch1_val_bitfiled_TypeDef;

typedef struct
{
	union {
	__IO	REG_pwd_ch1_val_bitfiled_TypeDef bf;//bitfiled
	__IO	uint32_t word;
	};
} REG_pwd_ch1_val_TypeDef;

typedef struct
{
	//usb_dp pulse width 1lsb = 1us
	uint32_t width:16;
	//usb_dp pulse level 1: high level 0: low level
	uint32_t level:1;
	uint32_t reserved_31_17:15;
} REG_pwd_ch2_val_bitfiled_TypeDef;

typedef struct
{
	union {
	__IO	REG_pwd_ch2_val_bitfiled_TypeDef bf;//bitfiled
	__IO	uint32_t word;
	};
} REG_pwd_ch2_val_TypeDef;

typedef struct
{
	//usb_dp pulse width 1lsb = 1us
	uint32_t width:16;
	//usb_dp pulse level 1: high level 0: low level
	uint32_t level:1;
	uint32_t reserved_31_17:15;
} REG_pwd_ch3_val_bitfiled_TypeDef;

typedef struct
{
	union {
	__IO	REG_pwd_ch3_val_bitfiled_TypeDef bf;//bitfiled
	__IO	uint32_t word;
	};
} REG_pwd_ch3_val_TypeDef;

//-----------------------------------------------------------------------------
// memory map
#define REG_PWD_CFG_BASE                                                       0x4000E000
#define REG_PWD_CH0_VAL_BASE                                                   0x4000E004
#define REG_PWD_CH1_VAL_BASE                                                   0x4000E008
#define REG_PWD_CH2_VAL_BASE                                                   0x4000E00C
#define REG_PWD_CH3_VAL_BASE                                                   0x4000E010
//-----------------------------------------------------------------------------
// declaration
#define REG_PWD_CFG                              ((REG_pwd_cfg_TypeDef                    *) REG_PWD_CFG_BASE                         )
#define REG_PWD_CH0_VAL                          ((REG_pwd_ch0_val_TypeDef                *) REG_PWD_CH0_VAL_BASE                     )
#define REG_PWD_CH1_VAL                          ((REG_pwd_ch1_val_TypeDef                *) REG_PWD_CH1_VAL_BASE                     )
#define REG_PWD_CH2_VAL                          ((REG_pwd_ch2_val_TypeDef                *) REG_PWD_CH2_VAL_BASE                     )
#define REG_PWD_CH3_VAL                          ((REG_pwd_ch3_val_TypeDef                *) REG_PWD_CH3_VAL_BASE                     )
//-----------------------------------------------------------------------------
// set 
#define REG_PWD_CFG_ENABLE_POS                              0
#define REG_PWD_CFG_ENABLE_MSK                             (0xFFul << REG_PWD_CFG_ENABLE_POS)
#define REG_PWD_CFG_ENABLE_SET(num)                        (((num) << REG_PWD_CFG_ENABLE_POS                            ) & REG_PWD_CFG_ENABLE_MSK)

#endif /*__PWD_DEFINE_H__*/