CPS/MXWK_美芯微科/common/reg_def/sysctrl_define.h

#ifndef __SYSCTRL_DEFINE_H__
#define __SYSCTRL_DEFINE_H__
//-----------------------------------------------------------------------------
// sysctrl registers definition                            
//-----------------------------------------------------------------------------
#pragma anon_unions

//-----------------------------------------------------------------------------
// registers structures
typedef struct
{
	uint32_t value:1;
	uint32_t reserved_31_1:31;
} REG_sysctrl_mem_remap_bitfiled_TypeDef;

typedef struct
{
	union {
	__IO	REG_sysctrl_mem_remap_bitfiled_TypeDef bf;//bitfiled
	__IO	uint32_t word;
	};
} REG_sysctrl_mem_remap_TypeDef;


typedef struct
{
	uint32_t value:1;
	uint32_t reserved_31_1:31;
} REG_sysctrl_pmuctrl_bitfiled_TypeDef;

typedef struct
{
	union {
	__IO	REG_sysctrl_pmuctrl_bitfiled_TypeDef bf;//bitfiled
	__IO	uint32_t word;
	};
} REG_sysctrl_pmuctrl_TypeDef;


typedef struct
{
	uint32_t value:1;
	uint32_t reserved_31_1:31;
} REG_sysctrl_resetop_bitfiled_TypeDef;

typedef struct
{
	union {
	__IO	REG_sysctrl_resetop_bitfiled_TypeDef bf;//bitfiled
	__IO	uint32_t word;
	};
} REG_sysctrl_resetop_TypeDef;


typedef struct
{
	uint32_t sys_reset:1;
	uint32_t watchdog_reset:1;
	uint32_t lockup_reset:1;
	uint32_t i2c_sys_reset:1;
	uint32_t i2c_mcu_reset:1;
	uint32_t reserved_31_5:27;
} REG_sysctrl_rstinfo_bitfiled_TypeDef;

typedef struct
{
	union {
	__IO	REG_sysctrl_rstinfo_bitfiled_TypeDef bf;//bitfiled
	__IO	uint32_t word;
	};
} REG_sysctrl_rstinfo_TypeDef;


typedef struct
{
	uint32_t dft_scan_mode_set:1;
	uint32_t dft_comp_mode_set:1;
	uint32_t reserved_31_2:30;
} REG_sysctrl_dftctrl_bitfiled_TypeDef;

typedef struct
{
	union {
	__IO	REG_sysctrl_dftctrl_bitfiled_TypeDef bf;//bitfiled
	__IO	uint32_t word;
	};
} REG_sysctrl_dftctrl_TypeDef;


typedef struct
{
	uint32_t value:6;
	uint32_t reserved_31_6:26;
} REG_sysctrl_int_remap_bitfiled_TypeDef;

typedef struct
{
	union {
	__IO	REG_sysctrl_int_remap_bitfiled_TypeDef bf;//bitfiled
	__IO	uint32_t word;
	};
} REG_sysctrl_int_remap_TypeDef;


//-----------------------------------------------------------------------------


//-----------------------------------------------------------------------------
// memory map
#define REG_SYSCTRL_MEM_REMAP_BASE                  0X4001F000
#define REG_SYSCTRL_PMUCTRL_BASE                    0X4001F004
#define REG_SYSCTRL_RESETOP_BASE                    0X4001F008
#define REG_SYSCTRL_RSTINFO_BASE                    0X4001F010
#define REG_SYSCTRL_DFTCTRL_BASE                    0X4001F014
#define REG_SYSCTRL_INT_REMAP_BASE                  0X4001F018
//-----------------------------------------------------------------------------


//-----------------------------------------------------------------------------
// declaration
#define REG_SYSCTRL_MEM_REMAP                   ((REG_sysctrl_mem_remap_TypeDef              *) REG_SYSCTRL_MEM_REMAP_BASE)
#define REG_SYSCTRL_PMUCTRL                     ((REG_sysctrl_pmuctrl_TypeDef                *) REG_SYSCTRL_PMUCTRL_BASE)
#define REG_SYSCTRL_RESETOP                     ((REG_sysctrl_resetop_TypeDef                *) REG_SYSCTRL_RESETOP_BASE)
#define REG_SYSCTRL_RSTINFO                     ((REG_sysctrl_rstinfo_TypeDef                *) REG_SYSCTRL_RSTINFO_BASE)
#define REG_SYSCTRL_DFTCTRL                     ((REG_sysctrl_dftctrl_TypeDef                *) REG_SYSCTRL_DFTCTRL_BASE)
#define REG_SYSCTRL_INT_REMAP                   ((REG_sysctrl_int_remap_TypeDef              *) REG_SYSCTRL_INT_REMAP_BASE)
//-----------------------------------------------------------------------------


//-----------------------------------------------------------------------------
// set
#define REG_SYSCTRL_MEM_REMAP_POS                             0
#define REG_SYSCTRL_MEM_REMAP_MSK                             (0x1ul           << REG_SYSCTRL_MEM_REMAP_POS)
#define REG_SYSCTRL_MEM_REMAP_SET(num)                        (((num)          << REG_SYSCTRL_MEM_REMAP_POS               ) & REG_SYSCTRL_MEM_REMAP_MSK)

#define REG_SYSCTRL_PMUCTRL_POS                               0
#define REG_SYSCTRL_PMUCTRL_MSK                               (0x1ul           << REG_SYSCTRL_PMUCTRL_POS)
#define REG_SYSCTRL_PMUCTRL_SET(num)                          (((num)          << REG_SYSCTRL_PMUCTRL_POS                 ) & REG_SYSCTRL_PMUCTRL_MSK)

#define REG_SYSCTRL_RESETOP_POS                               0
#define REG_SYSCTRL_RESETOP_MSK                               (0x1ul           << REG_SYSCTRL_RESETOP_POS)
#define REG_SYSCTRL_RESETOP_SET(num)                          (((num)          << REG_SYSCTRL_RESETOP_POS                 ) & REG_SYSCTRL_RESETOP_MSK)

#define REG_SYSCTRL_RSTINFO_SYS_RESET_POS                     0
#define REG_SYSCTRL_RSTINFO_SYS_RESET_MSK                     (0x1ul           << REG_SYSCTRL_RSTINFO_SYS_RESET_POS)
#define REG_SYSCTRL_RSTINFO_SYS_RESET_SET(num)                (((num)          << REG_SYSCTRL_RSTINFO_SYS_RESET_POS       ) & REG_SYSCTRL_RSTINFO_SYS_RESET_MSK)

#define REG_SYSCTRL_RSTINFO_WATCHDOG_RESET_POS                1
#define REG_SYSCTRL_RSTINFO_WATCHDOG_RESET_MSK                (0x1ul           << REG_SYSCTRL_RSTINFO_WATCHDOG_RESET_POS)
#define REG_SYSCTRL_RSTINFO_WATCHDOG_RESET_SET(num)           (((num)          << REG_SYSCTRL_RSTINFO_WATCHDOG_RESET_POS  ) & REG_SYSCTRL_RSTINFO_WATCHDOG_RESET_MSK)

#define REG_SYSCTRL_RSTINFO_LOCKUP_RESET_POS                  2
#define REG_SYSCTRL_RSTINFO_LOCKUP_RESET_MSK                  (0x1ul           << REG_SYSCTRL_RSTINFO_LOCKUP_RESET_POS)
#define REG_SYSCTRL_RSTINFO_LOCKUP_RESET_SET(num)             (((num)          << REG_SYSCTRL_RSTINFO_LOCKUP_RESET_POS    ) & REG_SYSCTRL_RSTINFO_LOCKUP_RESET_MSK)

#define REG_SYSCTRL_RSTINFO_I2C_SYS_RESET_POS                 3
#define REG_SYSCTRL_RSTINFO_I2C_SYS_RESET_MSK                 (0x1ul           << REG_SYSCTRL_RSTINFO_I2C_SYS_RESET_POS)
#define REG_SYSCTRL_RSTINFO_I2C_SYS_RESET_SET(num)            (((num)          << REG_SYSCTRL_RSTINFO_I2C_SYS_RESET_POS   ) & REG_SYSCTRL_RSTINFO_I2C_SYS_RESET_MSK)

#define REG_SYSCTRL_RSTINFO_I2C_MCU_RESET_POS                 4
#define REG_SYSCTRL_RSTINFO_I2C_MCU_RESET_MSK                 (0x1ul           << REG_SYSCTRL_RSTINFO_I2C_MCU_RESET_POS)
#define REG_SYSCTRL_RSTINFO_I2C_MCU_RESET_SET(num)            (((num)          << REG_SYSCTRL_RSTINFO_I2C_MCU_RESET_POS   ) & REG_SYSCTRL_RSTINFO_I2C_MCU_RESET_MSK)

#define REG_SYSCTRL_DFTCTRL_DFT_SCAN_MODE_SET_POS             0
#define REG_SYSCTRL_DFTCTRL_DFT_SCAN_MODE_SET_MSK             (0x1ul           << REG_SYSCTRL_DFTCTRL_DFT_SCAN_MODE_SET_POS)
#define REG_SYSCTRL_DFTCTRL_DFT_SCAN_MODE_SET_SET(num)        (((num)          << REG_SYSCTRL_DFTCTRL_DFT_SCAN_MODE_SET_POS) & REG_SYSCTRL_DFTCTRL_DFT_SCAN_MODE_SET_MSK)

#define REG_SYSCTRL_DFTCTRL_DFT_COMP_MODE_SET_POS             1
#define REG_SYSCTRL_DFTCTRL_DFT_COMP_MODE_SET_MSK             (0x1ul           << REG_SYSCTRL_DFTCTRL_DFT_COMP_MODE_SET_POS)
#define REG_SYSCTRL_DFTCTRL_DFT_COMP_MODE_SET_SET(num)        (((num)          << REG_SYSCTRL_DFTCTRL_DFT_COMP_MODE_SET_POS) & REG_SYSCTRL_DFTCTRL_DFT_COMP_MODE_SET_MSK)

#define REG_SYSCTRL_INT_REMAP_POS                             0
#define REG_SYSCTRL_INT_REMAP_MSK                             (0x6ul           << REG_SYSCTRL_INT_REMAP_POS)
#define REG_SYSCTRL_INT_REMAP_SET(num)                        (((num)          << REG_SYSCTRL_INT_REMAP_POS               ) & REG_SYSCTRL_INT_REMAP_MSK)

//-----------------------------------------------------------------------------


#endif /*__SYSCTRL_DEFINE_H__*/