CPS/MXWK_美芯微科/common/reg_def/uart_define.h

#ifndef __UART_DEFINE_H__
#define __UART_DEFINE_H__
//-----------------------------------------------------------------------------
// uart registers definition                            
//-----------------------------------------------------------------------------
#pragma anon_unions

//-----------------------------------------------------------------------------
// registers structures
typedef struct
{
	uint32_t bdrate_div:16;
	uint32_t reserved_16_16:1;
	uint32_t frm_to_en:1;
	uint32_t reserved_31_18:14;
} REG_uart_configure_rx_bitfiled_TypeDef;

typedef struct
{
	union {
	__IO	REG_uart_configure_rx_bitfiled_TypeDef bf;//bitfiled
	__IO	uint32_t word;
	};
} REG_uart_configure_rx_TypeDef;


typedef struct
{
	uint32_t bdrate_div:16;
	uint32_t bdr_sel:1;
	uint32_t idle_wid:2;
	uint32_t reserved_31_19:13;
} REG_uart_configure_tx_bitfiled_TypeDef;

typedef struct
{
	union {
	__IO	REG_uart_configure_tx_bitfiled_TypeDef bf;//bitfiled
	__IO	uint32_t word;
	};
} REG_uart_configure_tx_TypeDef;


typedef struct
{
	uint32_t rxfrm_to:8;
	uint32_t reserved_31_8:24;
} REG_uart_rxto_bitfiled_TypeDef;

typedef struct
{
	union {
	__IO	REG_uart_rxto_bitfiled_TypeDef bf;//bitfiled
	__IO	uint32_t word;
	};
} REG_uart_rxto_TypeDef;


typedef struct
{
	uint32_t tx_enable:1;
	uint32_t rx_enable:1;
	uint32_t rx_train_en:1;
	uint32_t rx_train_rstr:1;
	uint32_t reserved_31_4:28;
} REG_uart_ctrl_bitfiled_TypeDef;

typedef struct
{
	union {
	__IO	REG_uart_ctrl_bitfiled_TypeDef bf;//bitfiled
	__IO	uint32_t word;
	};
} REG_uart_ctrl_TypeDef;


typedef struct
{
	uint32_t reset_logic:1;
	uint32_t reset_all:1;
	uint32_t reserved_31_2:30;
} REG_uart_reset_bitfiled_TypeDef;

typedef struct
{
	union {
	__IO	REG_uart_reset_bitfiled_TypeDef bf;//bitfiled
	__IO	uint32_t word;
	};
} REG_uart_reset_TypeDef;


typedef struct
{
	uint32_t data_tx:8;
	uint32_t reserved_31_8:24;
} REG_uart_tx_dat_bitfiled_TypeDef;

typedef struct
{
	union {
	__IO	REG_uart_tx_dat_bitfiled_TypeDef bf;//bitfiled
	__IO	uint32_t word;
	};
} REG_uart_tx_dat_TypeDef;


typedef struct
{
	uint32_t data_rx:8;
	uint32_t reserved_31_8:24;
} REG_uart_rx_dat_bitfiled_TypeDef;

typedef struct
{
	union {
	__IO	REG_uart_rx_dat_bitfiled_TypeDef bf;//bitfiled
	__IO	uint32_t word;
	};
} REG_uart_rx_dat_TypeDef;


typedef struct
{
	uint32_t tx_empty:1;
	uint32_t tx_done:1;
	uint32_t rx_full:1;
	uint32_t rx_frm_busy:1;
	uint32_t reserved_15_4:12;
	uint32_t rx_bdrate_use:16;
} REG_uart_status_bitfiled_TypeDef;

typedef struct
{
	union {
	__IO	REG_uart_status_bitfiled_TypeDef bf;//bitfiled
	__IO	uint32_t word;
	};
} REG_uart_status_TypeDef;


typedef struct
{
	uint32_t empty:1;
	uint32_t done:1;
	uint32_t or:1;
	uint32_t reserved_31_3:29;
} REG_uart_int_tx_bitfiled_TypeDef;

typedef struct
{
	union {
	__IO	REG_uart_int_tx_bitfiled_TypeDef bf;//bitfiled
	__IO	uint32_t word;
	};
} REG_uart_int_tx_TypeDef;


typedef struct
{
	uint32_t empty:1;
	uint32_t done:1;
	uint32_t or:1;
	uint32_t reserved_31_3:29;
} REG_uart_int_tx_mask_bitfiled_TypeDef;

typedef struct
{
	union {
	__IO	REG_uart_int_tx_mask_bitfiled_TypeDef bf;//bitfiled
	__IO	uint32_t word;
	};
} REG_uart_int_tx_mask_TypeDef;


typedef struct
{
	uint32_t full:1;
	uint32_t frm_to:1;
	uint32_t frm_or:1;
	uint32_t reserved_3_3:1;
	uint32_t frm_err:1;
	uint32_t rxtr_err:1;
	uint32_t reserved_31_6:26;
} REG_uart_int_rx_bitfiled_TypeDef;

typedef struct
{
	union {
	__IO	REG_uart_int_rx_bitfiled_TypeDef bf;//bitfiled
	__IO	uint32_t word;
	};
} REG_uart_int_rx_TypeDef;


typedef struct
{
	uint32_t full:1;
	uint32_t frm_to:1;
	uint32_t frm_or:1;
	uint32_t reserved_3_3:1;
	uint32_t frm_err:1;
	uint32_t rxtr_err:1;
	uint32_t reserved_31_6:26;
} REG_uart_int_rx_mask_bitfiled_TypeDef;

typedef struct
{
	union {
	__IO	REG_uart_int_rx_mask_bitfiled_TypeDef bf;//bitfiled
	__IO	uint32_t word;
	};
} REG_uart_int_rx_mask_TypeDef;


typedef struct
{
	uint32_t rx_cst:4;
	uint32_t rxtr_cst:4;
	uint32_t tx_cst:4;
	uint32_t reserved_31_12:20;
} REG_uart_fsm_dbg_bitfiled_TypeDef;

typedef struct
{
	union {
	__IO	REG_uart_fsm_dbg_bitfiled_TypeDef bf;//bitfiled
	__IO	uint32_t word;
	};
} REG_uart_fsm_dbg_TypeDef;


typedef struct
{
	uint32_t dig_sel:8;
	uint32_t reserved_31_8:24;
} REG_uart_tst_mode_bitfiled_TypeDef;

typedef struct
{
	union {
	__IO	REG_uart_tst_mode_bitfiled_TypeDef bf;//bitfiled
	__IO	uint32_t word;
	};
} REG_uart_tst_mode_TypeDef;


//-----------------------------------------------------------------------------


//-----------------------------------------------------------------------------
// memory map
#define REG_UART_CONFIGURE_RX_BASE                  0X40001000
#define REG_UART_CONFIGURE_TX_BASE                  0X40001004
#define REG_UART_RXTO_BASE                          0X40001008
#define REG_UART_CTRL_BASE                          0X4000100C
#define REG_UART_RESET_BASE                         0X40001010
#define REG_UART_TX_DAT_BASE                        0X40001014
#define REG_UART_RX_DAT_BASE                        0X4000101C
#define REG_UART_STATUS_BASE                        0X40001020
#define REG_UART_INT_TX_BASE                        0X40001024
#define REG_UART_INT_TX_MASK_BASE                   0X40001028
#define REG_UART_INT_RX_BASE                        0X4000102C
#define REG_UART_INT_RX_MASK_BASE                   0X40001030
#define REG_UART_FSM_DBG_BASE                       0X40001034
#define REG_UART_TST_MODE_BASE                      0X40001038
//-----------------------------------------------------------------------------


//-----------------------------------------------------------------------------
// declaration
#define REG_UART_CONFIGURE_RX                   ((REG_uart_configure_rx_TypeDef              *) REG_UART_CONFIGURE_RX_BASE)
#define REG_UART_CONFIGURE_TX                   ((REG_uart_configure_tx_TypeDef              *) REG_UART_CONFIGURE_TX_BASE)
#define REG_UART_RXTO                           ((REG_uart_rxto_TypeDef                      *) REG_UART_RXTO_BASE)
#define REG_UART_CTRL                           ((REG_uart_ctrl_TypeDef                      *) REG_UART_CTRL_BASE)
#define REG_UART_RESET                          ((REG_uart_reset_TypeDef                     *) REG_UART_RESET_BASE)
#define REG_UART_TX_DAT                         ((REG_uart_tx_dat_TypeDef                    *) REG_UART_TX_DAT_BASE)
#define REG_UART_RX_DAT                         ((REG_uart_rx_dat_TypeDef                    *) REG_UART_RX_DAT_BASE)
#define REG_UART_STATUS                         ((REG_uart_status_TypeDef                    *) REG_UART_STATUS_BASE)
#define REG_UART_INT_TX                         ((REG_uart_int_tx_TypeDef                    *) REG_UART_INT_TX_BASE)
#define REG_UART_INT_TX_MASK                    ((REG_uart_int_tx_mask_TypeDef               *) REG_UART_INT_TX_MASK_BASE)
#define REG_UART_INT_RX                         ((REG_uart_int_rx_TypeDef                    *) REG_UART_INT_RX_BASE)
#define REG_UART_INT_RX_MASK                    ((REG_uart_int_rx_mask_TypeDef               *) REG_UART_INT_RX_MASK_BASE)
#define REG_UART_FSM_DBG                        ((REG_uart_fsm_dbg_TypeDef                   *) REG_UART_FSM_DBG_BASE)
#define REG_UART_TST_MODE                       ((REG_uart_tst_mode_TypeDef                  *) REG_UART_TST_MODE_BASE)
//-----------------------------------------------------------------------------


//-----------------------------------------------------------------------------
// set
#define REG_UART_CONFIGURE_RX_BDRATE_DIV_POS                  0
#define REG_UART_CONFIGURE_RX_BDRATE_DIV_MSK                  (0x10ul          << REG_UART_CONFIGURE_RX_BDRATE_DIV_POS)
#define REG_UART_CONFIGURE_RX_BDRATE_DIV_SET(num)             (((num)          << REG_UART_CONFIGURE_RX_BDRATE_DIV_POS    ) & REG_UART_CONFIGURE_RX_BDRATE_DIV_MSK)

#define REG_UART_CONFIGURE_RX_FRM_TO_EN_POS                   17
#define REG_UART_CONFIGURE_RX_FRM_TO_EN_MSK                   (0x1ul           << REG_UART_CONFIGURE_RX_FRM_TO_EN_POS)
#define REG_UART_CONFIGURE_RX_FRM_TO_EN_SET(num)              (((num)          << REG_UART_CONFIGURE_RX_FRM_TO_EN_POS     ) & REG_UART_CONFIGURE_RX_FRM_TO_EN_MSK)

#define REG_UART_CONFIGURE_TX_BDRATE_DIV_POS                  0
#define REG_UART_CONFIGURE_TX_BDRATE_DIV_MSK                  (0x10ul          << REG_UART_CONFIGURE_TX_BDRATE_DIV_POS)
#define REG_UART_CONFIGURE_TX_BDRATE_DIV_SET(num)             (((num)          << REG_UART_CONFIGURE_TX_BDRATE_DIV_POS    ) & REG_UART_CONFIGURE_TX_BDRATE_DIV_MSK)

#define REG_UART_CONFIGURE_TX_BDR_SEL_POS                     16
#define REG_UART_CONFIGURE_TX_BDR_SEL_MSK                     (0x1ul           << REG_UART_CONFIGURE_TX_BDR_SEL_POS)
#define REG_UART_CONFIGURE_TX_BDR_SEL_SET(num)                (((num)          << REG_UART_CONFIGURE_TX_BDR_SEL_POS       ) & REG_UART_CONFIGURE_TX_BDR_SEL_MSK)

#define REG_UART_CONFIGURE_TX_IDLE_WID_POS                    17
#define REG_UART_CONFIGURE_TX_IDLE_WID_MSK                    (0x2ul           << REG_UART_CONFIGURE_TX_IDLE_WID_POS)
#define REG_UART_CONFIGURE_TX_IDLE_WID_SET(num)               (((num)          << REG_UART_CONFIGURE_TX_IDLE_WID_POS      ) & REG_UART_CONFIGURE_TX_IDLE_WID_MSK)

#define REG_UART_RXTO_RXFRM_TO_POS                            0
#define REG_UART_RXTO_RXFRM_TO_MSK                            (0x8ul           << REG_UART_RXTO_RXFRM_TO_POS)
#define REG_UART_RXTO_RXFRM_TO_SET(num)                       (((num)          << REG_UART_RXTO_RXFRM_TO_POS              ) & REG_UART_RXTO_RXFRM_TO_MSK)

#define REG_UART_CTRL_TX_ENABLE_POS                           0
#define REG_UART_CTRL_TX_ENABLE_MSK                           (0x1ul           << REG_UART_CTRL_TX_ENABLE_POS)
#define REG_UART_CTRL_TX_ENABLE_SET(num)                      (((num)          << REG_UART_CTRL_TX_ENABLE_POS             ) & REG_UART_CTRL_TX_ENABLE_MSK)

#define REG_UART_CTRL_RX_ENABLE_POS                           1
#define REG_UART_CTRL_RX_ENABLE_MSK                           (0x1ul           << REG_UART_CTRL_RX_ENABLE_POS)
#define REG_UART_CTRL_RX_ENABLE_SET(num)                      (((num)          << REG_UART_CTRL_RX_ENABLE_POS             ) & REG_UART_CTRL_RX_ENABLE_MSK)

#define REG_UART_CTRL_RX_TRAIN_EN_POS                         2
#define REG_UART_CTRL_RX_TRAIN_EN_MSK                         (0x1ul           << REG_UART_CTRL_RX_TRAIN_EN_POS)
#define REG_UART_CTRL_RX_TRAIN_EN_SET(num)                    (((num)          << REG_UART_CTRL_RX_TRAIN_EN_POS           ) & REG_UART_CTRL_RX_TRAIN_EN_MSK)

#define REG_UART_CTRL_RX_TRAIN_RSTR_POS                       3
#define REG_UART_CTRL_RX_TRAIN_RSTR_MSK                       (0x1ul           << REG_UART_CTRL_RX_TRAIN_RSTR_POS)
#define REG_UART_CTRL_RX_TRAIN_RSTR_SET(num)                  (((num)          << REG_UART_CTRL_RX_TRAIN_RSTR_POS         ) & REG_UART_CTRL_RX_TRAIN_RSTR_MSK)

#define REG_UART_RESET_RESET_LOGIC_POS                        0
#define REG_UART_RESET_RESET_LOGIC_MSK                        (0x1ul           << REG_UART_RESET_RESET_LOGIC_POS)
#define REG_UART_RESET_RESET_LOGIC_SET(num)                   (((num)          << REG_UART_RESET_RESET_LOGIC_POS          ) & REG_UART_RESET_RESET_LOGIC_MSK)

#define REG_UART_RESET_RESET_ALL_POS                          1
#define REG_UART_RESET_RESET_ALL_MSK                          (0x1ul           << REG_UART_RESET_RESET_ALL_POS)
#define REG_UART_RESET_RESET_ALL_SET(num)                     (((num)          << REG_UART_RESET_RESET_ALL_POS            ) & REG_UART_RESET_RESET_ALL_MSK)

#define REG_UART_TX_DAT_DATA_TX_POS                           0
#define REG_UART_TX_DAT_DATA_TX_MSK                           (0x8ul           << REG_UART_TX_DAT_DATA_TX_POS)
#define REG_UART_TX_DAT_DATA_TX_SET(num)                      (((num)          << REG_UART_TX_DAT_DATA_TX_POS             ) & REG_UART_TX_DAT_DATA_TX_MSK)

#define REG_UART_INT_TX_MASK_EMPTY_POS                        0
#define REG_UART_INT_TX_MASK_EMPTY_MSK                        (0x1ul           << REG_UART_INT_TX_MASK_EMPTY_POS)
#define REG_UART_INT_TX_MASK_EMPTY_SET(num)                   (((num)          << REG_UART_INT_TX_MASK_EMPTY_POS          ) & REG_UART_INT_TX_MASK_EMPTY_MSK)

#define REG_UART_INT_TX_MASK_DONE_POS                         1
#define REG_UART_INT_TX_MASK_DONE_MSK                         (0x1ul           << REG_UART_INT_TX_MASK_DONE_POS)
#define REG_UART_INT_TX_MASK_DONE_SET(num)                    (((num)          << REG_UART_INT_TX_MASK_DONE_POS           ) & REG_UART_INT_TX_MASK_DONE_MSK)

#define REG_UART_INT_TX_MASK_OR_POS                           2
#define REG_UART_INT_TX_MASK_OR_MSK                           (0x1ul           << REG_UART_INT_TX_MASK_OR_POS)
#define REG_UART_INT_TX_MASK_OR_SET(num)                      (((num)          << REG_UART_INT_TX_MASK_OR_POS             ) & REG_UART_INT_TX_MASK_OR_MSK)

#define REG_UART_INT_RX_MASK_FULL_POS                         0
#define REG_UART_INT_RX_MASK_FULL_MSK                         (0x1ul           << REG_UART_INT_RX_MASK_FULL_POS)
#define REG_UART_INT_RX_MASK_FULL_SET(num)                    (((num)          << REG_UART_INT_RX_MASK_FULL_POS           ) & REG_UART_INT_RX_MASK_FULL_MSK)

#define REG_UART_INT_RX_MASK_FRM_TO_POS                       1
#define REG_UART_INT_RX_MASK_FRM_TO_MSK                       (0x1ul           << REG_UART_INT_RX_MASK_FRM_TO_POS)
#define REG_UART_INT_RX_MASK_FRM_TO_SET(num)                  (((num)          << REG_UART_INT_RX_MASK_FRM_TO_POS         ) & REG_UART_INT_RX_MASK_FRM_TO_MSK)

#define REG_UART_INT_RX_MASK_FRM_OR_POS                       2
#define REG_UART_INT_RX_MASK_FRM_OR_MSK                       (0x1ul           << REG_UART_INT_RX_MASK_FRM_OR_POS)
#define REG_UART_INT_RX_MASK_FRM_OR_SET(num)                  (((num)          << REG_UART_INT_RX_MASK_FRM_OR_POS         ) & REG_UART_INT_RX_MASK_FRM_OR_MSK)

#define REG_UART_INT_RX_MASK_FRM_ERR_POS                      4
#define REG_UART_INT_RX_MASK_FRM_ERR_MSK                      (0x1ul           << REG_UART_INT_RX_MASK_FRM_ERR_POS)
#define REG_UART_INT_RX_MASK_FRM_ERR_SET(num)                 (((num)          << REG_UART_INT_RX_MASK_FRM_ERR_POS        ) & REG_UART_INT_RX_MASK_FRM_ERR_MSK)

#define REG_UART_INT_RX_MASK_RXTR_ERR_POS                     5
#define REG_UART_INT_RX_MASK_RXTR_ERR_MSK                     (0x1ul           << REG_UART_INT_RX_MASK_RXTR_ERR_POS)
#define REG_UART_INT_RX_MASK_RXTR_ERR_SET(num)                (((num)          << REG_UART_INT_RX_MASK_RXTR_ERR_POS       ) & REG_UART_INT_RX_MASK_RXTR_ERR_MSK)

#define REG_UART_TST_MODE_DIG_SEL_POS                         0
#define REG_UART_TST_MODE_DIG_SEL_MSK                         (0x8ul           << REG_UART_TST_MODE_DIG_SEL_POS)
#define REG_UART_TST_MODE_DIG_SEL_SET(num)                    (((num)          << REG_UART_TST_MODE_DIG_SEL_POS           ) & REG_UART_TST_MODE_DIG_SEL_MSK)

//-----------------------------------------------------------------------------


#endif /*__UART_DEFINE_H__*/