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419 lines
16 KiB
419 lines
16 KiB
#ifndef __UFCS1_DEFINE_H__
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#define __UFCS1_DEFINE_H__
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//-----------------------------------------------------------------------------
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// ufcs1 registers definition
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//-----------------------------------------------------------------------------
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#pragma anon_unions
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//-----------------------------------------------------------------------------
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// registers structures
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typedef struct
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{
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uint32_t tx_enable:1;
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uint32_t rx_enable:1;
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uint32_t rxstop_en:1;
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uint32_t reserved_5_3:3;
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uint32_t hwrst_cble:1;
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uint32_t hwrst_tx:1;
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uint32_t stop_tx:1;
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uint32_t reserved_10_9:2;
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uint32_t tx_idle_wid:2;
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uint32_t reserved_31_13:19;
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} REG_ufcs1_ctrl_bitfiled_TypeDef;
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typedef struct
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{
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union {
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__IO REG_ufcs1_ctrl_bitfiled_TypeDef bf;//bitfiled
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__IO uint32_t word;
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};
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} REG_ufcs1_ctrl_TypeDef;
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typedef struct
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{
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uint32_t reset_logic:1;
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uint32_t reset_all:1;
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uint32_t reserved_31_2:30;
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} REG_ufcs1_reset_bitfiled_TypeDef;
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typedef struct
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{
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union {
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__IO REG_ufcs1_reset_bitfiled_TypeDef bf;//bitfiled
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__IO uint32_t word;
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};
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} REG_ufcs1_reset_TypeDef;
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typedef struct
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{
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uint32_t bdrate_tx:2;
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uint32_t rxtr_err:1;
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uint32_t reserved_15_3:13;
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uint32_t rx:16;
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} REG_ufcs1_bdrate_bitfiled_TypeDef;
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typedef struct
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{
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union {
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__IO REG_ufcs1_bdrate_bitfiled_TypeDef bf;//bitfiled
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__IO uint32_t word;
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};
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} REG_ufcs1_bdrate_TypeDef;
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typedef struct
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{
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uint32_t end:1;
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uint32_t crc_pass:1;
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uint32_t crc_fail:1;
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uint32_t type:3;
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uint32_t rxinfrm_to:1;
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uint32_t rxbtwfrm_to:1;
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uint32_t rx_processing:1;
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uint32_t rxhwrst_processing:1;
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uint32_t reserved_15_10:6;
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uint32_t len:9;
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uint32_t reserved_31_25:7;
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} REG_ufcs1_rxpkt_bitfiled_TypeDef;
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typedef struct
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{
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union {
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__IO REG_ufcs1_rxpkt_bitfiled_TypeDef bf;//bitfiled
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__IO uint32_t word;
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};
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} REG_ufcs1_rxpkt_TypeDef;
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typedef struct
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{
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uint32_t end:1;
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uint32_t processing:1;
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uint32_t reserved_7_2:6;
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uint32_t crc:8;
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uint32_t len:9;
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uint32_t reserved_31_25:7;
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} REG_ufcs1_txpkt_bitfiled_TypeDef;
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typedef struct
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{
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union {
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__IO REG_ufcs1_txpkt_bitfiled_TypeDef bf;//bitfiled
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__IO uint32_t word;
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};
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} REG_ufcs1_txpkt_TypeDef;
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typedef struct
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{
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uint32_t data:8;
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uint32_t reserved_31_8:24;
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} REG_ufcs1_rx_dat_bitfiled_TypeDef;
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typedef struct
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{
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union {
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__IO REG_ufcs1_rx_dat_bitfiled_TypeDef bf;//bitfiled
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__IO uint32_t word;
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};
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} REG_ufcs1_rx_dat_TypeDef;
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typedef struct
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{
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uint32_t data:8;
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uint32_t reserved_31_8:24;
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} REG_ufcs1_tx_dat_bitfiled_TypeDef;
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typedef struct
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{
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union {
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__IO REG_ufcs1_tx_dat_bitfiled_TypeDef bf;//bitfiled
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__IO uint32_t word;
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};
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} REG_ufcs1_tx_dat_TypeDef;
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typedef struct
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{
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uint32_t pkt_end:1;
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uint32_t pkt_crc_pass:1;
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uint32_t pkt_crc_fail:1;
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uint32_t pkt_type_err:1;
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uint32_t pkt_len_err:1;
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uint32_t tr_err:1;
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uint32_t infrm_to:1;
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uint32_t btwfrm_to:1;
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uint32_t hwrst:1;
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uint32_t reserved_31_9:23;
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} REG_ufcs1_int_rx_bitfiled_TypeDef;
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typedef struct
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{
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union {
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__IO REG_ufcs1_int_rx_bitfiled_TypeDef bf;//bitfiled
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__IO uint32_t word;
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};
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} REG_ufcs1_int_rx_TypeDef;
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typedef struct
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{
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uint32_t pkt_end:1;
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uint32_t pkt_crc_pass:1;
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uint32_t pkt_crc_fail:1;
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uint32_t pkt_type_err:1;
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uint32_t pkt_len_err:1;
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uint32_t tr_err:1;
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uint32_t infrm_to:1;
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uint32_t btwfrm_to:1;
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uint32_t hwrst:1;
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uint32_t reserved_31_9:23;
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} REG_ufcs1_int_rx_mask_bitfiled_TypeDef;
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typedef struct
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{
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union {
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__IO REG_ufcs1_int_rx_mask_bitfiled_TypeDef bf;//bitfiled
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__IO uint32_t word;
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};
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} REG_ufcs1_int_rx_mask_TypeDef;
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typedef struct
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{
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uint32_t pkt_end:1;
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uint32_t cble_hwrst:1;
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uint32_t tx_hwrst:1;
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uint32_t reserved_31_3:29;
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} REG_ufcs1_int_tx_bitfiled_TypeDef;
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typedef struct
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{
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union {
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__IO REG_ufcs1_int_tx_bitfiled_TypeDef bf;//bitfiled
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__IO uint32_t word;
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};
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} REG_ufcs1_int_tx_TypeDef;
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typedef struct
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{
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uint32_t pkt_end:1;
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uint32_t cble_hwrst:1;
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uint32_t tx_hwrst:1;
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uint32_t reserved_31_3:29;
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} REG_ufcs1_int_tx_mask_bitfiled_TypeDef;
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typedef struct
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{
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union {
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__IO REG_ufcs1_int_tx_mask_bitfiled_TypeDef bf;//bitfiled
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__IO uint32_t word;
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};
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} REG_ufcs1_int_tx_mask_TypeDef;
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typedef struct
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{
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uint32_t rxtr_cst:4;
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uint32_t rxfrm_cst:4;
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uint32_t rxpkt_cst:4;
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uint32_t reserved_15_12:4;
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uint32_t txfrm_cst:4;
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uint32_t txpkt_cst:4;
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uint32_t txdio_cst:3;
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uint32_t reserved_31_27:5;
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} REG_ufcs1_fsm_dbg_bitfiled_TypeDef;
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typedef struct
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{
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union {
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__IO REG_ufcs1_fsm_dbg_bitfiled_TypeDef bf;//bitfiled
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__IO uint32_t word;
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};
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} REG_ufcs1_fsm_dbg_TypeDef;
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typedef struct
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{
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uint32_t dig_sel:8;
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uint32_t reserved_31_8:24;
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} REG_ufcs1_tst_mode_bitfiled_TypeDef;
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typedef struct
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{
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union {
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__IO REG_ufcs1_tst_mode_bitfiled_TypeDef bf;//bitfiled
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__IO uint32_t word;
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};
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} REG_ufcs1_tst_mode_TypeDef;
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typedef struct
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{
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uint32_t rx_wid:4;
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uint32_t tx_wid:4;
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uint32_t cble_wid:4;
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uint32_t reserved_31_12:20;
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} REG_ufcs1_hwrst_bitfiled_TypeDef;
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typedef struct
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{
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union {
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__IO REG_ufcs1_hwrst_bitfiled_TypeDef bf;//bitfiled
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__IO uint32_t word;
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};
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} REG_ufcs1_hwrst_TypeDef;
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//-----------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
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// memory map
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#define REG_UFCS1_CTRL_BASE 0X40001000
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#define REG_UFCS1_RESET_BASE 0X40001004
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#define REG_UFCS1_BDRATE_BASE 0X40001008
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#define REG_UFCS1_RXPKT_BASE 0X4000100C
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#define REG_UFCS1_TXPKT_BASE 0X40001010
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#define REG_UFCS1_RX_DAT_BASE 0X40001020
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#define REG_UFCS1_TX_DAT_BASE 0X40001024
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#define REG_UFCS1_INT_RX_BASE 0X40001028
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#define REG_UFCS1_INT_RX_MASK_BASE 0X4000102C
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#define REG_UFCS1_INT_TX_BASE 0X40001030
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#define REG_UFCS1_INT_TX_MASK_BASE 0X40001034
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#define REG_UFCS1_FSM_DBG_BASE 0X40001038
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#define REG_UFCS1_TST_MODE_BASE 0X4000103C
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#define REG_UFCS1_HWRST_BASE 0X40001040
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//-----------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
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// declaration
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#define REG_UFCS1_CTRL ((REG_ufcs1_ctrl_TypeDef *) REG_UFCS1_CTRL_BASE)
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#define REG_UFCS1_RESET ((REG_ufcs1_reset_TypeDef *) REG_UFCS1_RESET_BASE)
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#define REG_UFCS1_BDRATE ((REG_ufcs1_bdrate_TypeDef *) REG_UFCS1_BDRATE_BASE)
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#define REG_UFCS1_RXPKT ((REG_ufcs1_rxpkt_TypeDef *) REG_UFCS1_RXPKT_BASE)
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#define REG_UFCS1_TXPKT ((REG_ufcs1_txpkt_TypeDef *) REG_UFCS1_TXPKT_BASE)
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#define REG_UFCS1_RX_DAT ((REG_ufcs1_rx_dat_TypeDef *) REG_UFCS1_RX_DAT_BASE)
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#define REG_UFCS1_TX_DAT ((REG_ufcs1_tx_dat_TypeDef *) REG_UFCS1_TX_DAT_BASE)
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#define REG_UFCS1_INT_RX ((REG_ufcs1_int_rx_TypeDef *) REG_UFCS1_INT_RX_BASE)
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#define REG_UFCS1_INT_RX_MASK ((REG_ufcs1_int_rx_mask_TypeDef *) REG_UFCS1_INT_RX_MASK_BASE)
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#define REG_UFCS1_INT_TX ((REG_ufcs1_int_tx_TypeDef *) REG_UFCS1_INT_TX_BASE)
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#define REG_UFCS1_INT_TX_MASK ((REG_ufcs1_int_tx_mask_TypeDef *) REG_UFCS1_INT_TX_MASK_BASE)
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#define REG_UFCS1_FSM_DBG ((REG_ufcs1_fsm_dbg_TypeDef *) REG_UFCS1_FSM_DBG_BASE)
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#define REG_UFCS1_TST_MODE ((REG_ufcs1_tst_mode_TypeDef *) REG_UFCS1_TST_MODE_BASE)
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#define REG_UFCS1_HWRST ((REG_ufcs1_hwrst_TypeDef *) REG_UFCS1_HWRST_BASE)
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//-----------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
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// set
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#define REG_UFCS1_CTRL_TX_ENABLE_POS 0
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#define REG_UFCS1_CTRL_TX_ENABLE_MSK (0x1ul << REG_UFCS1_CTRL_TX_ENABLE_POS)
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#define REG_UFCS1_CTRL_TX_ENABLE_SET(num) (((num) << REG_UFCS1_CTRL_TX_ENABLE_POS ) & REG_UFCS1_CTRL_TX_ENABLE_MSK)
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#define REG_UFCS1_CTRL_RXSTOP_EN_POS 2
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#define REG_UFCS1_CTRL_RXSTOP_EN_MSK (0x1ul << REG_UFCS1_CTRL_RXSTOP_EN_POS)
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#define REG_UFCS1_CTRL_RXSTOP_EN_SET(num) (((num) << REG_UFCS1_CTRL_RXSTOP_EN_POS ) & REG_UFCS1_CTRL_RXSTOP_EN_MSK)
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#define REG_UFCS1_CTRL_STOP_TX_POS 8
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#define REG_UFCS1_CTRL_STOP_TX_MSK (0x1ul << REG_UFCS1_CTRL_STOP_TX_POS)
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#define REG_UFCS1_CTRL_STOP_TX_SET(num) (((num) << REG_UFCS1_CTRL_STOP_TX_POS ) & REG_UFCS1_CTRL_STOP_TX_MSK)
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#define REG_UFCS1_CTRL_TX_IDLE_WID_POS 11
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#define REG_UFCS1_CTRL_TX_IDLE_WID_MSK (0x2ul << REG_UFCS1_CTRL_TX_IDLE_WID_POS)
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#define REG_UFCS1_CTRL_TX_IDLE_WID_SET(num) (((num) << REG_UFCS1_CTRL_TX_IDLE_WID_POS ) & REG_UFCS1_CTRL_TX_IDLE_WID_MSK)
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#define REG_UFCS1_RESET_RESET_LOGIC_POS 0
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#define REG_UFCS1_RESET_RESET_LOGIC_MSK (0x1ul << REG_UFCS1_RESET_RESET_LOGIC_POS)
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#define REG_UFCS1_RESET_RESET_LOGIC_SET(num) (((num) << REG_UFCS1_RESET_RESET_LOGIC_POS ) & REG_UFCS1_RESET_RESET_LOGIC_MSK)
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#define REG_UFCS1_RESET_RESET_ALL_POS 1
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#define REG_UFCS1_RESET_RESET_ALL_MSK (0x1ul << REG_UFCS1_RESET_RESET_ALL_POS)
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#define REG_UFCS1_RESET_RESET_ALL_SET(num) (((num) << REG_UFCS1_RESET_RESET_ALL_POS ) & REG_UFCS1_RESET_RESET_ALL_MSK)
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#define REG_UFCS1_BDRATE_BDRATE_TX_POS 0
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#define REG_UFCS1_BDRATE_BDRATE_TX_MSK (0x2ul << REG_UFCS1_BDRATE_BDRATE_TX_POS)
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#define REG_UFCS1_BDRATE_BDRATE_TX_SET(num) (((num) << REG_UFCS1_BDRATE_BDRATE_TX_POS ) & REG_UFCS1_BDRATE_BDRATE_TX_MSK)
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#define REG_UFCS1_TXPKT_LEN_POS 16
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#define REG_UFCS1_TXPKT_LEN_MSK (0x9ul << REG_UFCS1_TXPKT_LEN_POS)
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#define REG_UFCS1_TXPKT_LEN_SET(num) (((num) << REG_UFCS1_TXPKT_LEN_POS ) & REG_UFCS1_TXPKT_LEN_MSK)
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#define REG_UFCS1_TX_DAT_DATA_POS 0
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#define REG_UFCS1_TX_DAT_DATA_MSK (0x8ul << REG_UFCS1_TX_DAT_DATA_POS)
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#define REG_UFCS1_TX_DAT_DATA_SET(num) (((num) << REG_UFCS1_TX_DAT_DATA_POS ) & REG_UFCS1_TX_DAT_DATA_MSK)
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#define REG_UFCS1_INT_RX_MASK_PKT_END_POS 0
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#define REG_UFCS1_INT_RX_MASK_PKT_END_MSK (0x1ul << REG_UFCS1_INT_RX_MASK_PKT_END_POS)
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#define REG_UFCS1_INT_RX_MASK_PKT_END_SET(num) (((num) << REG_UFCS1_INT_RX_MASK_PKT_END_POS ) & REG_UFCS1_INT_RX_MASK_PKT_END_MSK)
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#define REG_UFCS1_INT_RX_MASK_PKT_CRC_PASS_POS 1
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#define REG_UFCS1_INT_RX_MASK_PKT_CRC_PASS_MSK (0x1ul << REG_UFCS1_INT_RX_MASK_PKT_CRC_PASS_POS)
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#define REG_UFCS1_INT_RX_MASK_PKT_CRC_PASS_SET(num) (((num) << REG_UFCS1_INT_RX_MASK_PKT_CRC_PASS_POS ) & REG_UFCS1_INT_RX_MASK_PKT_CRC_PASS_MSK)
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#define REG_UFCS1_INT_RX_MASK_PKT_CRC_FAIL_POS 2
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#define REG_UFCS1_INT_RX_MASK_PKT_CRC_FAIL_MSK (0x1ul << REG_UFCS1_INT_RX_MASK_PKT_CRC_FAIL_POS)
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#define REG_UFCS1_INT_RX_MASK_PKT_CRC_FAIL_SET(num) (((num) << REG_UFCS1_INT_RX_MASK_PKT_CRC_FAIL_POS ) & REG_UFCS1_INT_RX_MASK_PKT_CRC_FAIL_MSK)
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#define REG_UFCS1_INT_RX_MASK_PKT_TYPE_ERR_POS 3
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#define REG_UFCS1_INT_RX_MASK_PKT_TYPE_ERR_MSK (0x1ul << REG_UFCS1_INT_RX_MASK_PKT_TYPE_ERR_POS)
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#define REG_UFCS1_INT_RX_MASK_PKT_TYPE_ERR_SET(num) (((num) << REG_UFCS1_INT_RX_MASK_PKT_TYPE_ERR_POS ) & REG_UFCS1_INT_RX_MASK_PKT_TYPE_ERR_MSK)
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#define REG_UFCS1_INT_RX_MASK_PKT_LEN_ERR_POS 4
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#define REG_UFCS1_INT_RX_MASK_PKT_LEN_ERR_MSK (0x1ul << REG_UFCS1_INT_RX_MASK_PKT_LEN_ERR_POS)
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#define REG_UFCS1_INT_RX_MASK_PKT_LEN_ERR_SET(num) (((num) << REG_UFCS1_INT_RX_MASK_PKT_LEN_ERR_POS ) & REG_UFCS1_INT_RX_MASK_PKT_LEN_ERR_MSK)
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#define REG_UFCS1_INT_RX_MASK_TR_ERR_POS 5
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#define REG_UFCS1_INT_RX_MASK_TR_ERR_MSK (0x1ul << REG_UFCS1_INT_RX_MASK_TR_ERR_POS)
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#define REG_UFCS1_INT_RX_MASK_TR_ERR_SET(num) (((num) << REG_UFCS1_INT_RX_MASK_TR_ERR_POS ) & REG_UFCS1_INT_RX_MASK_TR_ERR_MSK)
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#define REG_UFCS1_INT_RX_MASK_INFRM_TO_POS 6
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#define REG_UFCS1_INT_RX_MASK_INFRM_TO_MSK (0x1ul << REG_UFCS1_INT_RX_MASK_INFRM_TO_POS)
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#define REG_UFCS1_INT_RX_MASK_INFRM_TO_SET(num) (((num) << REG_UFCS1_INT_RX_MASK_INFRM_TO_POS ) & REG_UFCS1_INT_RX_MASK_INFRM_TO_MSK)
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#define REG_UFCS1_INT_RX_MASK_BTWFRM_TO_POS 7
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#define REG_UFCS1_INT_RX_MASK_BTWFRM_TO_MSK (0x1ul << REG_UFCS1_INT_RX_MASK_BTWFRM_TO_POS)
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#define REG_UFCS1_INT_RX_MASK_BTWFRM_TO_SET(num) (((num) << REG_UFCS1_INT_RX_MASK_BTWFRM_TO_POS ) & REG_UFCS1_INT_RX_MASK_BTWFRM_TO_MSK)
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#define REG_UFCS1_INT_RX_MASK_HWRST_POS 8
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#define REG_UFCS1_INT_RX_MASK_HWRST_MSK (0x1ul << REG_UFCS1_INT_RX_MASK_HWRST_POS)
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#define REG_UFCS1_INT_RX_MASK_HWRST_SET(num) (((num) << REG_UFCS1_INT_RX_MASK_HWRST_POS ) & REG_UFCS1_INT_RX_MASK_HWRST_MSK)
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#define REG_UFCS1_INT_TX_MASK_PKT_END_POS 0
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#define REG_UFCS1_INT_TX_MASK_PKT_END_MSK (0x1ul << REG_UFCS1_INT_TX_MASK_PKT_END_POS)
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#define REG_UFCS1_INT_TX_MASK_PKT_END_SET(num) (((num) << REG_UFCS1_INT_TX_MASK_PKT_END_POS ) & REG_UFCS1_INT_TX_MASK_PKT_END_MSK)
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#define REG_UFCS1_INT_TX_MASK_CBLE_HWRST_POS 1
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#define REG_UFCS1_INT_TX_MASK_CBLE_HWRST_MSK (0x1ul << REG_UFCS1_INT_TX_MASK_CBLE_HWRST_POS)
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#define REG_UFCS1_INT_TX_MASK_CBLE_HWRST_SET(num) (((num) << REG_UFCS1_INT_TX_MASK_CBLE_HWRST_POS ) & REG_UFCS1_INT_TX_MASK_CBLE_HWRST_MSK)
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#define REG_UFCS1_INT_TX_MASK_TX_HWRST_POS 2
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#define REG_UFCS1_INT_TX_MASK_TX_HWRST_MSK (0x1ul << REG_UFCS1_INT_TX_MASK_TX_HWRST_POS)
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#define REG_UFCS1_INT_TX_MASK_TX_HWRST_SET(num) (((num) << REG_UFCS1_INT_TX_MASK_TX_HWRST_POS ) & REG_UFCS1_INT_TX_MASK_TX_HWRST_MSK)
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#define REG_UFCS1_TST_MODE_DIG_SEL_POS 0
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#define REG_UFCS1_TST_MODE_DIG_SEL_MSK (0x8ul << REG_UFCS1_TST_MODE_DIG_SEL_POS)
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#define REG_UFCS1_TST_MODE_DIG_SEL_SET(num) (((num) << REG_UFCS1_TST_MODE_DIG_SEL_POS ) & REG_UFCS1_TST_MODE_DIG_SEL_MSK)
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#define REG_UFCS1_HWRST_RX_WID_POS 0
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#define REG_UFCS1_HWRST_RX_WID_MSK (0x4ul << REG_UFCS1_HWRST_RX_WID_POS)
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#define REG_UFCS1_HWRST_RX_WID_SET(num) (((num) << REG_UFCS1_HWRST_RX_WID_POS ) & REG_UFCS1_HWRST_RX_WID_MSK)
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#define REG_UFCS1_HWRST_TX_WID_POS 4
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#define REG_UFCS1_HWRST_TX_WID_MSK (0x4ul << REG_UFCS1_HWRST_TX_WID_POS)
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#define REG_UFCS1_HWRST_TX_WID_SET(num) (((num) << REG_UFCS1_HWRST_TX_WID_POS ) & REG_UFCS1_HWRST_TX_WID_MSK)
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#define REG_UFCS1_HWRST_CBLE_WID_POS 8
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#define REG_UFCS1_HWRST_CBLE_WID_MSK (0x4ul << REG_UFCS1_HWRST_CBLE_WID_POS)
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#define REG_UFCS1_HWRST_CBLE_WID_SET(num) (((num) << REG_UFCS1_HWRST_CBLE_WID_POS ) & REG_UFCS1_HWRST_CBLE_WID_MSK)
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//-----------------------------------------------------------------------------
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#endif /*__UFCS1_DEFINE_H__*/
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