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165 lines
6.4 KiB
165 lines
6.4 KiB
#ifndef __VD_DEFINE_H__
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#define __VD_DEFINE_H__
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//-----------------------------------------------------------------------------
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// vd registers definition
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//-----------------------------------------------------------------------------
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#pragma anon_unions
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//-----------------------------------------------------------------------------
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// registers structures
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typedef struct
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{
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//vd low side comparator output high pulse width 41.6ns / lsb,max 21.33us
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uint32_t high_width:9;
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//vd low side comparator output low pulse width 41.6ns / lsb,max21.33us
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uint32_t low_width:9;
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//vd low side comparator output high pulse rising edge interval time 1. 12-bit with 24mhz clock (41.6ns/lsb) max 170us
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//2. it can be read by mcu
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uint32_t pwm:12;
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//vd low side comparator output high pulse rising edge interval time,time out flag,max170us,canbe write 1 clr by mcu
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uint32_t pwm_to_flag:1;
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uint32_t reserved_31_31:1;
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} REG_vd_ls_comp_bitfiled_TypeDef;
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typedef struct
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{
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union {
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__IO REG_vd_ls_comp_bitfiled_TypeDef bf;//bitfiled
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__IO uint32_t word;
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};
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} REG_vd_ls_comp_TypeDef;
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typedef struct
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{
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//register-optional vd rising edge blanking time,41.6ns / lsb,max:2.67us
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uint32_t blank_time:6;
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uint32_t reserved_31_6:26;
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} REG_vd_ls_bitfiled_TypeDef;
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typedef struct
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{
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union {
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__IO REG_vd_ls_bitfiled_TypeDef bf;//bitfiled
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__IO uint32_t word;
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};
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} REG_vd_ls_TypeDef;
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typedef struct
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{
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//debug signal select
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uint32_t sel:2;
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uint32_t reserved_2_2:1;
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//vd width fsm
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uint32_t vdw_cst:2;
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uint32_t reserved_15_5:11;
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//vd width counter
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uint32_t vdw_cnt:16;
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} REG_vd_dbg_bitfiled_TypeDef;
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typedef struct
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{
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union {
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__IO REG_vd_dbg_bitfiled_TypeDef bf;//bitfiled
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__IO uint32_t word;
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};
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} REG_vd_dbg_TypeDef;
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typedef struct
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{
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//1'b1:ac off counter 100ms flag, canbe write 1 clr by mcu
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uint32_t flag:1;
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//1=disable ac_off
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uint32_t dis:1;
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uint32_t reserved_31_2:30;
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} REG_vd_ac_off_bitfiled_TypeDef;
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typedef struct
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{
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union {
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__IO REG_vd_ac_off_bitfiled_TypeDef bf;//bitfiled
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__IO uint32_t word;
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};
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} REG_vd_ac_off_TypeDef;
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typedef struct
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{
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//vd reset counter select
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//0: 10ms counter overflow
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//1:100ms counter overflow
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uint32_t cnt_sel:1;
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//1'b1:vd rst counter 10ms/100ms flag or soft rst ,canbe write 1 clr by mcu
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uint32_t flag:1;
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//0:soft rst disable ; 1'b1:vd soft rst
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uint32_t soft:1;
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uint32_t reserved_31_3:29;
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} REG_vd_rst_bitfiled_TypeDef;
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typedef struct
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{
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union {
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__IO REG_vd_rst_bitfiled_TypeDef bf;//bitfiled
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__IO uint32_t word;
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};
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} REG_vd_rst_TypeDef;
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typedef struct
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{
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//2'b11:ring comparator enbale delay 750ns after vd < vth_sh
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//2'b10:ring comparator enbale delay 500ns after vd < vth_sh
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//2'b01:ring comparator enbale delay 250ns after vd < vth_sh
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//2'b00: disable delay
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uint32_t tdring_sel:2;
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uint32_t reserved_31_2:30;
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} REG_vd_cfg_bitfiled_TypeDef;
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typedef struct
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{
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union {
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__IO REG_vd_cfg_bitfiled_TypeDef bf;//bitfiled
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__IO uint32_t word;
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};
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} REG_vd_cfg_TypeDef;
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//-----------------------------------------------------------------------------
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// memory map
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#define REG_VD_LS_COMP_BASE 0x4000E800
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#define REG_VD_LS_BASE 0x4000E804
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#define REG_VD_DBG_BASE 0x4000E808
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#define REG_VD_AC_OFF_BASE 0x4000E810
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#define REG_VD_RST_BASE 0x4000E814
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#define REG_VD_CFG_BASE 0x4000E818
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//-----------------------------------------------------------------------------
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// declaration
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#define REG_VD_LS_COMP ((REG_vd_ls_comp_TypeDef *) REG_VD_LS_COMP_BASE )
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#define REG_VD_LS ((REG_vd_ls_TypeDef *) REG_VD_LS_BASE )
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#define REG_VD_DBG ((REG_vd_dbg_TypeDef *) REG_VD_DBG_BASE )
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#define REG_VD_AC_OFF ((REG_vd_ac_off_TypeDef *) REG_VD_AC_OFF_BASE )
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#define REG_VD_RST ((REG_vd_rst_TypeDef *) REG_VD_RST_BASE )
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#define REG_VD_CFG ((REG_vd_cfg_TypeDef *) REG_VD_CFG_BASE )
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//-----------------------------------------------------------------------------
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// set
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#define REG_VD_LS_BLANK_TIME_POS 0
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#define REG_VD_LS_BLANK_TIME_MSK (0x3Ful << REG_VD_LS_BLANK_TIME_POS)
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#define REG_VD_LS_BLANK_TIME_SET(num) (((num) << REG_VD_LS_BLANK_TIME_POS ) & REG_VD_LS_BLANK_TIME_MSK)
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#define REG_VD_DBG_SEL_POS 0
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#define REG_VD_DBG_SEL_MSK (0x3ul << REG_VD_DBG_SEL_POS)
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#define REG_VD_DBG_SEL_SET(num) (((num) << REG_VD_DBG_SEL_POS ) & REG_VD_DBG_SEL_MSK)
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#define REG_VD_AC_OFF_DIS_POS 1
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#define REG_VD_AC_OFF_DIS_MSK (0x1ul << REG_VD_AC_OFF_DIS_POS)
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#define REG_VD_AC_OFF_DIS_SET(num) (((num) << REG_VD_AC_OFF_DIS_POS ) & REG_VD_AC_OFF_DIS_MSK)
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#define REG_VD_RST_CNT_SEL_POS 0
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#define REG_VD_RST_CNT_SEL_MSK (0x1ul << REG_VD_RST_CNT_SEL_POS)
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#define REG_VD_RST_CNT_SEL_SET(num) (((num) << REG_VD_RST_CNT_SEL_POS ) & REG_VD_RST_CNT_SEL_MSK)
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#define REG_VD_RST_SOFT_POS 2
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#define REG_VD_RST_SOFT_MSK (0x1ul << REG_VD_RST_SOFT_POS)
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#define REG_VD_RST_SOFT_SET(num) (((num) << REG_VD_RST_SOFT_POS ) & REG_VD_RST_SOFT_MSK)
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#define REG_VD_CFG_TDRING_SEL_POS 0
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#define REG_VD_CFG_TDRING_SEL_MSK (0x3ul << REG_VD_CFG_TDRING_SEL_POS)
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#define REG_VD_CFG_TDRING_SEL_SET(num) (((num) << REG_VD_CFG_TDRING_SEL_POS ) & REG_VD_CFG_TDRING_SEL_MSK)
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#endif /*__VD_DEFINE_H__*/
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