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413 lines
9.9 KiB
413 lines
9.9 KiB
/**
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******************************************************************************
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* @copyright Copyright (C), 2016-2022, ConvenientPower. Co., Ltd.
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* @file drv_clock.h
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* @version 1.0
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* @author qing.cheng
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* @date 2023-03-09
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* @brief Header file of DRV_CLOCK_H module.
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******************************************************************************
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*/
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#ifndef DRV_CLOCK_H
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#define DRV_CLOCK_H
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#include "cmsdk_cm0.h"
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#include "core_comm.h"
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#include "stdbool.h"
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#include "stdlib.h"
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#include "string.h"
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#include "clkctrl_define.h"
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#include "sysctrl_define.h"
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#define SYSTEM_CLOCK_CONFIG (24000000)
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#define SYSTEM_6M (6000000)
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#define SYSTEM_12M (12000000)
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#define SYSTEM_24M (24000000)
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#define DELAY_CLOCK_24M (24)
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#define DELAY_CLOCK_12M (12)
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#define DELAY_CLOCK_6M (6)
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/*SYS_CTRL*/
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#define SYS_CTRL_MCLK_SEL_24_6M BIT_SET(0)
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#define SYS_CTRL_GREEN_MODE BIT_SET(1)
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#define SYS_CTRL_SLEEP_MODE BIT_SET(2)
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#define SYS_CTRL_MASK_VIN_OV BIT_SET(3)
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#define SYS_CTRL_MASK_VIN_UV BIT_SET(4)
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#define SYS_CTRL_MASK_VIN1_OV BIT_SET(5)
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#define SYS_CTRL_MASK_VIN1_UV BIT_SET(6)
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#define SYS_CTRL_MASK_VIN2_OV BIT_SET(7)
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#define SYS_CTRL_MASK_VIN2_UV BIT_SET(8)
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#define SYS_CTRL_MASK_VBUS1_OCP BIT_SET(9)
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#define SYS_CTRL_MASK_VBUS2_OCP BIT_SET(10)
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#define SYS_CTRL_MASK_GATE1_UV BIT_SET(11)
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#define SYS_CTRL_MASK_GATE2_UV BIT_SET(12)
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#define SYS_CTRL_MASK_GATE3_UV BIT_SET(13)
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#define SYS_CTRL_MASK_V2_OCP BIT_SET(14)
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#define SYS_CTRL_MASK_I2C1 BIT_SET(15)
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#define SYS_CTRL_MASK_I2C2 BIT_SET(16)
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#define SYS_CTRL_MASK_CS1 BIT_SET(17)
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#define SYS_CTRL_MASK_CS2 BIT_SET(18)
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#define SYS_CTRL_MASK_PD1_CC_COMP_ENTRY BIT_SET(19)
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#define SYS_CTRL_MASK_PD1_CC_COMP_EXIT BIT_SET(20)
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#define SYS_CTRL_MASK_PD1_BMC BIT_SET(21)
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#define SYS_CTRL_MASK_DPDN1_OP4V BIT_SET(22)
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#define SYS_CTRL_MASK_DPDN1_2P0V BIT_SET(23)
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#define SYS_CTRL_MASK_DPDN1_1P2V BIT_SET(24)
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#define SYS_CTRL_MASK_DPDN_OV BIT_SET(25)
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#define SYS_CTRL_MASK_PD1_CCX_OV BIT_SET(26)
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#define SYS_CTRL_MASK_PD1_VCON_OC BIT_SET(27)
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#define SYS_CTRL_MASK_PD1_CCX_STATUS BIT_SET(28)
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#define SYS_CTRL_TRIM_MCU_START_DIS BIT_SET(29)
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#define SYS_CTRL_TRIM_TRIM_START_DIS BIT_SET(30)
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#define SYS_CTRL_TRIM_DIS BIT_SET(31)
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/*PERI_CG*/
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#define PERI_TIMER0_EN BIT_SET(0)
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#define PERI_TIMER1_EN BIT_SET(1)
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#define PERI_TIMER2_EN BIT_SET(2)
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#define PERI_UART1_EN BIT_SET(3)
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#define PERI_UART2_EN BIT_SET(4)
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#define PERI_ADC_EN BIT_SET(5)
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#define PERI_DAC_CTR_EN BIT_SET(6)
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#define PERI_I2C_MASTER0_EN BIT_SET(7)
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#define PERI_I2C_MASTER1_EN BIT_SET(8)
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#define PERI_VD_EN BIT_SET(9)
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#define PERI_PWD0_EN BIT_SET(10)
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#define PERI_PWD1_EN BIT_SET(11)
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#define PERI_PWD2_EN BIT_SET(12)
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#define PERI_PWD3_EN BIT_SET(13)
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#define PERI_PD0H_EN BIT_SET(14)
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#define PERI_PD1H_EN BIT_SET(15)
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#define PERI_PD0L_EN BIT_SET(16)
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#define PERI_PD1L_EN BIT_SET(17)
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#define PERI_UFCS0_EN BIT_SET(18)
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#define PERI_UFCS1_EN BIT_SET(19)
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#define PERI_SCP0_EN BIT_SET(20)
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#define PERI_SCP1_EN BIT_SET(21)
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#define PERI_WDOG_EN BIT_SET(22)
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#define PERI_VIN_DIS_EN BIT_SET(23)
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/*sys_rstreg*/
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#define SYS_RSTREQ_MCU BIT_SET(0)
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#define SYS_RSTREQ_APB BIT_SET(8)
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#define SYS_RSTREQ_MCU_HOLD BIT_SET(16)
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#define SYS_RSTREQ_SYSTEM BIT_SET(24)
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#define SYS_PASSWORD 0x9A6E
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typedef enum SYS_MCLK_SEL_e
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{
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MCLK_SEL_24M = 0,
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MCLK_SEL_6M,
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} SYS_MCLK_SEL_e;
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typedef
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enum drv_gpio_pimux_e
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{
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PINMUX_GPIO_PIN0 = 0,
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PINMUX_GPIO_PIN1,
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PINMUX_GPIO_PIN2,
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PINMUX_GPIO_PIN3,
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PINMUX_GPIO_PIN4,
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PINMUX_GPIO_PIN5,
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PINMUX_GPIO_CC1_1,
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PINMUX_GPIO_CC2_1,
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PINMUX_GPIO_CC1_2,
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PINMUX_GPIO_CC2_2,
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PINMUX_GPIO_FB1,
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PINMUX_GPIO_COMP1,
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PINMUX_GPIO_FB2,
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PINMUX_GPIO_COMP2,
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PINMUX_GPIO_VFB,
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PINMUX_GPIO_IFB,
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PINMUX_PIN_MAX,
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} drv_gpio_pimux_e;
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/*
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* @brief drv_clkctrl_sys_ctrl_config
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* @param config
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* @note word used to strl sysclock , mcu sleep ,wake
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* @retval
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*/
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__forceinline void drv_clkctrl_sys_ctrl_config(uint32_t config)
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{
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REG_CLKCTRL_SYS_CTRL->word = config;
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}
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/*
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* @brief drv_clkctrl_sys_ctrl_mask_clr
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* @param config
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* @note null
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* @retval null
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*/
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__forceinline void drv_clkctrl_sys_ctrl_mask_clr(uint32_t clr)
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{
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REG_CLKCTRL_SYS_CTRL->word &= ~(clr);
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}
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/*
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* @brief drv_clkctrl_sys_ctrl_mask_set
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* @param value
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* @note null
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* @retval null
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*/
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__forceinline void drv_clkctrl_sys_ctrl_mask_set(uint32_t value)
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{
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REG_CLKCTRL_SYS_CTRL->word |= value;
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}
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/*
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* @brief drv_clkctrl_sys_ctrl_config
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* @param mclk_sel ��0:24M MCLK,1:6M MCLK��
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* @note
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* @retval
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*/
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__forceinline void drv_clkctrl_sys_ctrl_mclk_set(uint8_t mclk_sel)
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{
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REG_CLKCTRL_SYS_CTRL->bf.mclk_sel = mclk_sel;
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}
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/*
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* @brief drv_clkctrl_sys_ctrl_mclk_get
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* @param null
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* @note
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* @retval 24M/6M
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*/
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__forceinline uint32_t drv_clkctrl_sys_ctrl_mclk_get(void)
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{
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uint32_t sysclk_buf[2] = {SYSTEM_24M, SYSTEM_6M};
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return sysclk_buf[REG_CLKCTRL_SYS_CTRL->bf.mclk_sel];
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}
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/*
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* @brief drv_clkctrl_peri_cg_en
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* @param value
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* @note null
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* @retval null
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*/
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__forceinline void drv_clkctrl_peri_cg_en(uint32_t value)
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{
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REG_CLKCTRL_PERI_CG->word = value;
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}
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/*
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* @brief drv_clkctrl_peri_cg_mask_clr
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* @param clr
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* @note null
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* @retval null
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*/
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__forceinline void drv_clkctrl_peri_cg_mask_clr(uint32_t clr)
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{
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REG_CLKCTRL_PERI_CG->word &= ~(clr);
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}
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/*
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* @brief drv_clkctrl_peri_cg_mask_set
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* @param value
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* @note null
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* @retval null
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*/
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__forceinline void drv_clkctrl_peri_cg_mask_set(uint32_t value)
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{
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REG_CLKCTRL_PERI_CG->word |= value;
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}
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/*
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* @brief drv_clkctrl_sys_streq
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* @param value
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* @note null
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* @retval null
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*/
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__forceinline void drv_clkctrl_sys_streq(uint32_t value)
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{
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REG_CLKCTRL_PERI_CG->word = value;
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}
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/*
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* @brief drv_clkctrl_pin_mul_set
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* @param pin_mode
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* @note null
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* @retval null
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*/
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__forceinline void drv_clkctrl_pin_mul_set(uint32_t pin_mode)
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{
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REG_CLKCTRL_PIN_MUL_SET->word = pin_mode;
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}
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/*
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* @brief drv_clkctrl_pin_mul_mask_clr
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* @param pin
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* @param pin_clr
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* @note null
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* @retval null
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*/
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__forceinline void drv_clkctrl_pin_mul_mask_clr(uint8_t pin, uint8_t pin_clr)
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{
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REG_CLKCTRL_PIN_MUL_SET->word &= ~(pin_clr << (pin << 1));
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}
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/*
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* @brief drv_clkctrl_pin_mul_mask_set
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* @param pin
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* @param pin_mode
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* @note null
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* @retval null
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*/
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__forceinline void drv_clkctrl_pin_mul_mask_set(uint8_t pin, uint8_t pin_mode)
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{
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REG_CLKCTRL_PIN_MUL_SET->word |= (pin_mode << (pin << 1));
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}
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/*
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* @brief drv_clkctrl_mem_config
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* @param word
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* @note null
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* @retval null
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*/
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__forceinline void drv_clkctrl_mem_config(uint32_t word)
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{
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REG_CLKCTRL_MEM->word = word;
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}
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/*
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* @brief drv_clkctrl_mem_read
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* @param word
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* @note null
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* @retval null
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*/
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__forceinline uint8_t drv_clkctrl_mem_read(void)
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{
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return (REG_CLKCTRL_MEM->word & 0xff);;
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}
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/*
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* @brief drv_clkctrl_dtest_config
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* @param word
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* @note null
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* @retval null
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*/
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__forceinline void drv_clkctrl_dtest_config(uint32_t word)
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{
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REG_CLKCTRL_DTEST->word = word;
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}
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/*
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* @brief drv_clkctrl_mbist_config
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* @param word
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* @note null
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* @retval null
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*/
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__forceinline void drv_clkctrl_mbist_config(uint32_t word)
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{
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REG_CLKCTRL_MBIST->word = word;
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}
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/*
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* @brief drv_clkctrl_password ��pw_hit��
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* @param null
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* @note null
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* @retval null
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*/
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__forceinline void drv_clkctrl_password(void)
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{
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REG_CLKCTRL_CLKCTRL->word = SYS_PASSWORD;
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}
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/*
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* @brief drv_clkctrl_filter
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* @param filter_value
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* @note null
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* @retval null
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*/
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__forceinline void drv_clkctrl_filter1(uint32_t filter_value)
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{
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REG_CLKCTRL_FILTER->word = filter_value;
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}
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/*
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* @brief drv_baudrate_vld_skew
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* @param value
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* @note fcs/vfcp train baud rate valid range config based on 115200 bps.
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standard 115200 is 104cycle in 12MHz, config this reg to set the valid range x=104 +/- vlld_skew.
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57600 range = x*2, 38400 range=x*3, 19200 range=x*6.
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* @retval null
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*/
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__forceinline void drv_baudrate_vld_skew(uint8_t value)
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{
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REG_CLKCTRL_BAUDRATE->word = value;
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}
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/*******add 8860*****/
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/*
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* @brief drv_pin_mul_set1_mask_clr
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* @param clr
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* @note null
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* @retval null
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*/
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__forceinline void drv_pin_mul_set1_mask_clr(uint32_t clr)
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{
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REG_CLKCTRL_PIN_MUL_SET1->word &= ~(clr);
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}
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/*
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* @brief drv_pin_mul_set1_mask_set
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* @param value
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* @note null
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* @retval null
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*/
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__forceinline void drv_pin_mul_set1_mask_set(uint32_t value)
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{
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REG_CLKCTRL_PIN_MUL_SET1->word |= value;
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}
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/*
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* @brief drv_sys_stat_read
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* @param word
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* @note null
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* @retval null
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*/
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__forceinline uint8_t drv_sys_stat_read(void)
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{
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return (REG_CLKCTRL_SYS_STAT->word & 0x01);
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}
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/*
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* @brief drv_mcu_start_flag_read
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* @param word
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* @note null
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* @retval null
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*/
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__forceinline uint32_t drv_mcu_start_flag_read(uint32_t word)
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{
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return (REG_CLKCTRL_MCU_START_FLAG->word & 0x01);
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}
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/*
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* @brief drv_trim_start_flag_read
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* @param word
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* @note null
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* @retval null
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*/
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__forceinline uint32_t drv_trim_start_flag_read(uint32_t word)
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{
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return (REG_CLKCTRL_TRIM_START_FLAG->word & 0x01);
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}
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#endif
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