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445 lines
9.9 KiB
445 lines
9.9 KiB
/**
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******************************************************************************
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* @copyright Copyright (C), 2016-2022, ConvenientPower. Co., Ltd.
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* @file drv_i2c.h
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* @version 1.0
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* @author qing.cheng
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* @date 2022-11-08
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* @brief Header file of DRV_I2C_H module.
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******************************************************************************
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*/
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#ifndef _DRV_I2C_H_
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#define _DRV_I2C_H_
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#include "core_comm.h"
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#include "i2c_master_define.h"
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#include "i2c1_master_define.h"
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#include "clkctrl_define.h"
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#include "extint_define.h"
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#include "analog_define.h"
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#include "drv_clock.h"
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#include "stdbool.h"
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#if 1
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#define T_MEXT 5 /* ms */
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#define T_SEXT 25 /* ms */
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#define T_TIMEOUT 35 /* ms */
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#define MS_TO_SMBUS_T(ms) ((ms) * (drv_clkctrl_sys_ctrl_mclk_get() / 1000) / 1024)
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#define I2C_DELAY 1
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#define I2C_WR 0x0
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#define I2C_RD 0x1
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/******************i2c0*******************/
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#define I2C0_I2STAT (REG_I2C_MASTER_I2CSTA->word & 0xF8)
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#define I2C0_I2STAT_RST (REG_I2C_MASTER_I2CSTA->word = 0xF8)
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#define I2C0_SET_AA (REG_I2C_MASTER_I2CCON->bf.aa = 1)
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#define I2C0_CLR_AA (REG_I2C_MASTER_I2CCON->bf.aa = 0)
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#define I2C0_SI (REG_I2C_MASTER_I2CCON->bf.si)
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#define I2C0_CLR_SI (REG_I2C_MASTER_I2CCON->bf.si = 0)
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#define I2C0_STO (REG_I2C_MASTER_I2CCON->bf.sto)
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#define I2C0_SET_STO (REG_I2C_MASTER_I2CCON->bf.sto = 1)
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#define I2C0_CLR_STO (REG_I2C_MASTER_I2CCON->bf.sto = 0)
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#define I2C0_SET_STA (REG_I2C_MASTER_I2CCON->bf.sta = 1)
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#define I2C0_CLR_STA (REG_I2C_MASTER_I2CCON->bf.sta = 0)
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#define I2C0_SET_I2CEN (REG_I2C_MASTER_I2CCON->bf.ens1 = 1)
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#define I2C0_CLR_I2CEN (REG_I2C_MASTER_I2CCON->bf.ens1 = 0)
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#define I2C0_I2DAT (REG_I2C_MASTER_I2CDAT->word)
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/****************i2c1***********************/
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#define I2C1_I2STAT (REG_I2C1_MASTER_I2CSTA->word & 0xF8)
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#define I2C1_I2STAT_RST (REG_I2C1_MASTER_I2CSTA->word = 0xF8)
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#define I2C1_SET_AA (REG_I2C1_MASTER_I2CCON->bf.aa = 1)
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#define I2C1_CLR_AA (REG_I2C1_MASTER_I2CCON->bf.aa = 0)
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#define I2C1_SI (REG_I2C1_MASTER_I2CCON->bf.si)
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#define I2C1_CLR_SI (REG_I2C1_MASTER_I2CCON->bf.si = 0)
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#define I2C1_STO (REG_I2C1_MASTER_I2CCON->bf.sto)
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#define I2C1_SET_STO (REG_I2C1_MASTER_I2CCON->bf.sto = 1)
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#define I2C1_CLR_STO (REG_I2C1_MASTER_I2CCON->bf.sto = 0)
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#define I2C1_SET_STA (REG_I2C1_MASTER_I2CCON->bf.sta = 1)
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#define I2C1_CLR_STA (REG_I2C1_MASTER_I2CCON->bf.sta = 0)
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#define I2C1_SET_I2CEN (REG_I2C1_MASTER_I2CCON->bf.ens1 = 1)
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#define I2C1_CLR_I2CEN (REG_I2C1_MASTER_I2CCON->bf.ens1 = 0)
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#define I2C1_I2DAT (REG_I2C1_MASTER_I2CDAT->word)
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#define I2C_STA_SLV_RX_ADDR_W_ACK 0x60
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#define I2C_STA_SLV_RX_DATA_ACK 0x80
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#define I2C_STA_SLV_RX_DATA_NACK 0x88
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#define I2C_STA_SLV_RX_STO_RSTA 0xA0
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#define I2C_STA_SLV_TX_ADDR_R_ACK 0xA8
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#define I2C_STA_SLV_TX_DATA_ACK 0xB8
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#define I2C_STA_SLV_TX_DATA_NACK 0xC0
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#define I2C_STA_SLV_TX_LAST_DATA_ACK 0xC8
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#define I2C_STA_MISC_BUS_ERR 0x00
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#define I2C_STA_TO 0x07
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#define REG_I2C0_I2CCON_ACK_NEXT (REG_I2C_MASTER_I2CCON_ENS1_MSK | REG_I2C_MASTER_I2CCON_AA_MSK)
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#define REG_I2C0_I2CCON_NACK_NEXT (REG_I2C_MASTER_I2CCON_ENS1_MSK)
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#define REG_I2C1_I2CCON_ACK_NEXT (REG_I2C1_MASTER_I2CCON_ENS1_MSK | REG_I2C1_MASTER_I2CCON_AA_MSK)
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#define REG_I2C1_I2CCON_NACK_NEXT (REG_I2C1_MASTER_I2CCON_ENS1_MSK)
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#define I2C_MASTER_I2CCON_STO_MSK (0x1 << 4)
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#define I2C_SLAVE_R 0x01
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#define I2C_SLAVE_W 0x02
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typedef struct
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{
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uint8_t reg_data;//[TRANSMIT_BUF_SIZE];
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uint32_t wr_addr;
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uint8_t receive;//[RECEIVE_BUF_SIZE];
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/*
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* Private variables. They should never be accessed by i2c master.
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*/
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} __attribute__((packed)) s_ap_regs;
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#define AP_REG_FUNC(_name, _func) \
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{ ((uint32_t)(&(((s_ap_regs *)0)->_name)) + sizeof(((s_ap_regs *)0)->_name)), (_func) }
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#define ARRAY_LEN(x) (sizeof(x) / sizeof((x)[0]))
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#define TRANSMIT_BUF_SIZE 4
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#define RECEIVE_BUF_SIZE 4
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typedef void(*i2c_drv_rw_cb)(uint8_t rw, uint8_t i2c_num);
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typedef struct i2c_slave_msg_s
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{
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uint8_t *rx_buf;
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uint8_t *tx_buf;
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uint8_t *tx;
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uint8_t *tx_end;
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uint16_t rx_len;
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uint16_t tx_len;
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uint16_t rx_buf_size;
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uint16_t tx_buf_size;
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i2c_drv_rw_cb cb;
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void(*tx_end_cb)(uint8_t i2c_num);
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uint8_t slave_addr;
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uint8_t i2c_num;
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s_ap_regs ap_regs;
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} i2c_slave_msg_s;
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struct ap_reg_func_entry
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{
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uint8_t addr; /* Next address */
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void (*func)(i2c_slave_msg_s *);
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};
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typedef enum
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{
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DRV_I2C_FREQ_5K,
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DRV_I2C_FREQ_10K,
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DRV_I2C_FREQ_20K,
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DRV_I2C_FREQ_50K,
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DRV_I2C_FREQ_100K,
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DRV_I2C_FREQ_150K,
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DRV_I2C_FREQ_300K,
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DRV_I2C_FREQ_500K,
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DRV_I2C_FREQ_NUM,
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} drv_i2c_freq_e;
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typedef enum
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{
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I2C_BW_8BIT = 1,
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I2C_BW_16BIT = 2,
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I2C_BW_32BIT = 4,
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I2C_BW_MAX
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} i2c_bw_e;
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typedef enum
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{
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DRV_I2C0_NUM0 = 0,
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DRV_I2C0_NUM1,
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DRV_I2C0_NUM2,
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DRV_I2C0_NUM3,
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} drv_i2c0_num_e;
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typedef enum
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{
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DRV_I2C1_NUM0 = 0,
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DRV_I2C1_NUM1,
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DRV_I2C1_NUM2,
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} drv_i2c1_num_e;
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void delay_us(int32_t us);
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/*
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* @brief drv_i2c_i2csta_get
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* @param i2c_num
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* @note
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* @retval i2c stat
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*/
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uint8_t drv_i2c_i2csta_get(uint8_t i2c_num);
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/*
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* @brief drv_i2c_i2ccon_set_aa
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* @param i2c_num
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* @note
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* @retval i2c stat
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*/
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void drv_i2c_i2ccon_set_aa(uint8_t i2c_num, bool enable);
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/*
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* @brief drv_i2c_i2ccon_si_get
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* @param i2c_num
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* @note
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* @retval i2ccon si state
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*/
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uint8_t drv_i2c_i2ccon_si_get(uint8_t i2c_num);
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/*
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* @brief drv_i2c_i2ccon_clr_si
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* @param i2c_num
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* @note
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* @retval i2ccon si state
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*/
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void drv_i2c_i2ccon_clr_si(uint8_t i2c_num);
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/*
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* @brief drv_i2c_i2ccon_sto_get
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* @param i2c_num
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* @note
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* @retval i2ccon si state
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*/
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uint8_t drv_i2c_i2ccon_sto_get(uint8_t i2c_num);
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/*
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* @brief drv_i2c_i2ccon_stop_set
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* @param i2c_num
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* @param enable
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* @note
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* @retval i2ccon si state
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*/
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void drv_i2c_i2ccon_stop_set(uint8_t i2c_num, bool enable);
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/*
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* @brief drv_i2c_i2ccon_start_set
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* @param i2c_num
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* @param enable
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* @note
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* @retval i2ccon si state
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*/
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void drv_i2c_i2ccon_start_set(uint8_t i2c_num, bool enable);
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/*
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* @brief drv_i2c_i2ccon_start_set
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* @param i2c_num
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* @param enable
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* @note
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* @retval i2ccon si state
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*/
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void drv_i2c_i2ccon_ens1_set(uint8_t i2c_num, bool enable);
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/*
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* @brief drv_i2c_data_get
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* @param i2c_num
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* @note
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* @retval i2ccon si state
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*/
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uint8_t drv_i2c_data_get(uint8_t i2c_num);
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/*
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* @brief drv_i2c_data_set
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* @param i2c_num
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* @note
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* @retval i2ccon si state
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*/
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void drv_i2c_data_set(uint8_t i2c_num, uint8_t i2c_data);
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/*
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* @brief drv_i2c_i2cadr_set
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* @param i2c_num
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* @param i2c_addr
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* @note
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* @retval i2ccon si state
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*/
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void drv_i2c_i2cadr_set(uint8_t i2c_num, uint8_t i2c_addr);
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/*
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* @brief drv_i2c_data_get
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* @param i2c_num
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* @note
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* @retval i2ccon si state
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*/
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uint8_t drv_i2c_i2cadr_get(uint8_t i2c_num);
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/*
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* @brief drv_i2c_i2ccon_ack_next_get
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* @param i2c_num
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* @note
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* @retval i2ccon si state
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*/
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uint8_t drv_i2c_i2ccon_ack_next_get(uint8_t i2c_num);
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/*
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* @brief drv_i2c_i2con_nack_next_get
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* @param i2c_num
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* @note
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* @retval i2ccon si state
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*/
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uint8_t drv_i2c_i2con_nack_next_get(uint8_t i2c_num);
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/*
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* @brief drv_i2c_i2cdat_write
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* @param i2c_num
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* @param data
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* @note
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* @retval null
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*/
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void drv_i2c_i2cdat_write(uint8_t i2c_num, uint8_t data);
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/*
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* @brief drv_i2c_i2cdat_read
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* @param i2c_num
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* @note
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* @retval null
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*/
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uint8_t drv_i2c_i2cdat_read(uint8_t i2c_num);
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/*
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* @brief drv_analog_prot_word
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* @param word
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* @note
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* @retval null
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*/
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void drv_i2c_i2ccon_word(uint8_t i2c_num, uint8_t value);
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/*
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* @brief drv_i2c_i2ccon_clr
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* @param i2c_num
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* @param clr
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* @note
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* @retval null
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*/
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void drv_i2c_i2ccon_clr(uint8_t i2c_num, uint8_t clr);
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/*
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* @brief drv_i2c_i2ccon_mask_set
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* @param i2c_num
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* @param value
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* @note
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* @retval null
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*/
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void drv_i2c_i2ccon_mask_set(uint8_t i2c_num, uint8_t value);
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/*
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* @brief drv_i2c_i2ccon_read
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* @param i2c_num
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* @note
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* @retval i2c con value
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*/
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uint8_t drv_i2c_i2ccon_read(uint8_t i2c_num);
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/*
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* @brief drv_i2c_i2csta_read
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* @param i2c_num
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* @note
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* @retval i2c sta value
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*/
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uint8_t drv_i2c_i2csta_read(uint8_t i2c_num);
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/*
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* @brief drv_i2c_int_clr
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* @param i2c_num
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* @note
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* @retval NULL
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*/
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void drv_i2c_int_clr(uint8_t i2c_num);
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/*
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* @brief drv_i2c_set_freq
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* @param i2c_num
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* @param freq
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* @note
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* @retval null
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*/
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void drv_i2c_set_freq(uint8_t i2c_num, drv_i2c_freq_e freq);
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/*
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* @brief drv_i2c_init_smbus_timeout
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* @param i2c_num
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* @note
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* @retval null
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*/
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void drv_i2c_init_smbus_timeout(uint8_t i2c_num);
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/*
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* @brief drv_i2c_master_init
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* @param i2c_num
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* @param i2c_scl_num
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* @param i2c_sda_num
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* @param freq
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* @note
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* @retval null
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*/
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void drv_i2c_master_init(uint8_t i2c_num, uint8_t i2c_scl_num, uint8_t i2c_sda_num, drv_i2c_freq_e freq);
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/*
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* @brief drv_i2c_slave_init
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* @param i2c_num
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* @param i2c_scl_num
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* @param i2c_sda_num
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* @param freq
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* @note
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* @retval null
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*/
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void drv_i2c_slave_init(uint8_t i2c_num, uint8_t i2c_scl_num, uint8_t i2c_sda_num, uint8_t slave_addr);
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/*
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* @brief drv_i2c_read_byte
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* @param i2c_num
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* @param Slave_addr
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* @param reg_addr
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* @param bw
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* @param *u8DAT
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* @param data_len
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* @note
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* @retval null
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*/
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bool drv_i2c_read_byte(uint8_t i2c_num, uint8_t Slave_addr, uint32_t reg_addr, i2c_bw_e bw, uint8_t *u8DAT, uint8_t data_len);
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/*
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* @brief i2c_write_byte
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* @param i2c_num
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* @param Slave_addr
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* @param reg_addr
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* @param bw
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* @param *u8DAT
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* @param data_len
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* @note
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* @retval null
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*/
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bool drv_i2c_write_byte(uint8_t i2c_num, uint8_t Slave_addr, uint32_t reg_addr, i2c_bw_e bw, uint8_t *u8DAT, uint8_t data_len);
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/*
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* @brief drv_i2c_pin_set
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* @param i2c_num
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* @param i2c_scl_num
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* @param i2c_sda_num
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* @note
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* @retval null
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*/
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void drv_i2c_pin_set(uint8_t i2c_num, uint8_t i2c_scl_num, uint8_t i2c_sda_num);
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/*
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* @brief i2c_handler
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* @param i2c_slave
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* @note
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* @retval null
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*/
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void i2c_handler(i2c_slave_msg_s *i2c_slave);
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#endif
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#endif
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