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512 lines
9.0 KiB
512 lines
9.0 KiB
/**
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******************************************************************************
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* @copyright Copyright (C), 2016-2022, ConvenientPower. Co., Ltd.
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* @file ufcs_phy.h
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* @version 1.0
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* @author qing.cheng
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* @date 2022-12-02
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* @brief Header file of UFCS_PHY_H module.
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******************************************************************************
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*/
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#ifndef __UFCS_PHY_H__
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#define __UFCS_PHY_H__
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#include "drv_comm.h"
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#include "comp_dma.h"
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#include "comp_config.h"
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#include "ufcs_app.h"
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//#define UFCS_FIFO_MAXLEN 16
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#define UFCS_DPDN_FUNC 1
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#define UFCS_GPIO_FUNC 3
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#define DP1_PIN 2
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#define DN1_PIN 3
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#define DP2_PIN 4
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#define DN2_PIN 5
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typedef enum
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{
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UFCS_BAUD_RATE_115200 = 0,
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UFCS_BAUD_RATE_57600,
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UFCS_BAUD_RATE_38400,
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UFCS_BAUD_RATE_MAX
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} ufcs_baud_rate_e;
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/*
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* @brief ufcs_dn_level_low
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* @param port
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* @note null
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* @retval 1: dn <0.6V
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*/
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#define ufcs_dn_level_low(port) \
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drv_dpdn_dn_comp_0p6v_get(port)
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/*
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* @brief ufcs_phy_ctrl_tx_enable
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* @param port
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* @param en
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* @note null
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* @retval null
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*/
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__forceinline void ufcs_phy_ctrl_tx_enable(uint8_t port, bool en)
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{
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if(port == 0)
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{
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drv_ufcs0_ctrl_tx_enable(en);
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}
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else
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{
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drv_ufcs1_ctrl_tx_enable(en);
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}
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}
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/*
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* @brief ufcs_phy_ctrl_rx_enable
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* @param port
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* @param en
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* @note null
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* @retval null
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*/
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__forceinline void ufcs_phy_ctrl_rx_enable(uint8_t port, bool en)
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{
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if(port == 0)
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{
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drv_ufcs0_ctrl_rx_enable(en);
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}
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else
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{
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drv_ufcs1_ctrl_rx_enable(en);
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}
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}
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/*
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* @brief ufcs_phy_ctrl_rx_stop_en
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* @param port
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* @param en 1: hw clear rx_enable at the time of rxpkt_end, software set rx_enable; 0: sw control rx_enable directly
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* @note null
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* @retval null
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*/
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__forceinline void ufcs_phy_ctrl_rx_stop_en(uint8_t port, bool en)
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{
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if(port == 0)
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{
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drv_ufcs0_ctrl_rx_stop_en(en);
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}
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else
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{
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drv_ufcs1_ctrl_rx_stop_en(en);
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}
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}
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/*
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* @brief ufcs_phy_ctrl_hw_reset_cable
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* @param port
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* @param en 1: send cable hardware reset command, only valid when the "txpkt_end" is high level, set by software, clear by hw;
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* @note null
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* @retval null
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*/
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__forceinline void ufcs_phy_ctrl_hw_reset_cable(uint8_t port, bool en)
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{
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if(port == 0)
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{
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drv_ufcs0_ctrl_hw_reset_cable(en);
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}
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else
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{
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drv_ufcs1_ctrl_hw_reset_cable(en);
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}
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}
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/*
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* @brief ufcs_phy_ctrl_hw_reset_snk
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* @param port
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* @param en 1: send sink hardware reset command, only valid when the "txpkt_end" is high level, if tx packet not end status, miss this command
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* @note null
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* @retval null
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*/
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__forceinline void ufcs_phy_ctrl_hw_reset_tx(uint8_t port, bool en)
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{
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if(port == 0)
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{
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drv_ufcs0_ctrl_hw_reset_tx(en);
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}
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else
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{
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drv_ufcs1_ctrl_hw_reset_tx(en);
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}
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}
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/*
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* @brief ufcs_phy_reset_logic
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* @param port
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* @note null
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* @retval null
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*/
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__forceinline void ufcs_phy_reset_logic(uint8_t port)
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{
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if(port == 0)
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{
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drv_ufcs0_reset_logic();
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}
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else
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{
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drv_ufcs1_reset_logic();
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}
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}
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/*
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* @brief ufcs_phy_reset_all
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* @param port
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* @note null
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* @retval null
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*/
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__forceinline void ufcs_phy_reset_all(uint8_t port)
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{
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if(port == 0)
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{
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drv_ufcs0_reset_all();
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}
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else
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{
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drv_ufcs1_reset_all();
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}
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}
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/*
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* @brief ufcs_phy_reset_all
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* @param port
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* borate_num://0:115200 1:57600 2:38400 3:19200
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* @note null
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* @retval null
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*/
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__forceinline void ufcs_phy_bdrate_tx_set(uint8_t port, uint16_t borate_num)
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{
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if(port == 0)
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{
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drv_ufcs0_bdrate_tx(borate_num);
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}
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else
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{
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drv_ufcs1_bdrate_tx(borate_num);
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}
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}
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/*
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* @brief ufcs_phy_reset_all
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* @param port
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* @note null
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* @retval borate_num
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*/
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__forceinline uint16_t ufcs_phy_bdrate_rx_get(uint8_t port)
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{
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if(port == 0)
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{
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return drv_ufcs0_bdrate_rx();
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}
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else
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{
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return drv_ufcs1_bdrate_rx();
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}
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}
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/*
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* @brief ufcs_phy_reset_all
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* @param port
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* borate_num:0: 115200; 1:57600; 2:38400; 3: 19200bps
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* @note null
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* @retval null
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*/
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__forceinline void ufcs_phy_txpkt_len(uint8_t port, uint16_t len)
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{
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if(port == 0)
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{
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drv_ufcs0_txpkt_len(len);
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}
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else
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{
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drv_ufcs1_txpkt_len(len);
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}
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}
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//usb_dn pulse counter enable
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/*
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* @brief ufcs_dn_val_get
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* @param port
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* @note null
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* @retval data32 val
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*/
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__forceinline uint32_t ufcs_dn_val_get(uint8_t port)
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{
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if(port == 0)
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{
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return drv_ufcs0_get_pwd1_val();
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}
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else
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{
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return drv_ufcs1_get_pwd3_val();
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}
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}
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/*
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* @brief ufcs_dn_val_get
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* @param port
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* @note null
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* @retval null
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*/
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__forceinline uint8_t ufcs_dpdn_short_staus_ge_ok(uint8_t port)
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{
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return drv_dpdn_short_staus_get(port);
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}
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/*
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* @brief ufcs_phy_get_rx_int
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* @param port
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* @note null
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* @retval rx int flag state
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*/
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__forceinline uint32_t ufcs_phy_get_rx_int(uint8_t port)
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{
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if(port == 0)
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{
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return drv_ufcs0_get_rx_int();
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}
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else
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{
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return drv_ufcs1_get_rx_int();
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}
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}
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/*
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* @brief ufcs_phy_get_tx_int
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* @param port
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* @note null
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* @retval tx int flag state
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*/
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__forceinline uint32_t ufcs_phy_get_tx_int(uint8_t port)
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{
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if(port == 0)
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{
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return drv_ufcs0_get_tx_int();
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}
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else
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{
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return drv_ufcs1_get_tx_int();
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}
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}
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/*
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* @brief ufcs_phy_rx_int_mask
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* @param port
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* @param val
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* @note null
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* @retval null
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*/
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__forceinline void ufcs_phy_rx_int_mask(uint8_t port, uint32_t val)
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{
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if(port == 0)
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{
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drv_ufcs0_rx_int_mask(val);
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}
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else
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{
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drv_ufcs1_rx_int_mask(val);
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}
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}
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/*
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* @brief ufcs_phy_rx_int_clr
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* @param port
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* @param val
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* @note null
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* @retval null
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*/
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__forceinline void ufcs_phy_rx_int_clr(uint8_t port, uint32_t val)
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{
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if(port == 0)
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{
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drv_ufcs0_rx_int_clr(val);
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}
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else
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{
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drv_ufcs1_rx_int_clr(val);
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}
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}
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/*
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* @brief ufcs_phy_tx_int_mask
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* @param port
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* @param val
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* @note null
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* @retval null
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*/
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__forceinline void ufcs_phy_tx_int_mask(uint8_t port, uint32_t val)
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{
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if(port == 0)
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{
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drv_ufcs0_tx_int_mask(val);
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}
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else
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{
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drv_ufcs1_tx_int_mask(val);
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}
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}
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/*
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* @brief ufcs_phy_tx_int_clr
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* @param port
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* @param val
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* @note null
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* @retval null
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*/
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__forceinline void ufcs_phy_tx_int_clr(uint8_t port, uint32_t val)
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{
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if(port == 0)
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{
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drv_ufcs0_tx_int_clr(val);
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}
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else
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{
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drv_ufcs1_tx_int_clr(val);
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}
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}
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/*
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* @brief ufcs_dma_done_clr
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* @param port
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* @param chn_index
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* @note null
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* @retval null
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*/
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__forceinline void ufcs_dma_done_clr(uint8_t port, uint8_t chn_index)
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{
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if(port == 0)
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{
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drv_dma0_done_clr(chn_index);
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}
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else
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{
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drv_dma1_done_clr(chn_index);
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}
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}
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/*
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* @brief ufcs_rx_hard_reset_val_set
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* @param port
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* @param chn_index
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* @note null
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* @retval null
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*/
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__forceinline void ufcs_rx_hard_reset_val_set(uint8_t port, uint8_t chn_index)
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{
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if(port == 0)
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{
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drv_ufcs0_rx_hard_reset_val_set(chn_index);
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}
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else
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{
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drv_ufcs1_rx_hard_reset_val_set(chn_index);
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}
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}
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/*
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* @brief ufcs_phy_callback_init
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* @param ufcs_param
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* @note
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* @retval NULL
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*/
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void ufcs_phy_callback_init(uint8_t port, ufcs_param_s *ufcs_param);
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/*
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* @brief ufcs_phy_ctrl_stop_src_tx
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* @param port
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* @param
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*
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* //all the following condition is met, then the stop command is not effect
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//1 tx packet is processing
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//2. hwrst is processing
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* @retval null
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*/
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void ufcs_phy_ctrl_stop_src_tx(uint8_t port, uint8_t en);
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/*
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* @brief ufcs_handshake_init
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* @param uint8_t port
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* @param NULL
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* @note
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* @retval NULL
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*/
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void ufcs_handshake_init(uint8_t port);
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/*
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* @brief ufcs_handshake_disable
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* @param uint8_t port
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* @param NULL
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* @note
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* @retval NULL
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*/
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void ufcs_handshake_disable(uint8_t port);
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/*
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* @brief ufcs_phy_reg_config
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* @param uint8_t port
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* @param ufcs_param
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* @note
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* @retval NULL
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*/
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void ufcs_phy_reg_config(uint8_t port, ufcs_param_s *ufcs_param);
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/*
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* @brief ufcs_phy_reg_config
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* @param uint8_t port
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* @note
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* @retval NULL
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*/
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void config_ufcs_port(uint8_t port);
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/*
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* @brief send_ufcs_pkt
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* @param uint8_t port
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* @param dma_addr
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* @param ufcs_assist
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* @note
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* @retval NULL
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*/
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void send_ufcs_pkt(uint8_t port, uint32_t dma_addr, ufcs_assist_s *ufcs_assist);
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/*
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* @brief ufcs_phy_send_cable_reset
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* @param NULL
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* @note
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* @retval NULL
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*/
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void ufcs_phy_send_cable_reset(uint8_t port);
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/*
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* @brief ufcs_phy_send_hard_reset
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* @param NULL
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* @note
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* @retval NULL
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*/
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void ufcs_phy_send_hard_reset(uint8_t port);
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/*
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* @brief ufcs_phy_exit_ufcs_mode
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* @param NULL
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* @note
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* @retval NULL
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*/
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void ufcs_phy_exit_ufcs_mode(uint8_t port);
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/*
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* @brief ufcs_ping_follow_baudrate
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* @param ufcs_param
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* @note
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* @retval NULL
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*/
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void ufcs_ping_follow_baudrate(uint8_t port, ufcs_param_s *ufcs_param);
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#endif
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