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177 lines
4.0 KiB
177 lines
4.0 KiB
/**
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******************************************************************************
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* @copyright Copyright (C), 2016-2022, ConvenientPower. Co., Ltd.
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* @file ufcs_prl_define.h
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* @version 1.0
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* @author qing.cheng
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* @date 2022-12-02
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* @brief Header file of UFCS_PRL_DEFINE_H module.
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******************************************************************************
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*/
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#ifndef _UFCS_PRL_DEFINE_H_
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#define _UFCS_PRL_DEFINE_H_
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#include "core_comm.h"
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#include "drv_comm.h"
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#include "ufcs_flag.h"
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#define UFCS_CTRL_PKT 0
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#define UFCS_DATA_PKT 1
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#define UFCS_EXT_PKT 2
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#define T_DET_VALID_MIN 1000
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#define T_DET_VALID_MAX 12000
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#define T_DET1_MIN 1400
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#define T_DET1_MAX 2600
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#define T_DET2_MIN 5600
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#define T_DET2_MAX 10800
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#define HDSK_DEC_TIMES 6
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#define UFCS_TRAINING 0xAA
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#define ufcs_clr_timeout_flag(_port, _timer)\
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do\
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{\
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(_port)->ufcs_flags.ufcs_timer_flag.word &= ~((1u << (_timer)) & 0xfff);\
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}while(0)
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typedef enum
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{
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UFCS_PRL_Rx_Wait_for_PHY_Message = 0,
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// UFCS_PRL_Rx_Check_CRC,
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UFCS_PRL_Rx_Check_MsgNumber,
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UFCS_PRL_Rx_Max
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} ufcs_prl_rx_status_e;
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typedef enum
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{
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UFCS_PRL_Tx_Reset = 0,
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UFCS_PRL_Tx_Wait_for_Msg_Request,
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UFCS_PRL_Tx_Send_Msg,
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UFCS_PRL_Tx_Wait_Response,
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// UFCS_PRL_Tx_Match_MsgNumber,
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UFCS_PRL_Tx_Check_RetryCounter,
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UFCS_PRL_Tx_Max
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} ufcs_prl_tx_status_e;
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typedef enum
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{
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UFCS_PRL_HDSK_Pulse = 0,
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UFCS_PRL_HDSK_Wait_Ping,
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UFCS_PRL_HDSK_RDY,
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UFCS_PRL_HDSK_Max,
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} ufcs_prl_hdsk_status_e;
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typedef enum
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{
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UFCS_PRL_HR_RESET_LAYER = 0,
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UFCS_PRL_HR_WAIT_HARD_RESET_COMPLETE,
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UFCS_PRL_HR_WAIT_HARD_RESET_Max
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} ufcs_prl_hr_status_e;
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typedef enum UFCS_PROCESS_STATUS_e
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{
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UFCS_ENTER = 0,
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UFCS_EXIT,
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} UFCS_PROCESS_STATUS_e;
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typedef enum
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{
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ufcs_prl_rx_entry_status,
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ufcs_prl_rx_exit_status,
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} ufcs_prl_rx_process_status_e;
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typedef enum
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{
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ufcs_prl_tx_entry_status,
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ufcs_prl_tx_exit_status,
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} ufcs_prl_tx_process_status_e;
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typedef enum
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{
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ufcs_prl_hr_entry_status,
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ufcs_prl_hr_exit_status,
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} ufcs_prl_hr_process_status_e;
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typedef enum
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{
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ufcs_prl_hdsk_entry_status,
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ufcs_prl_hdsk_exit_status,
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} ufcs_prl_hdsk_process_status_e;
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typedef union
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{
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uint16_t data16;
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uint8_t byte[2];
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struct
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{
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uint8_t prl_packet_recived_from_pe: 1;
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uint8_t prl_snk_hardreset_recived_from_pe: 1;
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uint8_t prl_cable_hardreset_recived_from_pe: 1;
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uint8_t prl_recived_start_cable_from_pe: 1;
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uint8_t prl_recived_bdrate_not_support: 1;
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uint8_t prl_open_watchdog_recived_from_prl: 1;
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uint8_t prl_recived_start_cable_: 1;
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uint8_t prl_recived_stop_tx_pe: 1;
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uint8_t prl_packet_wait_ack_from_phy: 1;
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uint8_t reserved: 7;
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};
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} ufcs_prl_flags_u;
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typedef union ufcs_prl_int_flags_u
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{
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uint16_t data16;
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uint8_t byte[2];
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struct
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{
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uint8_t prl_hardreset_recived_from_phy: 1;
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uint8_t prl_packet_recived_from_phy: 1;
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uint8_t prl_packet_sent_succ_from_phy: 1;
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uint8_t prl_cable_hardreset_succ_from_phy: 1;
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uint8_t prl_snk_hardreset_succ_from_phy: 1;
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uint8_t prl_recived_msg_error_from_phy: 1;
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uint8_t prl_recived_error_frame_from_phy: 1;
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uint8_t prl_recived_crc_is_ok_from_phy: 1;
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//BYTE1
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uint8_t prl_relay_anck_start_from_prl: 1;
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uint8_t reserved: 7;
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};
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} ufcs_prl_int_flags_u;
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//4 *8 32byte sram calc zxs
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typedef struct
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{
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// ufcs_prl_hr_status_e prl_hr_status;
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// ufcs_prl_hr_process_status_e prl_hr_process_status;
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ufcs_prl_tx_status_e prl_tx_status; // tx status
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ufcs_prl_tx_process_status_e prl_tx_process_status; // tx process status
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ufcs_prl_rx_status_e prl_rx_status; // rx status
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ufcs_prl_rx_process_status_e prl_rx_process_status; // rx process status
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ufcs_prl_hdsk_status_e ufcs_prl_hdsk_status;
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ufcs_prl_hdsk_process_status_e prl_hdsk_process_status;
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} ufcs_prl_status_s;
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#endif
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