CPS/MXWK_美芯微科/common/reg_def/i2c1_master_define.h

#ifndef __I2C1_MASTER_DEFINE_H__
#define __I2C1_MASTER_DEFINE_H__
//-----------------------------------------------------------------------------
// i2c1_master registers definition                            
//-----------------------------------------------------------------------------
#pragma anon_unions

//-----------------------------------------------------------------------------
// registers structures
typedef struct
{
	uint32_t value:8;
	uint32_t reserved_31_8:24;
} REG_i2c1_master_i2cdat_bitfiled_TypeDef;

typedef struct
{
	union {
	__IO	REG_i2c1_master_i2cdat_bitfiled_TypeDef bf;//bitfiled
	__IO	uint32_t word;
	};
} REG_i2c1_master_i2cdat_TypeDef;


typedef struct
{
	uint32_t gc:1;
	uint32_t adr:7;
	uint32_t reserved_31_8:24;
} REG_i2c1_master_i2cadr_bitfiled_TypeDef;

typedef struct
{
	union {
	__IO	REG_i2c1_master_i2cadr_bitfiled_TypeDef bf;//bitfiled
	__IO	uint32_t word;
	};
} REG_i2c1_master_i2cadr_TypeDef;


typedef struct
{
	uint32_t cr:2;
	uint32_t aa:1;
	uint32_t si:1;
	uint32_t sto:1;
	uint32_t sta:1;
	uint32_t ens1:1;
	uint32_t cr2:1;
	uint32_t reserved_31_8:24;
} REG_i2c1_master_i2ccon_bitfiled_TypeDef;

typedef struct
{
	union {
	__IO	REG_i2c1_master_i2ccon_bitfiled_TypeDef bf;//bitfiled
	__IO	uint32_t word;
	};
} REG_i2c1_master_i2ccon_TypeDef;


typedef struct
{
	uint32_t reserved_2_0:3;
	uint32_t sta_code:5;
	uint32_t reserved_31_8:24;
} REG_i2c1_master_i2csta_bitfiled_TypeDef;

typedef struct
{
	union {
	__IO	REG_i2c1_master_i2csta_bitfiled_TypeDef bf;//bitfiled
	__IO	uint32_t word;
	};
} REG_i2c1_master_i2csta_TypeDef;


typedef struct
{
	uint32_t tmout:3;
	uint32_t reserved_6_3:4;
	uint32_t ex_en:1;
	uint32_t reserved_31_8:24;
} REG_i2c1_master_smb_sel_bitfiled_TypeDef;

typedef struct
{
	union {
	__IO	REG_i2c1_master_smb_sel_bitfiled_TypeDef bf;//bitfiled
	__IO	uint32_t word;
	};
} REG_i2c1_master_smb_sel_TypeDef;


typedef struct
{
	uint32_t value:8;
	uint32_t reserved_31_8:24;
} REG_i2c1_master_smb_dst_bitfiled_TypeDef;

typedef struct
{
	union {
	__IO	REG_i2c1_master_smb_dst_bitfiled_TypeDef bf;//bitfiled
	__IO	uint32_t word;
	};
} REG_i2c1_master_smb_dst_TypeDef;


//-----------------------------------------------------------------------------


//-----------------------------------------------------------------------------
// memory map
#define REG_I2C1_MASTER_I2CDAT_BASE                 0X4000C000
#define REG_I2C1_MASTER_I2CADR_BASE                 0X4000C004
#define REG_I2C1_MASTER_I2CCON_BASE                 0X4000C008
#define REG_I2C1_MASTER_I2CSTA_BASE                 0X4000C00C
#define REG_I2C1_MASTER_SMB_SEL_BASE                0X4000C010
#define REG_I2C1_MASTER_SMB_DST_BASE                0X4000C014
//-----------------------------------------------------------------------------


//-----------------------------------------------------------------------------
// declaration
#define REG_I2C1_MASTER_I2CDAT                  ((REG_i2c1_master_i2cdat_TypeDef             *) REG_I2C1_MASTER_I2CDAT_BASE)
#define REG_I2C1_MASTER_I2CADR                  ((REG_i2c1_master_i2cadr_TypeDef             *) REG_I2C1_MASTER_I2CADR_BASE)
#define REG_I2C1_MASTER_I2CCON                  ((REG_i2c1_master_i2ccon_TypeDef             *) REG_I2C1_MASTER_I2CCON_BASE)
#define REG_I2C1_MASTER_I2CSTA                  ((REG_i2c1_master_i2csta_TypeDef             *) REG_I2C1_MASTER_I2CSTA_BASE)
#define REG_I2C1_MASTER_SMB_SEL                 ((REG_i2c1_master_smb_sel_TypeDef            *) REG_I2C1_MASTER_SMB_SEL_BASE)
#define REG_I2C1_MASTER_SMB_DST                 ((REG_i2c1_master_smb_dst_TypeDef            *) REG_I2C1_MASTER_SMB_DST_BASE)
//-----------------------------------------------------------------------------


//-----------------------------------------------------------------------------
// set
#define REG_I2C1_MASTER_I2CDAT_POS                            0
#define REG_I2C1_MASTER_I2CDAT_MSK                            (0x8ul           << REG_I2C1_MASTER_I2CDAT_POS)
#define REG_I2C1_MASTER_I2CDAT_SET(num)                       (((num)          << REG_I2C1_MASTER_I2CDAT_POS              ) & REG_I2C1_MASTER_I2CDAT_MSK)

#define REG_I2C1_MASTER_I2CADR_GC_POS                         0
#define REG_I2C1_MASTER_I2CADR_GC_MSK                         (0x1ul           << REG_I2C1_MASTER_I2CADR_GC_POS)
#define REG_I2C1_MASTER_I2CADR_GC_SET(num)                    (((num)          << REG_I2C1_MASTER_I2CADR_GC_POS           ) & REG_I2C1_MASTER_I2CADR_GC_MSK)

#define REG_I2C1_MASTER_I2CADR_ADR_POS                        1
#define REG_I2C1_MASTER_I2CADR_ADR_MSK                        (0x7ul           << REG_I2C1_MASTER_I2CADR_ADR_POS)
#define REG_I2C1_MASTER_I2CADR_ADR_SET(num)                   (((num)          << REG_I2C1_MASTER_I2CADR_ADR_POS          ) & REG_I2C1_MASTER_I2CADR_ADR_MSK)

#define REG_I2C1_MASTER_I2CCON_CR_POS                         0
#define REG_I2C1_MASTER_I2CCON_CR_MSK                         (0x2ul           << REG_I2C1_MASTER_I2CCON_CR_POS)
#define REG_I2C1_MASTER_I2CCON_CR_SET(num)                    (((num)          << REG_I2C1_MASTER_I2CCON_CR_POS           ) & REG_I2C1_MASTER_I2CCON_CR_MSK)

#define REG_I2C1_MASTER_I2CCON_AA_POS                         2
#define REG_I2C1_MASTER_I2CCON_AA_MSK                         (0x1ul           << REG_I2C1_MASTER_I2CCON_AA_POS)
#define REG_I2C1_MASTER_I2CCON_AA_SET(num)                    (((num)          << REG_I2C1_MASTER_I2CCON_AA_POS           ) & REG_I2C1_MASTER_I2CCON_AA_MSK)

#define REG_I2C1_MASTER_I2CCON_SI_POS                         3
#define REG_I2C1_MASTER_I2CCON_SI_MSK                         (0x1ul           << REG_I2C1_MASTER_I2CCON_SI_POS)
#define REG_I2C1_MASTER_I2CCON_SI_SET(num)                    (((num)          << REG_I2C1_MASTER_I2CCON_SI_POS           ) & REG_I2C1_MASTER_I2CCON_SI_MSK)

#define REG_I2C1_MASTER_I2CCON_STO_POS                        4
#define REG_I2C1_MASTER_I2CCON_STO_MSK                        (0x1ul           << REG_I2C1_MASTER_I2CCON_STO_POS)
#define REG_I2C1_MASTER_I2CCON_STO_SET(num)                   (((num)          << REG_I2C1_MASTER_I2CCON_STO_POS          ) & REG_I2C1_MASTER_I2CCON_STO_MSK)

#define REG_I2C1_MASTER_I2CCON_STA_POS                        5
#define REG_I2C1_MASTER_I2CCON_STA_MSK                        (0x1ul           << REG_I2C1_MASTER_I2CCON_STA_POS)
#define REG_I2C1_MASTER_I2CCON_STA_SET(num)                   (((num)          << REG_I2C1_MASTER_I2CCON_STA_POS          ) & REG_I2C1_MASTER_I2CCON_STA_MSK)

#define REG_I2C1_MASTER_I2CCON_ENS1_POS                       6
#define REG_I2C1_MASTER_I2CCON_ENS1_MSK                       (0x1ul           << REG_I2C1_MASTER_I2CCON_ENS1_POS)
#define REG_I2C1_MASTER_I2CCON_ENS1_SET(num)                  (((num)          << REG_I2C1_MASTER_I2CCON_ENS1_POS         ) & REG_I2C1_MASTER_I2CCON_ENS1_MSK)

#define REG_I2C1_MASTER_I2CCON_CR2_POS                        7
#define REG_I2C1_MASTER_I2CCON_CR2_MSK                        (0x1ul           << REG_I2C1_MASTER_I2CCON_CR2_POS)
#define REG_I2C1_MASTER_I2CCON_CR2_SET(num)                   (((num)          << REG_I2C1_MASTER_I2CCON_CR2_POS          ) & REG_I2C1_MASTER_I2CCON_CR2_MSK)

#define REG_I2C1_MASTER_SMB_SEL_TMOUT_POS                     0
#define REG_I2C1_MASTER_SMB_SEL_TMOUT_MSK                     (0x3ul           << REG_I2C1_MASTER_SMB_SEL_TMOUT_POS)
#define REG_I2C1_MASTER_SMB_SEL_TMOUT_SET(num)                (((num)          << REG_I2C1_MASTER_SMB_SEL_TMOUT_POS       ) & REG_I2C1_MASTER_SMB_SEL_TMOUT_MSK)

#define REG_I2C1_MASTER_SMB_SEL_EX_EN_POS                     7
#define REG_I2C1_MASTER_SMB_SEL_EX_EN_MSK                     (0x1ul           << REG_I2C1_MASTER_SMB_SEL_EX_EN_POS)
#define REG_I2C1_MASTER_SMB_SEL_EX_EN_SET(num)                (((num)          << REG_I2C1_MASTER_SMB_SEL_EX_EN_POS       ) & REG_I2C1_MASTER_SMB_SEL_EX_EN_MSK)

//-----------------------------------------------------------------------------


#endif /*__I2C1_MASTER_DEFINE_H__*/