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237 lines
7.5 KiB
237 lines
7.5 KiB
/**
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******************************************************************************
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* @copyright Copyright (C), 2016-2022, ConvenientPower. Co., Ltd.
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* @file comp_dma.h
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* @version 1.0
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* @author qing.cheng
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* @date 2022-11-01
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* @brief Header file of COMP_DMA_H module.
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******************************************************************************
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*/
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#ifndef _COMP_DMA_H_
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#define _COMP_DMA_H_
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/*******************************************
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DMA内存排布：
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dma通道信息分布(2组每组4个通道)：
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//PORT0
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CH0:0x20000000--------0x2000000F-----PD0--TX
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CH1:0x20000010--------0x2000002F-----PD0--RX
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CH2:0x20000020--------0x20000030-----DPDN0--RX
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CH3:0x20000030--------0x20000040-----DPDN0--TX
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SRAM映射地址
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//PORT0
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0x20000040-------------0x2000007C----PD0--RX
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0x2000007C-------------0x200000B8----PD0--TX
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0x200000B8-------------0x200000F8----DPDN0--RX
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0x200000F8-------------0x2000013C----DPDN0--TX
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//PORT1
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0x2000013C-------------0x20000178----PD1--RX
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0x20000178-------------0x200001B4----PD1--TX
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0x200001B4-------------0x200001F4----DPDN1--RX
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//PORT1
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CH0:0x20000200--------0x20000210-----PD0--TX
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CH1:0x20000210--------0x20000220-----PD0--RX
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CH2:0x20000220--------0x20000230-----DPDN0--RX
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CH3:0x20000230--------0x20000240-----DPDN0--TX
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0x20000240-------------0x20000288----DPDN1--TX
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************************************************/
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#include "core_comm.h"
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#include "drv_dma.h"
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#define PD_DMA_MAX_BUFF_SIZE (60)
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#define UFCS_DMA_RX_MAX_BUFF_SIZE (64)
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#define UFCS_DMA_TX_MAX_BUFF_SIZE (68)
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#define TX_CONFIG_WORD 0xc0400000
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#define RX_CONFIG_WORD 0x0c400000
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#define DMA_CFG_BASE_ADDR_POS 9
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#define DMA_CFG_BASE_ADDR_MASK (0x7F << 9)
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#define DMA_CFG_ADDR_CHN_POS 4
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#define DMA_ADDR_WORD_SET(cfg_buf, addr)\
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do{\
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cfg_buf[0] = (uint32_t)(addr) & 0xFF;\
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cfg_buf[1] = ((uint32_t)(addr) >> 8) & 0xFF;\
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cfg_buf[2] = ((uint32_t)(addr) >> 16) & 0xFF;\
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cfg_buf[3] = ((uint32_t)(addr) >> 24) & 0xFF;\
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}while(0)
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#define DMA_CFG_WORD_SET(cfg_buf, dma_buf_len, ctrl_byte)\
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do{\
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cfg_buf[0] = 0x00;\
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cfg_buf[1] = 0x00;\
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cfg_buf[2] = dma_buf_len;\
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cfg_buf[3] = ctrl_byte;\
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}while(0)
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#define DMA0_CHN_PD_TX 0
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#define DMA0_CHN_PD_RX 1
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#define DMA0_CHN_PRL_RX 2
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#define DMA0_CHN_PRL_TX 3
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#define DMA0_CHN_ADC 4 /*not used*/
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#define DMA1_CHN_PD_TX 0
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#define DMA1_CHN_PD_RX 1
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#define DMA1_CHN_PRL_RX 2
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#define DMA1_CHN_PRL_TX 3
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#define DMA1_CHN_ADC 4 /*not used*/
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// must be align with 0x1FF(start with bit9)
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#define DMA_CFG_BASE_ADDR (uint32_t)0x20000000
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#define DMA_DATA_BASE_ADDR (uint32_t)(DMA_CFG_BASE_ADDR + ((DMA0_CHN_PRL_TX + 1 ) << DMA_CFG_ADDR_CHN_POS)) // start from unused cfg space, chn 7~chn31
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#define DMA1_CFG_BASE_ADDR (uint32_t)0x20000200
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#define DMA1_DATA_BASE_ADDR (uint32_t)(DMA1_CFG_BASE_ADDR + ((DMA1_CHN_PRL_TX + 1) << DMA_CFG_ADDR_CHN_POS))
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/*************************PORT0***********************************/
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/**********************************PD0*****************/
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#define PD0_RX_DATA_REG_ADDR ((uint32_t)REG_PD0_DATA_BASE+1)
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#define PD0_TX_DATA_REG_ADDR ((uint32_t)REG_PD0_DATA_BASE)
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#define PD0_RX_SRAM_MCU_ADDR (DMA_DATA_BASE_ADDR + 0)
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#define PD0_TX_SRAM_MCU_ADDR (PD0_RX_SRAM_MCU_ADDR + PD_DMA_MAX_BUFF_SIZE)
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#define PD0_RX_SRAM_AHB_ADDR ((uint32_t)0x00000000 + PD0_RX_SRAM_MCU_ADDR)
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#define PD0_TX_SRAM_AHB_ADDR ((uint32_t)0x00000000 + PD0_TX_SRAM_MCU_ADDR)
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/*****************************DPDN0**********************/
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#define DPDN0_RX_SRAM_MCU_ADDR (PD0_TX_SRAM_MCU_ADDR + PD_DMA_MAX_BUFF_SIZE)
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#define DPDN0_TX_SRAM_MCU_ADDR (DPDN0_RX_SRAM_MCU_ADDR + UFCS_DMA_RX_MAX_BUFF_SIZE)
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#define DPDN0_RX_SRAM_AHB_ADDR ((uint32_t)0x00000000 + DPDN0_RX_SRAM_MCU_ADDR)
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#define DPDN0_TX_SRAM_AHB_ADDR ((uint32_t)0x00000000 + DPDN0_TX_SRAM_MCU_ADDR)
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#define DPDN0_UFCS_TX_ACK_SRAM_AHB_ADDR DPDN0_TX_SRAM_AHB_ADDR + 64
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////////////////////////////////////////////////// UFCS0 //////////////////////////////////////////////
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#define UFCS0_RX_DATA_REG_ADDR ((uint32_t)REG_UFCS_RX_DAT_BASE)
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#define UFCS0_TX_DATA_REG_ADDR ((uint32_t)REG_UFCS_TX_DAT_BASE)
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////////////////////////////////////////////////// SCP0 //////////////////////////////////////////////
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#define SCP0_RX_DATA_REG_ADDR ((uint32_t)REG_SCP_RX_DATA_BASE)
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#define SCP0_TX_DATA_REG_ADDR ((uint32_t)REG_SCP_TX_DATA_BASE)
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/*************************PORT1***********************************/
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/**********************************PD1*****************/
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#define PD1_RX_DATA_REG_ADDR ((uint32_t)REG_PD_DATA_BASE+1)
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#define PD1_TX_DATA_REG_ADDR ((uint32_t)REG_PD_DATA_BASE)
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#define PD1_RX_SRAM_MCU_ADDR (DPDN0_TX_SRAM_AHB_ADDR + UFCS_DMA_TX_MAX_BUFF_SIZE)
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#define PD1_TX_SRAM_MCU_ADDR (PD1_RX_SRAM_MCU_ADDR + PD_DMA_MAX_BUFF_SIZE)
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#define PD1_RX_SRAM_AHB_ADDR ((uint32_t)0x00000000 + PD1_RX_SRAM_MCU_ADDR)
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#define PD1_TX_SRAM_AHB_ADDR ((uint32_t)0x00000000 + PD1_TX_SRAM_MCU_ADDR)
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/*****************************DPDN1**********************/
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#define DPDN1_RX_SRAM_MCU_ADDR (PD1_TX_SRAM_MCU_ADDR + PD_DMA_MAX_BUFF_SIZE)
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/**/
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#define DPDN1_TX_SRAM_MCU_ADDR (0x00000000 + DMA1_DATA_BASE_ADDR)
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#define DPDN1_RX_SRAM_AHB_ADDR ((uint32_t)0x00000000 + DPDN1_RX_SRAM_MCU_ADDR)
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#define DPDN1_TX_SRAM_AHB_ADDR ((uint32_t)0x00000000 + DPDN1_TX_SRAM_MCU_ADDR)
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#define DPDN1_UFCS_TX_ACK_SRAM_AHB_ADDR DPDN1_TX_SRAM_AHB_ADDR + 64
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////////////////////////////////////////////////// UFCS1 //////////////////////////////////////////////
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#define UFCS1_RX_DATA_REG_ADDR ((uint32_t)REG_UFCS1_RX_DAT_BASE)
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#define UFCS1_TX_DATA_REG_ADDR ((uint32_t)REG_UFCS1_TX_DAT_BASE)
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////////////////////////////////////////////////// SCP1 //////////////////////////////////////////////
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#define SCP1_RX_DATA_REG_ADDR ((uint32_t)REG_SCP1_RX_DATA_BASE)
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#define SCP1_TX_DATA_REG_ADDR ((uint32_t)REG_SCP1_TX_DATA_BASE)
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/******port0**********/
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extern uint8_t pd0_dma_rx_buffer[PD_DMA_MAX_BUFF_SIZE];
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extern uint8_t pd0_dma_tx_buffer[PD_DMA_MAX_BUFF_SIZE];
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extern uint32_t pd0_dma_tx_cfg[4];
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extern uint8_t dpdn0_dma_rx_buffer[UFCS_DMA_RX_MAX_BUFF_SIZE];
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extern uint8_t dpdn0_dma_tx_buffer[UFCS_DMA_TX_MAX_BUFF_SIZE];
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extern uint32_t dpdn0_dma_tx_cfg[4];
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/******port1**********/
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extern uint8_t pd1_dma_rx_buffer[PD_DMA_MAX_BUFF_SIZE];
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extern uint8_t pd1_dma_tx_buffer[PD_DMA_MAX_BUFF_SIZE];
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extern uint32_t pd1_dma_tx_cfg[4];
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extern uint8_t dpdn1_dma_rx_buffer[UFCS_DMA_RX_MAX_BUFF_SIZE];
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extern uint8_t dpdn1_dma_tx_buffer[UFCS_DMA_TX_MAX_BUFF_SIZE];
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extern uint32_t dpdn1_dma_tx_cfg[4];
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/**
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* @brief comp_dma_pd_set_tx_size
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* @note
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* @param port 0/1
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* @param n: send len size
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* @retval None
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*/
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void comp_dma_pd_set_tx_size(uint8_t port, uint16_t n);
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/**
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* @brief comp_dma_dpdn_set_tx_size
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* @note
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* @param port 0/1
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* @param n: send len size
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* @retval None
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*/
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void comp_dma_dpdn_set_tx_size(uint8_t port, uint16_t n);
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/**
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* @brief comp_dma_dpdn_set_tx_size
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* @note
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* @param port 0/1
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* @retval recv num
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*/
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uint8_t comp_dma_dpdn_get_recv_size(uint8_t port);
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/**
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* @brief init dma module & chn
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* @note
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* @param port 0/1
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* @retval None
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*/
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void comp_dma_init(uint8_t port);
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/*
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* @brief comp_dma_pd_init
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* @param port 0/1
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* @note NULL
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* @retval NULL
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*/
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void comp_dma_pd_init(uint8_t port);
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/*
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* @brief comp_dma_ufcs_init
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* @param port 0/1
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* @note NULL
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* @retval NULL
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*/
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void comp_dma_ufcs_init(uint8_t port);
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/*
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* @brief comp_dma_scp_init
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* @param port 0/1
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* @note NULL
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* @retval NULL
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*/
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void comp_dma_scp_init(uint8_t port);
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#endif
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